JP2012134334A - Method for manufacturing laminated device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a laminated device capable of producing the same with a high yield.SOLUTION: The method comprises: a semiconductor wafer preparing step for preparing m sheets of semiconductor wafers ( m is an integer of 3 or more ); a map forming step for forming nondefective unit and a defective unit maps 12A, 12B, 12C, 12D for every semiconductor wafer in m sheets of semiconductor wafers; a combination detecting step for detecting a combination in which the number of defective semiconductor devices 16b included in the semiconductor devices is minimum by selecting and laminating a predetermined number n sheets of semiconductor wafers from the m sheets of semiconductor wafers; a laminated wafer forming step for forming the predetermined number n sheets of semiconductor wafers according the combination of semiconductor wafers detected in the combination detecting step; and a splitting step for splitting the laminated wafer formed in the laminated wafer forming step along a scheduled division line and forming a laminated device in which the predetermined number n sheets of semiconductor devices are laminated.

Description

  The present invention relates to a method for manufacturing a stacked device in which a plurality of semiconductor devices are stacked.

  In the manufacturing process of semiconductor devices, devices such as ICs and LSIs are formed in each region partitioned by dividing lines called streets on the surface of the semiconductor wafer. Then, individual semiconductor devices are manufactured by dividing the semiconductor wafer into chips along the planned dividing lines. The semiconductor device manufactured in this way is widely used in various electric appliances.

  In recent years, along with miniaturization and thinning of electrical equipment, semiconductor device packages are also required to be miniaturized and thin, and higher density of packaging is required. One technique for integrating a plurality of semiconductor devices in one package is a three-dimensional mounting in which a plurality of semiconductor device chips are stacked in the vertical direction and mounted.

  In conventional three-dimensional packaging, wire bonding is used to connect between semiconductor device chips or between a semiconductor device chip and an interposer. In connection by wire bonding, inductance and the like increase by the length of the wiring, so that there is a problem that it is not suitable for high-speed signal exchange, and it is necessary to stack chips so that wires do not touch semiconductor device chips and the like Therefore, there are problems such as difficulty in miniaturization.

  In recent years, as a new three-dimensional mounting technique, a mounting technique using a through-silicon via (TSV) instead of a wire has attracted attention. When the TSV technology is used, since the wiring length is shorter than that of the wire, the wiring resistance and inductance can be greatly reduced, and the power consumption can be greatly reduced.

  As one of the TSV technologies, there is a method in which a plurality of semiconductor wafers are stacked, a through electrode penetrating the stacked semiconductor wafers is formed, and the wafers are connected to each other (Wafer on Wafer: WOW).

JP 2003-249620 A

  However, since most semiconductor wafers contain both good semiconductor devices and several defective semiconductor devices, a plurality of semiconductor wafers are stacked together to form a through electrode that penetrates the stacked semiconductor wafers. The WOW technology for connecting wafers has a problem of poor yield. The above problem becomes significant when a large number of semiconductor wafers are stacked.

  This invention is made | formed in view of such a point, The place made into the objective is providing the manufacturing method of the laminated device which can suppress the deterioration of a yield.

  According to the present invention, there is provided a laminated device manufacturing method for manufacturing a laminated device in which a predetermined number n (n is an integer of 2 or more) of semiconductor devices are laminated, each having a plurality of division lines that intersect at the same position. A semiconductor wafer preparation step of preparing m semiconductor wafers (m is an integer of 3 or more) larger than the n semiconductor wafers each having a semiconductor device formed in each region partitioned by the division line, and the semiconductor wafer preparation step In the m semiconductor wafers prepared in step (b), a map creation step for creating a map of which semiconductor devices are non-defective products and which semiconductor devices are defective products for each semiconductor wafer; Of the combinations in which the predetermined number n of semiconductor wafers are selected from a plurality of semiconductor wafers and stacked, the stacked semiconductor devices A predetermined number n of semiconductor wafers are stacked in accordance with a combination of a combination detection step for detecting a combination in which the number of defective semiconductor devices is the smallest in the semiconductor wafer and a combination of the semiconductor wafers detected in the combination detection step. A laminated wafer forming step, and a dividing step in which the laminated wafer formed in the laminated wafer forming step is divided along the planned dividing line to form a laminated device in which the predetermined number n of semiconductor devices are laminated. A method for manufacturing a laminated device is provided.

  According to the method for manufacturing a laminated device of the present invention, the combination of the laminated devices among all the prepared semiconductor wafers is selected to form the laminated wafer, so that the yield of the laminated devices obtained by dividing the laminated wafer is increased. Can be improved.

It is a figure explaining a semiconductor wafer preparation step. It is a figure explaining a map formation step. FIG. 3A is a diagram showing a combination of a map of the semiconductor wafer A and a map of the semiconductor wafer B, and FIG. 3B is a diagram showing a combination of a map of the semiconductor wafer C and a map of the semiconductor wafer D. 4A is a diagram showing a combination of a map of the semiconductor wafer A and a map of the semiconductor wafer C, and FIG. 4B is a diagram showing a combination of a map of the semiconductor wafer B and a map of the semiconductor wafer D. FIG. 5A is a diagram showing a combination of a map of the semiconductor wafer A and a map of the semiconductor wafer D, and FIG. 5B is a diagram showing a combination of a map of the semiconductor wafer B and a map of the semiconductor wafer C. FIG. 6A is a perspective view of a laminated wafer in which a semiconductor wafer A and a semiconductor wafer C are laminated, and FIG. 6B is a perspective view of a laminated wafer in which a semiconductor wafer B and a semiconductor wafer D are laminated. It is a perspective view which shows the division | segmentation step which divides | segments a laminated wafer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, an explanatory diagram of the semiconductor wafer preparation step is shown. Here, four semiconductor wafers 2A, 2B, 2C, and 2D are prepared.

  Each of the semiconductor wafers 2A to 2D is formed of a silicon wafer, and a semiconductor device 6a such as an IC or LSI is formed in each region partitioned by a plurality of division lines (streets) 4 formed in a lattice shape on the surface thereof. 6b is formed.

  Here, it is assumed that the white semiconductor device 6a is white and the shaded device is a defective semiconductor device 6b. Reference numeral 8 denotes a notch as a mark indicating the crystal orientation of the silicon wafer.

  All semiconductor devices of the semiconductor wafers 2A to 2D are inspected for electrical characteristics in the inspection process, the non-defective semiconductor device 6a is a semiconductor device that has passed the inspection process, and the defective semiconductor device 6b is rejected in the inspection process. Semiconductor device.

  In the method for manufacturing a laminated device of the present invention, after preparing the semiconductor wafers 2A to 2D shown in FIG. 1, a map of which semiconductor devices are non-defective products and which semiconductor devices are defective products in the semiconductor wafers 2A to 2D. The map creation step to be created every time is performed.

  In this map creation step, maps as shown in FIG. 2 are created, and these maps are stored, for example, in the memory of the wafer laminating apparatus. Here, 12A is a map corresponding to the semiconductor wafer 2A shown in FIG. 1, 16a shows the position of the non-defective semiconductor device, 16b shows the position of the defective semiconductor device, and the non-defective semiconductor device of the semiconductor wafer 2A, respectively. 6a corresponds to the defective semiconductor device 6b.

  12B is a map of the semiconductor wafer 2B, and the non-defective semiconductor device position 16a and the defective semiconductor device position 16b correspond to the non-defective semiconductor device 6a and the defective semiconductor device 6b of the semiconductor wafer 2B, respectively.

  12C is a map of the semiconductor wafer 2C, and the non-defective semiconductor device position 16a and the defective semiconductor device position 16b correspond to the non-defective semiconductor device 6a and the defective semiconductor device 6b of the semiconductor wafer 2C, respectively.

  12D is a map of the semiconductor wafer 2D, and the non-defective semiconductor device position 16a and the defective semiconductor device position 16b correspond to the non-defective semiconductor device 6a and the defective semiconductor device 6b of the semiconductor wafer 2D, respectively.

  As described above, in the map creation step of the present invention, a map showing the position of the non-defective semiconductor device and the position of the defective semiconductor device is created for all the semiconductor wafers prepared in the semiconductor wafer preparation step, and these maps are stored in the memory of the wafer stacking apparatus. To store.

  After performing the map creation step, a combination detection step is performed to detect a combination of semiconductor wafers in which the number of defective semiconductor devices 6b contained in a plurality of stacked semiconductor devices is the smallest.

  For example, when a laminated wafer is formed by combining two semiconductor wafers from the four semiconductor wafers 2A to 2D shown in FIG. 1, there are three combinations shown in FIGS.

  FIG. 3 shows a first combination method, FIG. 3A shows a case where a map 12A of the semiconductor wafer 2A and a map 12B of the semiconductor wafer 2B are combined, and FIG. 3B shows the case of the semiconductor wafer 2C. The case where the map 12C and the map 12D of the semiconductor wafer 2D are combined is shown.

  FIG. 4 shows a second combination method, FIG. 4A shows a case where a map 12A of the semiconductor wafer 2A and a map 12C of the semiconductor wafer 2C are combined, and FIG. 4B shows the case of the semiconductor wafer 2B. The case where the map 12B and the map 12D of the semiconductor wafer 2D are combined is shown.

  FIG. 5 shows a third combination method, FIG. 5 (A) shows a case where a map 12A of the semiconductor wafer 2A and a map 12D of the semiconductor wafer 2D are combined, and FIG. 5 (B) shows a case of the semiconductor wafer 2B. The case where the map 12B and the map 12C of the semiconductor wafer 2C are combined is shown.

  In the combination detection step of the present invention, the combination in which the number of defective semiconductor devices 6b contained in the stacked semiconductor devices is minimized is detected. Here, the number of defective semiconductor devices 16b in the semiconductor wafer 2A is A, the number of defective semiconductor devices 16b in the semiconductor wafer 2B is B, the number of defective semiconductor devices 6b in the semiconductor wafer 2C is C, and the semiconductor wafer. Assuming that the number of defective semiconductor devices 6b in 2D is D and the number of defective semiconductor devices whose positions overlap is x, each of the first to third combinations shown in FIGS. The relationship is obtained.

  In the first combination method shown in FIG. 3, FIG. 3A shows A + B−x = 5 + 6-1 = 10, and FIG. 3B shows C + D−x = 10 + 3-3 = 10, Twenty defective laminated devices are obtained.

  In the second combination method shown in FIG. 4, FIG. 4A is A + C−x = 5 + 10−4 = 11, and FIG. 4B is B + D−x = 7 + 3−2 = 8. Includes 19 defective stacked devices.

  In the third combination method shown in FIG. 5, FIG. 5A is A + D−x = 5 + 3-3 = 5, and FIG. 5B is B + C−x = 7 + 10−6 = 11. Includes 16 defective stacked devices.

  Therefore, in the combination detection step of the present invention, the third combination method shown in FIG. 5 is a combination method of combining the semiconductor wafer 2A and the semiconductor wafer 2D, and further combining the semiconductor wafer 2B and the semiconductor wafer 2C. It is detected that a good multilayer device can be manufactured.

  Therefore, in the manufacturing method of the laminated device of the present invention, the laminated wafer 18A is formed by combining the semiconductor wafer 2A and the semiconductor wafer 2D as shown in FIG. 6A according to the laminated combination of the semiconductor wafers detected in the combination detecting step. Then, as shown in FIG. 6B, a laminated wafer 18B is formed by combining the semiconductor wafer 2B and the semiconductor wafer 2C.

  Next, as shown in FIG. 7, while the laminated wafer 18A is sucked and held by a chuck table (not shown) of the cutting apparatus, the laminated wafer is drawn by the cutting blade 20 along the division line 4 extending in the first direction of the laminated wafer 18A. The dividing groove 22 is formed by cutting 18A.

  After the formation of the dividing grooves 22 along all the planned dividing lines 4 extending in the first direction, the chuck table (not shown) is rotated by 90 degrees and then extended in the second direction orthogonal to the first direction. The laminated wafer 18A can be divided into individual laminated devices by forming the same divided grooves 22 along all the planned division lines 4 to be performed.

  The same applies to the laminated wafer 18B shown in FIG. 6B, and the division grooves 22 are formed along all the division lines 4 extending in the first direction and the second direction orthogonal to the first direction. Thus, the laminated wafer 18B can be divided into individual laminated devices.

  In the above-described embodiment, the example in which two semiconductor wafers are stacked from among the four semiconductor wafers 2A to 2D has been described. However, the manufacturing method of the stacked device of the present invention is not limited to this, In particular, when n (n is an integer of 2 or more) semiconductor wafers are stacked, the same applies to the case where an optimal combination is obtained from m (m is an integer greater than n) semiconductor wafers. it can.

2A, 2B, 2C, 2D Semiconductor wafer 4 Scheduled line (street)
6a Non-defective semiconductor device 6b Defective semiconductor device 12A, 12B, 12C, 12D Map 16a Non-defective semiconductor device position 16b Defective semiconductor device position 18A, 18B Multilayer semiconductor wafer 20 Cutting blade

Claims (1)

A manufacturing method of a laminated device for producing a laminated device in which a predetermined number n (n is an integer of 2 or more) semiconductor devices are laminated,
A plurality of semiconductor wafers each having a plurality of division lines intersecting at the same position, each having a semiconductor device formed in each region partitioned by the division lines (m is an integer greater than or equal to 3) A semiconductor wafer preparation step to be prepared;
A map creation step of creating a map of which semiconductor devices are non-defective and which are defective in each of the m semiconductor wafers prepared in the semiconductor wafer preparation step;
After performing the map creation step, among the combinations in which the predetermined number n of semiconductor wafers are selected from the m semiconductor wafers and stacked, the number of defective semiconductor devices included in the stacked semiconductor devices is the highest. A combination detection step for detecting fewer combinations;
A laminated wafer forming step of forming the laminated wafer by laminating the predetermined number n of semiconductor wafers according to the combination of the semiconductor wafers detected in the combination detecting step;
A dividing step of dividing the laminated wafer formed in the laminated wafer forming step along the division planned line to form a laminated device in which the predetermined number n of semiconductor devices are laminated;
The manufacturing method of the laminated device characterized by comprising.

Images