CN102339646B - Detector for discontinuous type layer identification numbers of three-dimensional (3D) chips and method thereof - Google Patents
Detector for discontinuous type layer identification numbers of three-dimensional (3D) chips and method thereof Download PDFInfo
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- CN102339646B CN102339646B CN201010231041.3A CN201010231041A CN102339646B CN 102339646 B CN102339646 B CN 102339646B CN 201010231041 A CN201010231041 A CN 201010231041A CN 102339646 B CN102339646 B CN 102339646B
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Abstract
The invention relates to detector for discontinuous type layer identification numbers of three-dimensional (3D) chips and a method thereof. The detector is a detector which is used for a 3D chip of each layer of an N-layer stacked component. The detector comprises a 2-divided circuit, a first comparator, a second comparator, a first add/sub circuit and a second add/sub circuit, wherein the 2-divided circuit is coupled to a (N-1) signal; the first comparator is coupled to the 2-divided circuit, an input A of the first comparator is coupled to an initial layer number signal, and an input B of the first comparator is coupled to an output of the 2-divided circuit; the second comparator is coupled to the initial number of layers through an input A of the second comparator, and a num is coupled to an input B of the second comparator; the first add/sub circuit is coupled to the num through an input A of the first add/sub circuit, is coupled to the first comparator through an input B of the first add/sub circuit and is coupled to the second comparator through an input '+/-' signal of the first add/sub circuit; and the second add/sub circuit is coupled to the first comparator through an input A of the second add/sub circuit and is coupled to the num through an input B of the second add/sub circuit.
Description
Technical field
The present invention is about a kind of three-dimensional stack chip assembly, and there is the discontinuous kenel layer identiflication number detecting device about a kind of three-dimensional chip in special system.
Background technology
The portable electronic device of coming in, for example mobile phone and non-volatility semiconductor memory media (for example integrated circuit memory card), minification designs or manufactures, and the minimizing of newly-increased demand wish is used for the number of parts of equipment and media and dwindles its size.Therefore,, in semi-conductor industry, the encapsulation technology of integrated circuit has advanced to and has met miniaturization and the demand of following reliability.For example, the demand of miniaturization and cause the accelerated development of encapsulation technology, makes it have the similar size to semiconductor chip.Moreover then the importance of reliability in encapsulation technology is to promote the then efficiency of processing procedure, and after completing, improve machinery and electrical fiduciary level in then processing procedure.Therefore, existing considerable work is to develop packaged semiconductor efficiently.The encapsulation that meets the demand comprises: the chip size packages (CSP) with the rough package size that equals semi-conductor chip, have multiple semiconductor chips to include heavy chip package more than a single encapsulation in, and multiple packaging body storehouse and the storehouse that is incorporated into a monolithic structure dress encapsulate.
Along with the development of technology, the increase of the relative required storage volume of response memory, and the semiconductor subassembly (multiple chip assembly) of proposition storehouse kenel, it has semiconductor integrated circuit chip storehouse together.In other words, it is the storehouse kenel semiconductor subassembly that provides at least two SIC (semiconductor integrated circuit) assembly storehouses to be formed, each has specification and comprises semiconductor integrated circuit (IC) chip, wherein each SIC (semiconductor integrated circuit) assembly comprises that a conductor passes wherein, and SIC (semiconductor integrated circuit) assembly is electrically connected by conductor, and above-mentioned specification value comprises that the size of the superiors or orlop SIC (semiconductor integrated circuit) assembly is maximum or minimum.Therefore, storehouse kenel semiconductor subassembly has a plurality of chip stacks in 1 vertical direction.In storehouse kenel semiconductor subassembly, chip system for example sees through and is electrically connected through the connector (plugs) of chip.Therefore, selecting the storehouse memory chip of a suitable same structure is a important work.If a storehouse kenel semiconductor subassembly completes manufacture, chip can be individually by operational testing, and only normal chip can be selected and storehouse.
One provides technology connected vertically to be called silicon wafer perforation (TSV), and it has become a promising solution of three-dimensional heap stack component.In above-mentioned technology, vertically connect linear system and form through wafer, and make to be linked up between stack chip.A relevant paper can be " utilizing the three-dimensional DDR3 DRAM (Dynamic Random Access Memory) of 8 kilomegabits of silicon wafer puncturing technique " (IEEE, JOURNAL OF SOLID-STATE CIRCUITS, VOL.45, NO.1, JANUARY2010) with reference to title.In this paper, the proposition that has a silicon wafer perforation Three-Dimensional Dynamic random access memory has been the restriction that overcomes traditional modular approach.It also discloses how to design this structure and data routing.It also discloses the silicon wafer perforation connectivity inspection and the restorative procedure that comprise 3-D technology, and power noise reduction method.Silicon wafer perforation can see through simple mode and form after dispatching from the factory, and therefore integrates without separately add special processing procedure during normal processing procedure.Chip identification system normally distributes.
After identical or different chip stack forms three-dimensional chip, for in selecting a chip of wanting to operate more than 3-D integrated circuit assembly between heavy chip, in the time that system operates, each chip of 3-D integrated circuit assembly must confirm that its layer of identiflication number is to select specifying chip to operate.Past, existing many methods of confirming layer identiflication number proposed, but it not only increases cost, and the stack chip that does not overcome more 3-D integrated circuit assembly has more multielectrode problem.For example, the U.S.'s 20070126105 patents that Er Bida internal memory company applies for, disclose a kind of stacked-type semiconductor internal memory modular and choose circuit chip.It provides a stacked-type semiconductor internal memory modular, when select a semi-conductor chip of wanting between a plurality of stacked-type semi-conductor chips, the a plurality of chip identification numberings that differ from one another can produce automatically by the function circuit of a plurality of connections that are arranged in series, and the semi-conductor chip of wanting can by be assigned to each semi-conductor chip unique identiflication number and positively select, its be utilize semi-conductor chip to there is identical structure and without utilize complicated structure or especially control.In known techniques, M be arranged in series between the increment circuit connecting one of last increment circuit calculate output can be for determining the number M of semi-conductor chip.Accordingly, in the time that the number of stacked-type semiconductor subassembly is unknown, the semi-conductor chip of correct number can positively be confirmed.Further known techniques is the U.S. the 7th, 494, No. 846 patents, and it is disclosed by Taiwan semiconductor manufacturing company, applies on March 9th, 2007.Its exposure comprises the first semiconductor grain and second semiconductor grain identical with the first semiconductor grain.The first semiconductor grain comprises that one first identification circuit and first a plurality of I/o pads are formed on the surface of the first semiconductor grain.The second semiconductor grain comprises one second identification circuit, and wherein the programming of the first identification circuit and the second identification circuit differs from one another, and second a plurality of I/o pads are formed on the surface of the second semiconductor grain.Each of first a plurality of I/o pads is perpendicular alignmnet and be connected to second corresponding a plurality of I/o pads.The second semiconductor grain is perpendicular alignmnet and is welded on the first semiconductor grain.
The invention provides a kind of method of three dimensional integrated circuits identification of novelty.
Summary of the invention
One of the present invention viewpoint is method and the framework of the discontinuous kenel detecting device that a kind of three-dimensional chip heap stack component is provided.
A kind of three-dimensional chip detecting device of every one deck for N layer stack assembly, comprising: one except two circuit, couple one (N-1) signal; One first comparer, couples except two circuit, and wherein an input A couples an initiation layer and counts signal, and one of first comparer input B couples except the output of one of two circuit; One second comparer, couples the initial number of plies by one of second comparer input A, and a num couples one of second comparer input B; One first plus-minus circuit, couples num by one of first plus-minus circuit input A, couples the first comparer by one of first plus-minus circuit input B, and couples the second comparer by one of first plus-minus circuit input " +/-" signal; And one second plus-minus circuit, by one of second plus-minus circuit input A and couple the first comparer, by one of second plus-minus circuit input B and couple num.
Wherein the output A of the first comparer equals the output B of the first comparer, and one of first comparer is output as 0; The output A of the first comparer is not equal to the output B of the first comparer, and one of first comparer is output as 1.
Above-mentioned detecting device more comprises one-plus-one circuit, couples initiation layer and counts between signal and lower one deck initiation layer number.
Wherein the output A of the second comparer is not equal to the output B of the second comparer, and one of second comparer is output as 0.The output A of the second comparer equals the output B of the second comparer, and one of first comparer is output as 1.Wherein one of second plus-minus circuit input " +/-" signal, one of coupling second comparer output " +/-" signal.Wherein, when input " +/-" signal is that one of 1, the first plus-minus circuit is output as (A+B), one of second plus-minus circuit is output as (A+B); When input " +/-" signal is that one of 0, the first plus-minus circuit is output as (A-B), one of second plus-minus circuit is output as (A-B).Finally, one deck identiflication number system is from the second plus-minus circuit output.
A kind of method of one deck identiflication number of three-dimensional chip of every one deck that detects N layer stack assembly, comprising: be incremented to (N-1) and produce an initial number of plies from 0 by one of every one deck detecting device; Specify one of this every one deck num by N/2, be incremented to a quotient and be decremented to 0 from quotient from 0 by detecting device respectively subsequently, and getting the num of quotient as every one deck; Specify " +/-" to every one deck by detecting device and based on num with the initial number of plies; And produce one deck identiflication number in every one deck by detecting device and based on num, the initial number of plies with " +/-".
Brief description of the drawings
Said modules, and further feature of the present invention and advantage, by read hold within embodiment and graphic after, will be more obvious:
Fig. 1 shows the process flow diagram of one of the identiflication number detecting device according to the present invention embodiment.
Fig. 2 shows the functional block diagram of the present invention's detecting device.
Fig. 3 shows the present invention's the functional block diagram with six layer stack assemblies.
Primary clustering symbol description:
100 steps
110 steps
120 steps
130 steps
200 detecting devices
210 except two (frequently) circuit
220 first comparers
230 add a circuit
240 second comparers
250 first plus-minus circuit
260 second plus-minus circuit
Embodiment
The present invention is specified in down its preferred embodiment of cooperation and the diagram of enclosing.Should the person of understanding be that preferred embodiments all in the present invention is only the use of illustration, be not in order to restriction.Therefore the preferred embodiment in literary composition, the present invention also can be widely used in other embodiment.And the present invention is not limited to any embodiment, should be with the claim of enclosing and equivalent fields thereof and determine.
As shown in Table 1, detection layers identiflication number (layer ID) organization method comprises a first step 100, add a circuit by one of every one deck and define each initiation layer numbering and offer every one deck from 0 to (N-1), wherein pile stack component and there is N layer chip.Reference table one, the first row represents the layer numbering of every one deck.If heap stack component has 6 layers of chip, initiation layer is numbered 0 to 5 and offers respectively every one deck.Next, in step 110, detecting device is specified the order of n um, and its rule is for being incremented to N/2 (getting quotient, no matter remainder) from 0, is decremented to 0 again after repeating once from N/2.For example, from table one, initiation layer is numbered 0 to 5.Then, N is 5, and the num of every one deck is incremented to N/2 from 0, and is then decremented to 0 from N/2.Its order can be turned around.In other words, increase progressively from 0 to the 2 (5/2=2+1/2 of 1 order system; Round numbers 2), 1 the order system from 2 to 0 of successively decreasing.Num order can reference table one the second row, wherein num is respectively 0,1,2,2,1,0.
Table one
Next,, in step 120, determine whether initiation layer numbering equals num.If initiation layer numbering equals num, detecting device specifies addition ("+") to this layer, otherwise specifies subtraction ("-") to this layer.This work can be carried out by adder-subtractor (add/sub device), and it will narrate in subsequent figure 2 and Fig. 3.Afterwards, in step 130, detecting device 200 is according to symbol "+" or "-" and by increasing progressively (or subtracting) even number and odd number to redefine a layer identiflication number, and separates layers identiflication number is two groups by this, comprise an odd number group and an even number group, the fourth line of reference table one.In an example, layer identiflication number is 0,2,4,1,3,5.The kenel of this kind of layer identiflication number is called discontinuous kenel layer identiflication number.Table two is another example, wherein has number of layers from 0 to 8, and heap stack component has 9 layers of chip.N equals 8, num system from 0 to 4 and increases progressively, and follows from 4 to 0 and successively decrease.As a result, layer identiflication number is split up into even number group 0,2,4,6,8 and odd number group 1,3,5,7.
Table two
One of the detecting device of every one deck (N) of Fig. 2 display stack stack component embodiment.Detecting device 200 comprises that one is coupled to one (N-1) signal except two (frequently) circuit 210.One first comparer 220 sees through its input B and couples except two circuit 210, and its input A couples one deck signal (N-1).When input A is while equaling to input B, the first comparer 220 be output as 0.On the contrary, when input A is not equal to input when B, the first comparer 220 be output as 1.Adding a circuit 230 begins between the number of plies at the beginning of being coupled to the 1 initial number of plies of this layer and next (or last) layer.By adding a circuit 230, the number of plies that begins at the beginning of lower one deck will be than one of current this layer many 1.
One second comparer 240 couples the initial number of plies by its input A, and a num couples the input B of the second comparer 240.The function of the second comparer 240 is to determine that with the input of the initial number of plies symbol of each respective layer is "+" or "-" according to num.When input A is not equal to input when B, the second comparer 240 be output as 0.On the other hand, when input A is while equaling to input B, the second comparer 240 be output as 1.
Next, one first plus-minus circuit (Add/sub circuit) 250 couples num by its input A, couples the first comparer 220 via input B, and couples the second comparer 240 via the 3rd input " +/-".Input " +/-" end of the first plus-minus circuit 250 couples the output signal of the second comparer 240.When input " +/-" is be output as (A+B) of 1, the first plus-minus circuit 250.On the contrary, when input " +/-" be output as (A-B) of 0, the first plus-minus circuit 250.The first plus-minus circuit 250 is for determine (A+B) or (A-B) according to the output of the input of num and the first comparer 220.In other words, input, the first comparer 220 and the second comparer 240 based on num, plus-minus signal can see through the first plus-minus circuit 250 and specify.
One second plus-minus circuit 260 couples the first comparer 220 by the first input A, couples num via the second input B.Moreover the 3rd input " +/-" of the second plus-minus circuit 260 couples output " +/-" signal of the second comparer 240.When input " +/-" is be output as (A+B) of 1, the second plus-minus circuit 260.On the contrary, when input " +/-" be output as (A-B) of 0, the second plus-minus circuit 260.Layer identiflication number will be exported from the second plus-minus circuit 260.In other words, the input " +/-" of input, num and the second comparer 240 based on the initial number of plies, the second plus-minus circuit 260 is the identiflication number for determining each corresponding layer.
By the method for utilizing in Fig. 2 set detecting device and Fig. 1, therefore layer identiflication number will be defined.Fig. 3 shows the example of the heap stack component with six layers.The superiors, for example, the initial number of plies (N-1) is 5, feed-in is removed two circuit 210 by it, and output 2.As can be found from the table 1, num is 0, and the initial number of plies is also 0.Because the input of A is 2, input B is 0, and A is not equal to B, and therefore the output of the first comparer 220 will be 1.But because the input of A equals to input B, therefore the output of the second comparer 240 will be 1.The communication wire of every one deck can bore a hole to form by silicon wafer.
Input A, input B and the input " +/-" of the first plus-minus circuit 250 are respectively 0,1,1, therefore the-add and subtract circuit 250 be output as 1.Similarly, the input A of the second plus-minus circuit 260, input B and input " +/-" are respectively 0,0,1, therefore second add and subtract circuit 260 be output as 0, it is the layer identiflication number of current this layer.
By utilizing identical method, the layer of lower one deck and num are 1, and by the above-mentioned method of operation, the second plus-minus circuit 260 of lower one deck be output as 2, it is the layer identiflication number of lower one deck.The identiflication number of other layer can see through identical mode and obtain.Therefore be no longer described in detail.
One embodiment is the present invention's 1 example or example.Be described in it " embodiment " in instructions, " some embodiment " or " other embodiment " mean describe and one of be linked in this embodiment in the involved minimum embodiment of specific characteristic, structure or characteristic, but not all embodiment are all essential.The narration of the difference such as " embodiment " or " some embodiment " means and nonessential this some embodiment that mention.It should be noted that in the specific embodiment of narrating above about the present invention, different characteristic sometimes can be gathered in a single embodiment, graphic or narration and is in order to simplified illustration and helps the understanding to one or more different aspect of the present invention.But this exposure method should not be used to the invention category that reflection is asked, thereby the feature in described example is added in each claim.Otherwise, can be less than all features in the above-mentioned single embodiment disclosing in following the present invention's that claim reflects viewpoint.Therefore, described embodiment is contained in claim system, and each claim itself all can be considered the present invention's 1 independent embodiment.
Claims (10)
1. for the three-dimensional chip detecting device of every one deck of N layer stack assembly, it is characterized in that comprising:
One except two circuit, couple one (N-1) number of plies signal;
One first comparer, couples this except two circuit, and wherein an input A couples an initiation layer and counts signal, and one of this first comparer input B couples this except the output of one of two circuit;
One second comparer, couples this initiation layer by one of this second comparer input A and counts signal, and a num couples one of this second comparer input B, and this num is order signal;
One first plus-minus circuit, couple this num by one of this first plus-minus circuit input A, couple this first comparer by one of this first plus-minus circuit input B, and couple this second comparer by one of this first plus-minus circuit input " +/-" signal; And
One second plus-minus circuit, couples this first comparer by one of this second plus-minus circuit input A, couples this num by one of this second plus-minus circuit input B;
Wherein this detecting device is according to this input " +/-" signal and by increasing progressively or subtract even number and odd number to redefine a layer identiflication number, by this separately this layer of identiflication number be two groups to form discontinuous kenel layer identiflication number.
2. the three-dimensional chip detecting device of every one deck for N layer stack assembly as claimed in claim 1, is characterized in that this input A of this first comparer equals this input B of this first comparer, and one of this first comparer is output as 0; This input A of this first comparer is not equal to this input B of this first comparer, and one of this first comparer is output as 1.
3. the three-dimensional chip detecting device of every one deck for N layer stack assembly as claimed in claim 1, is characterized in that more comprising one-plus-one circuit, couples that this initiation layer is counted signal and lower one deck initiation layer is counted between signal.
4. the three-dimensional chip detecting device of every one deck for N layer stack assembly as claimed in claim 1, is characterized in that this input A of this second comparer is not equal to this input B of this second comparer, and one of this second comparer is output as 0; This input A of this second comparer equals this input B of this second comparer, and one of this second comparer is output as 1.
5. the three-dimensional chip detecting device of every one deck for N layer stack assembly as claimed in claim 1, is characterized in that one of this second plus-minus circuit input " +/-" signal, one of this second comparer that is coupled output " +/-" signal.
6. the three-dimensional chip detecting device of every one deck for N layer stack assembly as claimed in claim 1, it is characterized in that working as this input " +/-" signal is 1, one of this first plus-minus circuit is output as (A+B), and one of this second plus-minus circuit is output as (A+B); When this input " +/-" signal is 0, one of this first plus-minus circuit is output as (A-B), and one of this second plus-minus circuit is output as (A-B); Wherein one deck identiflication number system is from this second plus-minus circuit output.
7. a method that detects the layer identiflication number of every one deck of N layer stack assembly, is characterized in that comprising:
By one of this every one deck detecting device from 0 be incremented to (N-1) and produce an initial number of plies;
Specify one of this every one deck num by N/2, be incremented to a quotient and be decremented to 0 from this quotient from 0 by this detecting device respectively subsequently, and get this quotient this num as this every one deck, the quotient that this quotient is N/2;
By this detecting device and based on this num and this initial number of plies and specify input " +/-" signal to this every one deck; And
Produce one deck identiflication number in this every one deck by this detecting device and based on this num, this initial number of plies and this input " +/-" signal;
Wherein this detecting device is according to this input " +/-" signal and by increasing progressively or subtract even number and odd number to redefine a layer identiflication number, by this separately this layer of identiflication number be two groups to form discontinuous kenel layer identiflication number.
8. the method for the layer identiflication number of every one deck of detection N layer stack assembly as claimed in claim 7, is characterized in that this layer of identiflication number of this every one deck comprises an odd number group and an even number group.
9. the method for the layer identiflication number of every one deck of detection N layer stack assembly as claimed in claim 7, is characterized in that this detecting device comprises:
One except two circuit, couple one (N-1) number of plies signal;
One first comparer, couples this except two circuit, and wherein an input A couples an initiation layer and counts signal, and one of this first comparer input B couples this except the output of one of two circuit;
One second comparer, couples this initiation layer by one of this second comparer input A and counts signal, and a num couples one of this second comparer input B, and this num is order signal;
One first plus-minus circuit, couple this num by one of this first plus-minus circuit input A, couple this first comparer by one of this first plus-minus circuit input B, and couple this second comparer by one of this first plus-minus circuit input " +/-" signal; And
One second plus-minus circuit, couples this first comparer by one of this second plus-minus circuit input A, couples this num by one of this second plus-minus circuit input B.
10. the method for the layer identiflication number of every one deck of detection N layer stack assembly as claimed in claim 7, this input " +/-" signal that it is characterized in that this every one deck is to determine by this second comparer, and this layer of identiflication number system of this every one deck determines by this second plus-minus circuit.
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| JP2003059285A (en) * | 2001-08-13 | 2003-02-28 | Mitsubishi Electric Corp | Semiconductor memory and grasping method for number of times of rewriting |
| CN101641747A (en) * | 2008-01-28 | 2010-02-03 | 株式会社东芝 | Semiconductor memory device |
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| JP4122750B2 (en) * | 2001-10-24 | 2008-07-23 | 沖電気工業株式会社 | Semiconductor memory device and data writing method of semiconductor memory device |
| JP4799157B2 (en) * | 2005-12-06 | 2011-10-26 | エルピーダメモリ株式会社 | Multilayer semiconductor device |
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| JP2003059285A (en) * | 2001-08-13 | 2003-02-28 | Mitsubishi Electric Corp | Semiconductor memory and grasping method for number of times of rewriting |
| CN101641747A (en) * | 2008-01-28 | 2010-02-03 | 株式会社东芝 | Semiconductor memory device |
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