CN104766828A - Wafer three-dimensional integration method - Google Patents
Wafer three-dimensional integration method Download PDFInfo
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- CN104766828A CN104766828A CN201510148917.0A CN201510148917A CN104766828A CN 104766828 A CN104766828 A CN 104766828A CN 201510148917 A CN201510148917 A CN 201510148917A CN 104766828 A CN104766828 A CN 104766828A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
The invention relates to the field of semiconductor manufacturing, in particular to a wafer three-dimensional integration method. According to the method, wafers containing chips with different processes and different functions can be integrated to a wafer-stage heterogeneous-medium three-dimensional structure, the functions of the chips are improved to a large scale while the sizes of the chips are kept, metal interconnection between the function chips is greatly shortened, and heating, consumption and delay are reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of three-dimensional integrated method of wafer.
Background technology
Constantly reducing of integrated circuit (IC)-components makes integrated level improve constantly, at present can be integrated more than 1,000,000,000 transistors on the chip area of every square centimeter, and the total length of metal interconnecting wires reaches tens kilometers especially.This not only makes wiring become complex, the more important thing is that metal interconnected delay, power consumption, noise etc. all constantly increase along with the reduction of characteristic size, particularly globally interconnected RC (resistance capacitance) postpones, and has had a strong impact on the performance of integrated circuit.In addition, dynamic power consumption is directly proportional to the load capacitance value of circuit, in the dynamic power consumption of current mainstream high performance microprocessor, has and exceedes that half all causes by interconnection line.The method of current solution interconnect delay increases a series of buffer on globally interconnected line, and adding due to a large amount of buffer, the power consumption of circuit increases considerably, and namely utilizes power consumption to exchange speed for.The use of copper-connection and end K medium makes series resistance and parasitic capacitance decrease, and makes technique develop into 90nm by 130nm and overall performance increases, and introduces super low-K dielectric and also can only maintain technological development to 65nm node.Therefore, the metal interconnected transistor that replaced becomes the principal element determining performance of integrated circuits.
Chip system (SoC, System on a Chip) technology wishes the repertoire realizing system on a single chip, as array, simulation, radio frequency, photoelectricity and MEMS (Microelectromechanical Systems, MEMS (micro electro mechanical system)), in SoC development, maximum difficulty is different process compatible problem, such as realize SoC and may need the technique such as standard C OMS, RF, Bipolar and MEMS, the backing material of these manufacturing process is all different, hardly may by its Integrated manufacture on a logical chip.Even if the module that backing material is identical, the manufacture feasibility of each circuit module also to be considered in the mill.This on the one hand can not to the manufacture feasibility of each circuit module.This can not optimize each circuit module on the one hand fully, on the other hand in order in one plane realize multiple module, needs to increase mask plate quantity, arranges mutually to limit during process sequence, certainly will increase the cost that circuit manufactures, the raising of limiting performance.Therefore, the chip of current multifunction module remains discrete, and the various advantages of SoC still rest on stage of imagination due to the restriction manufactured.
Three-dimensional interconnection is on the basis of planar circuit, utilize the third dimension to realize the integrated of multilayer device in one single chip, namely be divided into some functional modules relevant to be in logic distributed in multiple adjacent chip layer a large planar circuit, the three-dimensional perpendicular interconnection then by penetrating substrate is integrated by multilayer chiop.Three-dimensional interconnection can realize the Vertical collection of multi-chip of different functions, different process, significantly reduces globally interconnected length, thus the power consumption significantly reducing interconnect delay, improve integrated circuit speed, reduce chip.Three-dimensional interconnection can the integrated circuit of integrated multi-layer different process or various substrates material, and the SoC for heterogeneous chip provides good solution.Three-dimensional interconnection is all physical interconnections, can solve heterogeneous integrated, the problem such as high-bandwidth communication and interconnect delay of multi-chip.
But existing three-dimensional is integrated, is mainly carried out at package level (package level) in the integrated inside of three-dimensional and outside connection by TSV (Though Silicon Via, the silicon is bored a hole) packaged type such as structure 13 and tin ball 16.As depicted in figs. 1 and 2, be difficult to realize in wafer scale (waferlevel), hinder the development of the further integrated level of SoC, this is that those skilled in the art are unwilling to see.
Summary of the invention
In view of the above problems, the invention provides a kind of three-dimensional integrated method of wafer.
The technical scheme that technical solution problem of the present invention adopts is:
The three-dimensional integrated method of wafer, wherein, comprising:
The bonding wafer that one is provided with interconnect area and lead areas is provided, metal connection structure and metal level is provided with in above-mentioned bonding wafer, the metal level of mutually insulated is electrically connected by above-mentioned metal connection structure, and the part surface of above-mentioned metal connection structure is exposed to the upper surface of above-mentioned bonding wafer;
On above-mentioned bonding wafer, prepare a metallic film, above-mentioned metallic film covers the surface that above-mentioned metal connection structure exposes;
Remove the described metallic film of part, to form the metal interconnecting layer be electrically connected with metal connection structure in above-mentioned interconnection region and metal wiring layer adjacent metal interconnects structure in above-mentioned lead areas be electrically connected.
The three-dimensional integrated method of above-mentioned wafer, wherein, above-mentioned bonding wafer comprises the first wafer and the second wafer, and above-mentioned first wafer comprises the first silicon substrate layer and a BEOL dielectric layer; Second wafer comprises the second silicon substrate layer and the 2nd BEOL dielectric layer, and above-mentioned second integrated circuit layer covers the upper surface of above-mentioned first integrated circuit layer.
The three-dimensional integrated method of above-mentioned wafer, wherein, any above-mentioned metal connection structure is all electrically connected two above-mentioned metal levels.
The three-dimensional integrated method of above-mentioned wafer, wherein, any above-mentioned metal connection structure is electrically connected two above-mentioned metal levels, lays respectively in an above-mentioned BEOL dielectric layer and in the 2nd BEOL dielectric layer.
The three-dimensional integrated method of above-mentioned wafer, wherein, the preparation technology of above-mentioned metal connection structure is: the etching technics of through hole after the etching technics of groove or first groove after first through hole.
The three-dimensional integrated method of above-mentioned wafer, wherein, after above-mentioned first through hole, the etching technics of groove comprises:
Etch above-mentioned second silicon substrate layer, above-mentioned 2nd BEOL dielectric layer and an above-mentioned BEOL dielectric layer, to form the through hole exposed by above-mentioned layer on surface of metal;
On basis based on above-mentioned through hole, etching is positioned at any two the second silicon substrate layer needing the metal layer be electrically connected by above-mentioned metal connection structure, to form above-mentioned groove.
The three-dimensional integrated method of above-mentioned wafer, wherein, after above-mentioned first groove, the etching technics of through hole comprises:
Etching is positioned at any two the second silicon substrate layer needing the metal layer be electrically connected by above-mentioned metal connection structure, to form groove;
On basis based on above-mentioned groove, etching is positioned at the 2nd BEOL dielectric layer and a BEOL dielectric layer of any above-mentioned metal layer, to form above-mentioned groove.
The three-dimensional integrated method of above-mentioned wafer, wherein, after above-mentioned first through hole, after the etching technics of groove or first groove, the etching technics of through hole also comprises:
After forming above-mentioned groove, in above-mentioned groove, fill metal material.
The three-dimensional integrated method of above-mentioned wafer, wherein, the material of above-mentioned metal material is copper, aluminium, tin or tungsten.
The three-dimensional integrated method of above-mentioned wafer, wherein, the material of above-mentioned metal lead wire is the composite material of metal or metal and metal nitride.
Technique scheme tool has the following advantages or beneficial effect:
By method of the present invention can by comprising different process, the wafer of chip of difference in functionality is integrated in a heterogeneous three-dimensional structure of wafer scale, while maintaining chip volume, the function of extensive raising chip, what significantly shorten between each functional chip is metal interconnected, reduce heating, power consumption, with postpone, improve the bandwidth between each functional module.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is the structural representation of three-dimensional TSV integrated morphology in background technology of the present invention;
Fig. 2 is the structural representation of tin ball packaged type in background technology of the present invention;
Fig. 3-9 is structural representations that in the inventive method, each step is corresponding.
Embodiment
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is the structural representation of three-dimensional TSV integrated morphology in background technology of the present invention;
Fig. 2 is the structural representation of tin ball packaged type in background technology of the present invention;
Fig. 3-9 is structural representations that in the inventive method, each step is corresponding.
Embodiment
The invention provides a kind of three-dimensional integrated method of wafer.The Lead-on-Chip region being applicable to bonding wafer and three-dimensional interconnection region need the situation of separating.
Core concept of the present invention is by two panels having been completed wafer prepared by integrated circuit mutually in the face of placing; again by above-mentioned two panels wafer bonding; again by arranging across the TSV between wafer; interconnection between the chip of the difference in functionality of realization between different wafer; and by utilizing repeatedly the deposition of protective layer to form the protective layer of a thickness higher than metal interconnecting layer, thus the metal interconnected Rotating fields of protect IC.
Below in conjunction with accompanying drawing, the inventive method is described in detail, but not as a limitation of the invention.
First, the bonding wafer that one is provided with interconnect area 1 and lead areas 2 is provided, be provided with metal connection structure 28 and metal level in bonding wafer, the metal level of mutually insulated is electrically connected by metal connection structure, and the part surface of metal connection structure is exposed to the upper surface of bonding wafer.
Interconnect area at least comprises a metal connection structure, and lead areas at least comprises two metal connection structures;
A metallic film 29 is prepared, the surface that metallic film 29 covering metal connecting line construction exposes on bonding wafer.
Remove part metals film 29, to form the metal interconnecting layer 210 be electrically connected with metal connection structure in interconnection region and the metal wiring layer 211 adjacent metal interconnects structure in lead areas be electrically connected.
Prepare metal lead wire 210 to be electrically connected being arranged in adjacent described metal connection structure 28 ＇ of described lead areas and 28 ＇ ＇.
Below, lift a specific embodiment to be described in further detail the present invention.
First, provide and complete the first wafer and the second wafer prepared by integrated circuit, above-mentioned first wafer includes the first silicon substrate layer 21 and BEOL dielectric layer 22 structure, and above-mentioned second wafer includes the second silicon substrate layer 24 and the 2nd BEOL dielectric layer 25 structure.
Wherein, a BEOL dielectric layer 22 and the 2nd BEOL dielectric layer 25 comprise some metal levels, for ease of setting forth the object doing invention, six place's metal levels are only shown.
Namely an above-mentioned BEOL dielectric layer also includes the first metal layer 23, the 3rd metal level 23 ＇ and the 5th metal level 23 ＇ ＇, and the 2nd BEOL dielectric layer 25 also includes the second metal level 26, the 4th metal level 26 ＇ and the 6th metal level 26 ＇ ＇.
Wherein, the first metal layer is the metal interconnection layer of integrated circuit on the first wafer, is electrically connected with each function element in integrated circuit in the first wafer.Second metal level is the part-structure of the metal interconnection layer of integrated circuit on the second wafer, is electrically connected with each function element in integrated circuit in the second wafer.
Then, the second integrated circuit layer covers the upper surface of described first integrated circuit layer, its structure structure as shown in Figure 3.Again to completing the first wafer of stacking and the second wafer carries out bonding technology, it is made to connect for entirety, again reduction process is carried out to the wafer completing bonding technology, with thinning first silicon substrate layer 21 and the second silicon substrate layer 24, to facilitate the follow-up etching technics to the first silicon substrate layer 21 and the second silicon substrate layer 24, the chip interconnects between completing across wafer.
Wherein, above-mentioned bonding technology and reduction process can adopt any one process program of prior art.
Subsequently, first micro-shadow etching technics is carried out to the first wafer and the second wafer, namely carry out etching technics to the second silicon substrate layer 24 part of the first metal layer and the second metal layer, etching technics stops to above-mentioned 2nd BEOL dielectric layer 25 upper surface, structure as shown in Figure 4.Again in the second silicon substrate layer 24 and the 2nd BEOL dielectric layer 25 disposed thereon one deck separator 27, be not destroyed in subsequent technique to protect the second silicon substrate layer 24 and the 2nd BEOL dielectric layer 25.
Wherein, the material of separator 27 is preferably oxide or nitride.
Afterwards, carry out second micro-shadow etching technics to the first wafer and the second wafer, namely carry out etching technics to the 2nd BEOL dielectric layer 25 part above the first metal layer, etching technics stops to the first metal layer upper surface, structure as shown in Figure 5.
Then, carry out the 3rd micro-shadow etching technics to above-mentioned first wafer and the second wafer, namely carry out etching technics to the 2nd BEOL dielectric layer 25 part of the second metal layer, etching technics stops to above-mentioned second metal level upper surface, structure as shown in Figure 6.
Then, in the groove that step etching technics each in first, second, and third micro-shadow etching technics is formed, fill metal material, form the first metal connection structure 28, second metal connection structure 28 ＇ and the 3rd metal connection structure 28 ＇ ＇, and remove separator 27, structure as shown in Figure 7.
Wherein, metal material is preferably copper, aluminium, tin or tungsten etc.
Subsequently, at the second silicon base 24, first metal connection structure 28, second metal connection structure 28 ＇ and the 3rd metal connection structure 28 ＇ ＇ upper surface deposition layer of metal film 29, structure as shown in Figure 8.
Wherein, the material of metallic film 29 is preferably the composite material of metal or metal and metal nitride.
Finally, 4th micro-shadow etching technics is carried out to the first wafer and the second wafer, namely part metals film 29 is etched, form the metal interconnecting layer 210 be electrically connected with the first metal connection structure 28 in interconnection region 1 and the metal wiring layer 211 be electrically connected by second metal connection structure 28 ＇ adjacent in lead areas 2 and the 3rd metal connection structure 28 ＇ ＇.
Above-mentioned first to the 3rd micro-shadow etching technics is only the present embodiment and describes and arrange numbering, and do not form the present embodiment restriction, its processing step according to the needs of actual product, can adjust accordingly.
In sum, the three-dimensional integrated method of wafer of the present invention by method of the present invention can by comprising different process, the wafer of chip of difference in functionality is integrated in a heterogeneous three-dimensional structure of wafer scale, for needing lead areas and three-dimensional interconnection region needs process conditions separately, while maintaining chip volume, the function of extensive raising chip, what significantly shorten between each functional chip is metal interconnected, reduce heating, power consumption, with postpone, improve the bandwidth between each functional module.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. the three-dimensional integrated method of wafer, is characterized in that, comprising:
The bonding wafer that one is provided with interconnect area and lead areas is provided, metal connection structure and metal level is provided with in described bonding wafer, the metal level of mutually insulated is electrically connected by described metal connection structure, and the part surface of described metal connection structure is exposed to the upper surface of described bonding wafer;
On described bonding wafer, prepare a metallic film, described metallic film covers the surface that described metal connection structure exposes;
Remove the described metallic film of part, to form the metal interconnecting layer be electrically connected with metal connection structure in described interconnection region and metal wiring layer adjacent metal interconnects structure in described lead areas be electrically connected.
2. the three-dimensional integrated method of wafer as claimed in claim 1, it is characterized in that, described bonding wafer comprises the first wafer and the second wafer, and described first wafer comprises the first silicon substrate layer and a BEOL dielectric layer; Second wafer comprises the second silicon substrate layer and the 2nd BEOL dielectric layer, and described second integrated circuit layer covers the upper surface of described first integrated circuit layer.
3. the three-dimensional integrated method of wafer as claimed in claim 1, it is characterized in that, any described metal connection structure is all electrically connected two described metal levels.
4. the three-dimensional integrated method of wafer as claimed in claim 3, it is characterized in that, any described metal connection structure is electrically connected two described metal levels, lays respectively in a described BEOL dielectric layer and in the 2nd BEOL dielectric layer.
5. the three-dimensional integrated method of wafer as claimed in claim 1, it is characterized in that, the preparation technology of described metal connection structure is: the etching technics of through hole after the etching technics of groove or first groove after first through hole.
6. the three-dimensional integrated method of wafer as claimed in claim 5, it is characterized in that, after described first through hole, the etching technics of groove comprises:
Etch described second silicon substrate layer, described 2nd BEOL dielectric layer and a described BEOL dielectric layer, to form the through hole exposed by described layer on surface of metal;
On basis based on described through hole, etching is positioned at the second silicon substrate layer of the metal layer that any two needs are electrically connected by described metal connection structure, to form described groove.
7. the three-dimensional integrated method of wafer as claimed in claim 5, it is characterized in that, after described first groove, the etching technics of through hole comprises:
Etching is positioned at the second silicon substrate layer of the metal layer that any two needs are electrically connected by described metal connection structure, to form groove;
On basis based on described groove, etching is positioned at the 2nd BEOL dielectric layer and a BEOL dielectric layer of any described metal layer, to form described groove.
8. the three-dimensional integrated method of wafer as claimed in claims 6 or 7, is characterized in that, after described first through hole, after the etching technics of groove or first groove, the etching technics of through hole also comprises:
After forming described groove, in described groove, fill metal material.
9. the three-dimensional integrated method of wafer as claimed in claim 8, it is characterized in that, the material of described metal material is copper, aluminium, tin or tungsten.
10. the three-dimensional integrated method of wafer as claimed in claim 1, it is characterized in that, the material of described metal lead wire is the composite material of metal or metal and metal nitride.
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| CN109148361A (en) * | 2018-08-28 | 2019-01-04 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
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