TW307038B - - Google Patents

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Publication number
TW307038B
TW307038B TW085100630A TW85100630A TW307038B TW 307038 B TW307038 B TW 307038B TW 085100630 A TW085100630 A TW 085100630A TW 85100630 A TW85100630 A TW 85100630A TW 307038 B TW307038 B TW 307038B
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TW
Taiwan
Prior art keywords
layer
window
dielectric layer
conductive
interlayer dielectric
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Application number
TW085100630A
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English (en)
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Motorola Inc
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Publication of TW307038B publication Critical patent/TW307038B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/959Mechanical polishing of wafer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

A7 A7 且更特別的是有關 五、發明説明(1 ) 和先前應用之交互參考資_ 本項應用已於m5年2月24日列構爲美國 件 08/393,782。 T ”宵系 發明領域 本發明大致上是和半導趙元件有關 於半導體元件中形成導電插頭的方法 發明背景 在諸如積體電路之半導體元件内,轉插頭正成爲廣泛應 用於各種導電層間製造電性連結的一個方彳 哨万式。通常,鎢插 頭是在半導體S件之第—層導電層上先沉積—層層間介電 層而形成的。之後在層間介電層内蝕刻出窗口,曝露出— 部份第一層導電層。之後,在此元件上全面沉 〜.,.·一一一1 .jfc...二具一_ -TE3 此填入層間介電層内的窗口内,同時能接觸到第一層導電 層。之後又拋光或蝕平至除去鎢層上所有部份爲止,而位 於層間介電層窗口内的鎢則未予除去。這樣得到一個鎮插 頭,能作爲和第一層導電層之垂直方向的電性連結。 上文描述内容存在的一個基本問題是鎮不容易和常用層 間介電材料黏結在一起’諸如二氧化妙、妙鱗酸玻璃(pSG) 、摻雜硼之矽磷酸玻璃、或電漿強化氧化物,及氮化矽等 材料。結果,使用鎢插頭時通常需要利用一層黏結層,以 .確保鎢能和元件黏結在一起。黏結層的典型應用是顯示於 圖1至2之中,此圖示乃是一部份利用先前技藝之半導體元 件(10)之橫截面。如圖1所示,半導體元件(iO)包含一半導 體基板(12) ’其上形成第—層介電層(14)及金屬連接線(16) -·—....— -4- ..---rd t衣-- (請先閔讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4说格(210人297公慶) 經濟部中央橾準局員工消費合作社印製 3〇7〇38 A7 ___B7 五、發明説明(2 ) 。其上沉積了層間介電層(丨8),使其形成圖樣,再進行蝕 刻以產生一接觸窗口或是曝露出連結線路的插頭窗口(1 9) 。之後,黏結層(20)沉積於層間介電層上,並延著窗口(〗9) 的側壁及底部沉積。黏結層(2〇)可以採用單一材料,如氮 化欽,但是通常是一種連續沉積秣及氮化鈦的组合,這是 和使用哪一種導電材料作接點有關。其次,鎢層(22)會全 面沉積於元件(10)之黏結層上以壤滿窗口 G9).,如圖1所示 。爲了要在許多填滿的窗口之間提供電性絕緣,在每一窗 口(19)以外的鎢層及部份黏結層(2〇)會被移除,如圖2所示 。黏結層(2)及鎢層(22)之移除通常是以蝕刻或拋光方式進 行的。結果會在窗口(19)之内形成鎢插頭(24),同時會有 一層圍在四周的黏結層(20)把鎢插頭和層間介電層(18)分 隔開。 在形成上文討論到之鎢插頭時,使用鈦及氮化鈦黏結層 —- — -·· . ··. ____ 有許多、缺點。其中一個問題是生產量很慢。作爲黏結層 (20)的最初然!通常是以平行的濺鍍製程沉積至久〇〇赛或4〇 兔辦米_的厚度。尤戈是較佳的方式,它可以確保 鈇能在側壁和接觸窗口的底部均勻地沉積至足夠的厚度。:: vJ!·—.,一.1·........................................ 氮化欽也是以類似濺鍍方式沉積,通常到達J00埃(8〇毫微 声)的厚度。濺魂沉積,特別是平行的m積,是二種 Λ相當慢的製每。例如,要沉積出前述黏結層厚度的話,使 用1.5:1的瞄準儀接著沉積鈦及氮化鈦層大約孝片晶圓須花 一費.3至5分鐘。除了花在沉積黏結層的寶貴時間外,要把接 II I 1__ —" ,. -Ά —— 觸窗口之U氣轉瘦曼斧亦是很慢的。例如,要同時移除 ____ -5- 本紙張尺度適 (請先閲讀背面之注意事項再填寫本頁) 、-·β A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(3 ) 鸠層(22)及鈥和氮化欽黏結層(2〇)所需的過半抛光時間是 用於移除黏結層,雖然該黏結層僅只有鎢層厚度的五分之 —(20%)而已。 而另外一個使用鈦及氮化鈦黏結層的問題是接觸電阻。 黏結層中鎢的部份是通常用於改善鎢插頭和金屬連接線之 間的接觸電阻,這和氮化鈦本身作爲黏結層用是不同的a 然而,即使加入鈦作爲黏結層中的一部份,如果層間介電 層内接觸窗口形成過程中,金屬連接線受損或污染,則接 觸電阻仍然是個問題。例如,在形成接觸窗口時使用氟基 的化學藥品,氟會和連接線中的鋁反應而形成氟氧彳匕銘*' (A10xFy),這將使接觸電阻退化。 圖之簡述 圖1至2是一橫截面視圖,顯示一種根據先前技藝以黏結 層來形成導電插頭的製程。圖3至8顯示一根據本發明以黏 結層來形成導電插頭的製程之橫截面視圖。 圖9是一種類似圖8所示之半導體元件之橫截面視圖,但 這是根據本發明之另一個具髏實施例。 圖10也是根據本發明之一種半導體元件之橫截面視圖, 其中的導電插頭是形成於一摻雜基板區域中之導電區域。 圖11是另外一個半導體元件之橫截面視圖,顯示出本發 明在臨界尺寸(CD)控制的優點。 較佳具體實施例之詳細描述 大體上,本發明提供一種在半導體元件内形成導電插頭 的万法,不需要使用到一般的鈦和氮化鈦黏結層與插頭窗 -6- 本祕尺度適财咖雜準( (請先聞讀背面之注意事項再填寫本頁) Γ 裝.
•1T —Λ m i In . 3〇7〇38 A7 — B7 經濟部中央標準局員工消費合作社印裝 五、發明説明(4 ) 口排在一起。結果,採用本發明之方法使得在沉積與移除 這些黏結層的製造時間能節省下來。本發明藉由氮化鋁黏 結層之應用,可獲得此項及其它的優點。然而,這和先前 的技藝不同’氮化鋁黏結層在沉積後不需要移除,而且它 不會和插頭窗口的侧壁及底部放在一起。根據本發明之具 體實施例,氮化鋁層是沉積在層間介電層的上方。之後, 穿越黏結層及層間介電層形成接點或插頭窗口,曝露出一 部伤在下層的金屬連接線。之後將鶴或其它的導電材料沉 積至元件上及窗口内’和金屬連接線作電性連結。氮化鋁 黏結層可以改善鎢和層間介電層的黏著,使得後續的抛光 步驟中,嫣層不會從層間介電層上剝離或翹起來。儘管黏 結層沒有存在插頭或接觸窗口之中,鎢插頭在沿著窗口内 ,側壁仍和層間介電層有足夠的黏著。再者,由於氮化鋁 是—介電材料,在插頭形成之後不需要把黏結層移除,這 和先前的技藝製程相比,可減少處理步驟之製造時間。從 下文之詳細描述及配合附圖的説明,可以更清楚地瞭解到 這些及其它特點和優點。値得一提的是,這些附圖並不一 2依尺寸比例繪製,且可能還有本發明的其它具體實施例 之、严有特別顯不出來。再者,#注意有時候在不同的視圖中 ϋ使用相同的參考代號來代表相同或相似的元件。 χ圖3至8顯示—部份半導體元件(30)在經由本發明之處理 ‘步驟形成導電插頭時的橫截面視圖。如圖3所示,最初的 結構包含-塊半導體基板(32),其上覆有介電層(Μ)及金 屬連接線(36)。在諸如積體電路的半導體元件中,基板 本紙張尺纽财®KiiT〇7s ) Α4ΜΛ ( 210X297^« ) (請先閲讀背面之注意事項再填寫本頁) Γ 裝· 、va 經濟部中央標準局員工消费合作社印製 A7 —-------------- B7 五、發明説明(5 ) 通常是使用單晶的矽θ如 / 的 卜 吵日Η圓,但也可以是絕緣體上矽(SOI) . 藍寶石上矽(sos)基板 '砷化鎵基板,或類似的 西;1電層(34)可以用高溫成長的二氧化妙、掺雜或未 摻·雜的沉積二氣化劝 * 碎' 氮化矽、氮氧化物,或是用於半導 體元件上的其它傳統介電材料。 在頁較佳具體實施例中,金屬連接線(36)至少包含有 兩個部份’ -個主要部份(37)及—個覆蓋部份⑽。包含 覆盖邵份(38)的目的會在連接線上層間介電層(4〇)内形成 接觸窗口或插頭窗口的參考資料中作更詳細的描述。在某 類型式中’連接隻,或是更精確地 説,是含有少量銅亦或芝的鋁合金。录蓋部份 要邵份相互搭配時,最好兔生里I。在形成圖3所 示之金屬連接線(36)之堆疊結構時,鋁和鎢的地耗層是同 時作成圖樣及蝕刻的。主要部份(37)形成的厚度有4 〇〇〇至 10,000埃(400〜1,〇〇〇毫微米),而覆蓋部份(38)的厚度則是 從500〜2000埃(50〜200毫微米)。在另一個具體實施例中, 氮化鈦障礙層是作爲一部份覆蓋部份(3 8),使得覆蓋部份 包含了氮化鈦層上覆有鎢層。在此項不同選擇的具體實施 例中,氮化鈦層的厚度濺鍍至250〜1000埃(25〜1〇〇毫微米) 之間。於沉積鎢層之前進行。之後,鎢層、氮化鈦層、和 鋁層都作成圖樣且一塊蚀刻,形成堆疊的連接線。而在另 一個的具體實施例中,連接線具有氮化鈦的覆蓋部份,厚 度達15〇〜1000埃(I5〜100毫微米),並未上覆鎢層。 圖3至8之中顯示的金屬連接線(36)是形成於介電層(34) -8 - 本紙張尺度逍用中國國家橾準(CNS ) A4规格(210乂297公釐) -----:--Ί《裝------訂------fA (請先閲讀背面之注意事項再填寫本頁} 經濟部中央標準扃貝工消费合作社印裝 A7 -__B7 五、發明説明(6 ) 之上;然而,有些人可能會希望在連接線和底下的基板 (32)之間插入許多層。例如,掺雜區、矽化物區複晶廣 、隔離區及用於形成諸如電晶體之活性元件用的各種介電 層或間隔層都有可能存在其間。爲了要瞭解本發明起見, 對這些插入層的瞭解並沒有必要’因此在此不予討論或圖 示説明。再者,甚至介電層(34)也是沒有必要的,根據本 發明的導電插頭可以和基板(32)(而非金屬連接線)之掺雜 或導電部份作電性連接。 繼續圖3所示之最初元件結構’—層間介電層(4〇)會覆蓋 在連接線(36)之上。f間介電層通常是矽基的介電物質, 如BPSG、PSG、TEOS、SOG、或是電漿強化氧化物。 爲了要和連接線(36)有電性連結,層間介電層内必須開 窗口,把下層的連接線曝露出來。如先前所提到的,在製 造此窗口時有可能會對連接線造成損壞或污染,導致接觸 電阻很差。有一個潛在的問題是如果用於蝕刻層間介電層 的蝕刻材料中的氟和連接線中的鋁接觸,則會形成氟氧化 銘(A10xFy)。根槔丰發後名具體實施例,使用覆蓋 ......IV η - .1- ....... .1 ..乂备..,’’ 5!.免.步成A10xFy。藉由在連接線上覆蓋鎢層,則使用含 氟的化學藥品來蝕穿層間介電層(4〇)時,由於 每ι把鋁-曝露ϋ。再者,因爲在典型 乾式蝕刻的情形時氟氧化鋁是揮發性的,因此無需擔心在 蝕刻層間介電層時會生成不想要有的氟氧化鎢。爲能邊一 t避ϋ·可至穿越鎢覆蓋層遷移,可加入氮化鈦或其它障 礙材料的障礙層至覆蓋部份(38),如同上文所描述的相同 -y - 本_尺度1Ϊ财ϋϋ冢4準(( 210X297公釐)一· ------:--.裝------訂------^ (請先閱讀背面之注意事項再填寫本頁) A7 B7 a〇7〇aa 五、發明説明(7 ) 情形。然而,鎢本身就足以保護連接線。鎢以外的材料也 可作爲覆蓋部份,而仍然能在蚀刻期間對連接線提供必要 的保護。例如,可?.姨.使1氣Μΐϋ—金屬連接線 圖樣化的光學照相蚀刻期間有額外的好處,可作爲抗展射 ρ塗層。須注意在本發明中,覆蓋層並不是必要的部份, 伊疋是.被..5L於提供元件.的效„能。可以預期在某些連接線結 構中’不使用任何此種覆蓋層亦可得到適當的接觸電阻。 在形成所要的連接線結構及沉積層間介電層(4〇)之後, 會沉積一層黏結層(42)在元件(30)上面,如囷4所示。根據 本發明,黏結層(42)是氮化_务層。在一較佳的型式中,黏 、丨丨丨 — -~ - 結層(42)是利用反應性賤鍍(RS)方式,以銘托在氮的氣氛 下沉積上去的,純氮或是加入氦、氬等惰性氣體都可以。 依反應器型式及其它的變數,特定的製程參數是可以作變 化的,但通常基板溫度是20。至500X:,氮氣分壓是1.〇_ 8.0毫托(mTorr),陰極功率爲0.5至8.0¾ (kW)。更特別地, 最好是採用4.0毫托(mTorr)氮分壓、基板溫度、及3 〇 瓧(kW)陰極功率的RS製程。使用氮化鋁複合靶的濺鍍製程 亦適用於製造黏結層(42),在此情形下不需要使用反應式 的濺鍍。其它沉積氮化鋁的方法亦適用於形成黏結層,例 如化學蒸氣沉積(CVD)。最好黏結層(42)沉積至1〇〇至400 埃的厚度(10至40毫微米),250埃更好(25毫微米)。黏結層 (42)的沉積厚度可以比先前技藝中的黏結層還薄,這是因 爲在相當平坦的層間介電層(40)上沉積黏結層沒有階段覆 蓋性的考慮問題,而且它是在層間介電層形成接觸窗口之 -10- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) --------—— • . (請先閲讀背面之注意事項再填寫本頁) 、ys 丁 經濟部中央標準局員工消費合作社印裝 A7 B7 經濟部中央樣準局員工消費合作社印製 五、發明説明(8 前沉積的。 在沉積黏結層(42)之後,元件(30)作成圖樣化並蝕刻, 以形成穿越黏結層(42)且進入層間介電層(4〇)至足以露出 一部份連接線(36)的接觸窗口或插頭窗口(44),如圖5所示 。要形成窗口(44)可以用傳統光學照相蝕刻技術來形成— 光阻罩幕(未顯示出)’界定出那裹要形成窗口。之後,元 件進行乾蚀刻移除連接線上方的介電材料。可以使用單— 氟基乾蚀刻化學藥品來除去氮化鋁黏結層(42)及層間介電 層(4〇)。雖然氮化鋁在氟中的^趣匁率很低,但由於黏結層 巧薄,因此使用單一種蝕刻化學藥品來同時移除黏結層和 層間命電層_是使ϋ種不同的蝕刻化學藥品是更有敫率 在氟基的化學藥品中移除氮化鋁特別有可能發生在蚀 刻開始的階段,因爲大部份的蝕刻在剛開始時選擇比較低 。此蝕刻動作移除掉部份結層及氧化物,產生窗口(44)而 曝露出連接線的覆蓋部份(3 8)。如上文中所解釋的,在蚀 刻的後段期間覆蓋部份(38)可以保護連接線的主要部份(37) ,避免鋁直接曝露於氟之中。使用氟基的化學藥品,二氧 化歹和鎢之間的選擇比高,如此可以適度地保障所形成的 窗口(44)是已經把所有介電材料移出窗口内,而得到最佳 ^接觸表面。如圖5所示,形成窗口(44)時,黏結層(42)只. 存在於窗口以外的區域,而心並未如許多先前扶藝中所用 的|構會存在於底部或側壁:上。 其次’將一層鎢層或其它合適的導電插頭材料沉積於元 件(30)上面。這是圖6中所顯示的導電層(45)。插頭材料是 11 - 良紙張尺度適用中國國家標準(CNS ) A4坑格(2丨0χ297公羡 (請先閲讀背面之注意事項再填寫本頁) 裝· 丁 、τ 經濟部中央標準局貝工消費合作·社印製 A7 B7 五、發明説明(9 沉積至足以填滿窗口(44)的厚度,這在許多例子中是介於 2500至6000埃(25〇至6〇0毫微米)之間。任何沉積鎢之已知 方法’或是其它合適的插頭材料都可以用於本發明的應用 上。如圖6所示,在沉積導電層(45)時,用於形成插頭之 導電材料只有在窗口(44)之内才和層間介電層(4〇)有直接 接觸。在窗口(44)之外的位置,導電材料(45)是和層間介 電層(4〇)隔著一層黏結層(42)。因此,在層間介笔量的上 表一面上,於有氮化銘黏結層(42)而能克服鎢和矽基介電_ • . 資之間的不良黏著性。_在諸如抛光的後續處理步驟中,導 電層(45)能原封不動地留在元件上,免於剝離或是從元件 上脱落。再注意窗口(44)之内,導電層(45)和窗口側壁之 間並沒有黏結層(42)。儘管沒有黏結層,鶏層和層間 介電層的黏著情況是令人滿意的,這或許是因爲窗口内或 其周遭在處理時留下的壓縮應力所致。 因爲沉積導電層(45)大致上是非選擇性的,因此有必要 移除部份窗口(44)外的導電層,使形成的每一個導電插頭 之間有電性絕緣。如圖7中所示,可以用蝕刻或拋光方式 把導電層(45)移除至露出黏結層(42),而在窗口(44)内留下 一導電插頭(46)。最好導電層是被拋光處理至平坦。抛 丝Hi程中,黏結屠(42X玄真本在_^_會作-一 個蚀刻終止層,這是和所用的化學藥品有關。 個化學機械或抛光步驟中,可以使用硝酸鐵或過'氧化氫的 泥漿配合氧化鋁磨料把鎢層移除。在抛光之後,導電層 (48)被沉積至元件(30)上面而和導電插頭接觸,如圖8所示 -12- 本紙張尺度適用中國囤家標準(CNS ) A4規格(210x29*7公釐 ------·---^-- - (請先閲讀背面之注意事項再填寫本頁) 訂 3〇7άίβ Α7 __ Β7 五、發明説明(1〇 ) 。在某些例子中’氮化鋁可能會有比鎢更快的拋光速率, 在此例子中,有一部份留下來的導電插頭(46)會相對高於 相鄰的層間介電層(40)。較突出的插頭冬較有益處的,因 爲它能提供導電層(48)更大的接觸面積。) 經濟部中央標準局員工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 在一蝕平的製程中,可用一種氟基的化學藥品來蝕平鎢 層’終止於氮化鋁黏結層上面。最好能把氮化鋁黏結層移 除,雖然從下文的討論中我們知道不一定得移除它。利用 氣基的乾蚀刻及化學蝕刻方式可以在氮化鋁和下面的層間 介電層間選擇性移除氮化鋁。在後續的氣基蝕刻中移除黏 結層(42)有一個優點,就是四周的層間介電層(4〇)會從導 電插頭(46)上表,^往下凹大約有被移除黏結層的厚<。如 上文所討論的,+電層從插頭上表面往下凹有助於導電插 頭和後續沉積的層間之接觸,並増加接觸面積。另一 個方式’在沉積後續的導電材料和導電插頭接觸之前,黏 結層(42)可以被留在元件之内。如圖9所示,黏結層(42)在 窗口(4句之外的其餘部份留在半導體元件(5〇)之内。因爲 #結層―是由氩也JS所曼成的,它是一介電翁質故不必擔二厂 導電插言免臺立免1盤遵或1電兔見有短路農風遷,這 在使用其i傳統黏結層材料時是會發生的。再者,氮化飽 可以和前段及後段處理條件相容’因此不需要將其移除。 圖10顯示的是一個半導體元件(70)的橫截面,其中導電 插頭(46)疋形成於基板(32)之捧雜區(74)上面’而非在金屬 連接線上面。使用和圖4至8相同的處理步驟來產生半導體 元件(70),只有基本的結構是不同的。和形成連接線不同 -13- 本紙張尺度適用中國國家標準(CNS ) A4規格(210\297公着) A7 ---- B7 五、發明説明(11 ) ’掺雜區(74)是以傳統離子佈植或擴散技術所形成的。層 間介電層(40)是沉積於摻雜區上而非在連接線上。之後, 使用和上文描述相同的方式來處理。 經濟部中央樣準局貝工消費合作社印製 根據本發明所用岛氮化色!有另外一個好處,氮化鋁可 气爲金屬窗口蚀刻期間臨界尺寸(CD)控制的硬軍。圖11顯 示一半導體元彳牛(80)的橫截面及此優點的效果。在蝕刻金 屬窗口或是介電材料窗口’尤其是牽涉到高位向比d齊 寬^.,光阻沖蝕的問題對窗口的尺寸有不利的影 響。在延長的金屬窗口蝕刻期間,光阻會從原有界定的位 置上被拉下來或除去。由於在整個蝕刻期間光阻罩幕邊緣 位置會改變,導致層間介電層内產生的窗口之尺寸也會改 變。气電層上方使用氮化鋁層可以補償掉此種光阻沖蝕 的效應。i α示,元件(80)包括基板(32)上.方的層間 A %層(40)。如上文中所描述的,氮化鋁層(42)會沉積在 層間介《層上。光阻罩幕(82)會根據傳統光學照相蝕刻技 術形成於元件(80)上面。如同原先形成的圖樣,光阻罩幕 (82)具有大致上垂直的邊緣(83),而且和層間介電層内 要形成的窗口邊界對齊。在對層間介電層(4〇)作異支向性 凌]期間,光阻罩幕(82)的邊緣(83)會侵蝕到所示的位置 若沒有氮化鋁層(42)存在的話,層間介電層中之窗口(84) 將會有凹入的光阻邊緣所造成的較大寬度尺寸,而不是原 先光阻圖樣所界疋的尺寸。然而,氮化銘對於可能被用於 層之氟基化學藥品有非常低的蝕刻速率,椅一; 2是在蚀刻的初期階段。氮-銘層内形成之窗口在i至是 本紙張尺度ϋ财關家標TT^ns ) A7 B7 五、發明説明(12 ) 〜〜 延長的金屬窗口蝕刻期間,可以維持其尺寸不變,作爲一 蚀刻硬罩。如果有必要的話,氮化鋁的厚度也可以再作充 分地增加,比上文所描述的還原,以確保它能夠成功地作 爲一硬罩。須注意的一點是本發明在CD控制上的優點和 是否採用氮化鋁層作爲黏結層是無關的。再者,在本發明 的這個目標中,插頭的下方歹一定需要有一導電物質。再 者,在形成氮化鋁層(42)之窗口後,但是在蝕刻層間介電 層(40)之前,可以把光阻罩幕(82)移除。結果,i化鋁罩 1 本考m 一蝕刻罩导:.上此可消除掉層間介電層勉刻〜 期間光阻污染的可能性。 前面的描述及包含之圖示顯示了許多和本發明有關的優 點。特別是它顯示出氮化鋁可作爲導電插頭形成過程中的 黏結層,有助於抛光或蝕平的製程。使用本發明所用的黏 結層比起先前技藝中所用的黏結層有一些好處,其中用於 形成氮化銘努释層n拉座間比形成先前技藝中所用黏結 層的時間運要少。在某些案例中,沉積氮化鋁所需的時間 是形成傳統式鈦層和氮化鈦黏結層組合的時間之十分之一 (10%)至五分之一(2〇%)。由於根據本發明之黏結層是在接 觸窗口形成前沉積於層間介電層上,黏結層不需要沉積至 足以Φς供適當階段覆蓋率的厚度。再者,當配合連接線覆 盖層使用時’只需要使用一種材料作爲黏結層,而先前技 藝所用的黏結層通常是使用兩種材料的組合。而另外的好 處疋本發明所用..的黏結層不需要移除,因此可省下更多的 芝造時間。再者,可避免先前技藝之黏結層和其下方金屬 _____"15 - 本紙張尺度適用中國國家標準(~CNS ) Α4規格(210Χ297公廣) ------;---ΊΜ Λ—— ί請先閑請背面之注意事項再填寫本頁) -a 經濟部中央標準局貝工消費合作社印製 發明説明(13 連接線的不良反應,因爲在接琴窗口内沒有^結層。反而 ’插頭材料是直接和金屬連接線接觸,如此可減少 阻為加的潛在危險。 因此很明顯地,根據本發明已證實了一種用於形成插頭 及具備該插頭之半導體元件的方法,完全滿足之前所提之 需要及優點。雖然本發明已根據特定的具體實施例作了描 述及説明,本發明並非只偈限於這些顯示出丰的具體實施 例。對於那些熟知此項技藝的人士而言都能昧解,在不偏 離本發明的精神下可以做一些改良及變化。例如,本發明 並不一定是只能配合鎢插頭來使用。其它的插頭材料,不 管是否爲導電性,都能從在此敎導的方法受庫。此外,本 發明並不受限於形成半導體元件内金屬層上的插頭。反而 ’本發明可用於配合形成任何插頭及元件内的任—層位置 ’特別是配合形成基板擴散區上之插頭。再者,如果是配 合金屬連接線使用’不需要使用覆蓋部份。也(不需要以在 此描述的特別方式來沉積或形成氮化鋁黏結層。因此,本 發明是要包含所有這些落入申請專利範固内的各種變化及 改良事項。 ------.--Ί「装------訂------f、· , - (請先閲讀背面之注意事項再填寫本頁) 經濟部中央棟準局貝工消費合作杜印裝 -16- 本紙張尺度適用中國國家標率(CNS ) A4规路(210 X 29*7公釐)

Claims (1)

  1. A8 B8 C8 D8 3〇,f〇3a 申請專利範圍:. i-—種用於製埤導體元件之方法,其包括以下之步驟: 製備一具有連接線之半導體基板; 於金屬連接線上方沉積一層間介電層; 於層間介電層上方沉積一氣化鋁组成之黏結層; 穿越層間介電層及黏結層蝕刻一窗口,其中該窗口是 位於金屬連接線上方並曝露部份的金屬連接線; 於黏結層上沉積一導電插頭材料’並於窗口内沉積一 導電插頭材料,直到填滿窗口爲止;及 把導電插頭材料拋平以於窗口内形成一導電插頭,同 時和金屬連接線作電性連接。 2_ —種用於製造半導體元件之方法,其包括以下之步驟 製備一半導體基板; 於半導體基板上方沉積一介電層; 於該介電層之上方沉積一氮化鋁組成之薄層; 穿越該薄層蝕刻出第一個窗口,該第一個窗口具有第 一個寬度尺寸; 以該薄層中的第一個窗口作爲硬罩,在介電層内異方 向蝕刻出第二個窗口,使得第二個窗口所具有的第二個 寬度尺寸大致上和第一個寬度尺寸相同; 經濟部中央標隼局員工消費合作社印製 在氮化鋁組成之該薄層上作出圖樣化的光阻罩幕,梦 光阻罩幕界定出第一個窗口的邊界; 使用光阻罩幕來產生第一個窗口;且 在異方向性鈾刻第二個窗口之前移除光阻罩幕。 3. —種用於製造半導體元件之方法’其包括以下之步驟· -17- 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐)
    、申請專利範圍 4. 經濟部中央標準局員工消費合作社印袋 製備=具有接觸用導電區之半導體基板; 於琢導電區上方沉積一介電層; 2該介電層上方沉積—氛化銘組成之黏結層 穿越孩黏結層、進入介電層而蝕刻出一窗口 區曝露出來; 沉積一導電插頭材料於黏結層之其餘部份及窗口内 其足以填滿窗口並和導電區作電性連接,其中該窗口 之導電插頭材料是緊臨著介電層;及 移除窗口外面之其它導電插頭材料部份,以形成一 電插頭。 —種用於製造半導體元件之方法,其包括以下之步驟: 製備一半導體基板; 於半導體基板上形成一金屬連接線,其中該金屬連接 線具有由鋁组成之主要部份及在其上的覆蓋層; 於金屬連接線上沉積一層間介電層; 於層間介電層上沉積一氮化鋁組成之黏結層; 穿越黏結層並進入層間介電層蝕刻出一窗口,曝露一 部份金屬連接線上的覆蓋層; 於半導體基板上及黏結層上沉積一鎢組成之插頭層, 直至足以填滿窗口且和金屬連接線有電性接觸爲止 抛平插頭層以除去窗口外的插頭層部份,如此可在 口内形成一鎢插頭。 使導電 導 ;及 -----^--f 裝------訂------ft (請先閱讀背面之注意事項再填寫本頁) 18 本紙張尺度適用中國國家標準(CNS〉A4規格(210X297公釐)
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JPH08250595A (ja) 1996-09-27
US5578523A (en) 1996-11-26
KR960032686A (ko) 1996-09-17
US5534462A (en) 1996-07-09
JP4094073B2 (ja) 2008-06-04

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