經濟部中央標準局員工消费合作社印製 A7 _______B7 五、發明説明（） ~~ 5-1發明領域 本發明係有關於一種控制半導體元件中的保護層 厚度的方法，特別是有關於一種控制動態隨機存取記憶 體上之保護層厚度之方法，其中的保護層製程過程中， 只用一個光罩’而且動態隨機存取記憶體中具有保險絲 (fuse)。 5-2發明背景 在設計動態隨機存取記憶體時，經過晶圓的電性測 試之後，可以將多餘記憶胞（redundant cell)連結到未受 損害的記憶胞’以將受損害的記憶胞取代掉，而在晶圓 中的保險絲（fuse)可以被用來剔除電性測試之後所發現 的受損之記憶胞，所以在進行半導體元件的製程中，多 餘記憶胞會被廣泛使用到，在製造記憶胞時，保護層是 被形成在半導體晶圓表面，而一般常用的保護層材料是 用化學氣相沉積法的磷玻璃（CVD PSG)，或是電漿加強 式（plasma enhanced)化學氣相沉積法的氮化矽，此保護 層是用來保護半導體晶圓免於受到污染物以及濕氣的侵 蚀’同時也避免晶圓受到刮傷，保護層被沉積在半導體 晶圓表面’藉以保護半導體晶圓中的元件免於受到損 害，並且可以在晶圓組合以及封裝的過程中，避免半導 體元件受到化學性或機械性的傷害。 如圖一所示的半導體晶圓之剖面圖，是典型的一個 本紙張尺度適用中國國家標牟（CNS ) Λ4規格（2lOX29_7公# ) (請先閱讀f面之注意事項再填寫本頁- -裝- •11 經濟部中央標準局員工消費合作社印製 A7 B7 — 五、發明説明（） 將上述所提及的保險絲埋在半導體晶圓中所形成的半導 體晶圓之剖面囷，其場氧化層（field oxjde)i的厚度是 2150埃（angStr〇ms)，而形成在場氧化層’上的TE〇s 氧化層2的厚度大約是1000埃。其次形成在te〇S氧化 層2上的第一複晶砍層間氧化層（|nter p〇|y 〇xjde)3的 厚度大約是5100埃，而形成在第一複晶矽層間氧化層3 上的是第二複晶梦廣間氧化層4，其厚度大約是iqoq 埃。 至於形成在第二複晶矽層間氧化層4上的複晶發 保險絲層5的厚度大約是1 5 0 〇埃’而形成在複晶矽保險 絲層5上的第三複晶矽層間氧化層6的厚度大約是4000 埃’而形成在第三複晶矽層間氧化層6上的介層間氧化 層7的厚度大約是11 000埃。形成在介層間氧化層7上 的鈦層8的厚度大約是1000埃，而且形成在鈦層8上的 氮化鈦層9的厚度大約是600埃，第一金屬層1〇是形成 於氮化鈦層9上，形成於第一金屬層10上的第一抗反射 層（Anti-Reflective Coating : ARC)11 的厚度大約是 300 埃，此抗反射層11之功用在提昇第一金屬層（反光層）10 後續的黃光製程對準精確度，而形成於第一抗反射層11 上的金屬間介電層12的厚度大約是11000埃。其中第一 金屬層通常是由銅鋁合金（AlCu alloy)所形成，而在製作 記憶胞的傳統技術上，第一抗反射層通常是由氮化鈦 (TiN)所形成》 然後使用光罩（photo mask)以形成光阻圖案層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公# ) (請先閱讀背^之注意事項再填寫本頁}Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _______B7 V. Description of the Invention () ~~ 5-1 Field of the Invention The present invention relates to a method for controlling the thickness of a protective layer in a semiconductor device, and more particularly to a method for controlling dynamic randomness. A method for accessing the thickness of the protective layer on the memory. In the protective layer manufacturing process, only one photomask is used, and a fuse is included in the dynamic random access memory. 5-2 Background of the Invention When designing a dynamic random access memory, after electrical testing of the wafer, redundant cells can be connected to unimpaired memory cells to replace the damaged memory cells. The fuse in the wafer can be used to eliminate the damaged memory cells found after the electrical test. Therefore, in the process of semiconductor device manufacturing, extra memory cells will be widely used. When the memory cell is used, a protective layer is formed on the surface of the semiconductor wafer. The commonly used protective layer material is phosphorous glass (CVD PSG) using chemical vapor deposition, or plasma enhanced chemical vapor phase. Deposited silicon nitride, this protective layer is used to protect semiconductor wafers from being attacked by pollutants and moisture. At the same time, it also prevents the wafer from being scratched. The protective layer is deposited on the surface of the semiconductor wafer to protect the semiconductor. The components in the wafer are free from damage, and the semiconductor components can be protected from chemical or mechanical damage during the wafer assembly and packaging process. The cross-sectional view of the semiconductor wafer shown in Figure 1 is a typical paper size applicable to the Chinese National Standards (CNS) Λ4 specification (2lOX29_7 公 #) (Please read the precautions on f before filling out this page-- -• 11 Printed by A7 B7, Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs — V. Description of the invention () The cross section of the semiconductor wafer formed by burying the fuse mentioned above in the semiconductor wafer, and its field oxide layer The thickness of the (field oxjde) i is 2150 angstroms (angstrom), and the thickness of the TE0s oxide layer 2 formed on the field oxide layer 'is about 1000 angstroms. The second one is formed on the te0S oxide layer 2 A polycrystalline interlayer oxide layer (| nter p〇 | y 〇xjde) 3 has a thickness of about 5100 angstroms, and a second polycrystalline dream interlayer oxide layer 4 is formed on the first polycrystalline silicon interlayer oxide layer 3 Its thickness is about iqoq angstrom. As for the thickness of the polycrystalline fuse layer 5 formed on the second polycrystalline silicon interlayer oxide layer 4, the thickness of the polycrystalline fuse layer 5 is about 1 500 angstroms and the first formed on the polycrystalline silicon fuse layer 5 The thickness of the triplex silicon interlayer oxide layer 6 is about 4000 Angstroms' and is formed in the third layer. The thickness of the interlayer oxide layer 7 on the intercrystalline silicon interlayer oxide layer 6 is about 11,000 angstroms. The thickness of the titanium layer 8 formed on the interlayer oxide layer 7 is about 1000 angstroms, and the nitrogen formed on the titanium layer 8 The thickness of the titaniumized layer 9 is about 600 angstroms. The first metal layer 10 is a first anti-reflective coating (ARC) 11 formed on the titanium nitride layer 9 and formed on the first metal layer 10. The thickness of the anti-reflection layer 11 is about 300 angstroms. The function of the anti-reflection layer 11 is to improve the alignment accuracy of the subsequent yellow light process of the first metal layer (reflective layer) 10, and the intermetal dielectric formed on the first anti-reflection layer 11 The thickness of the layer 12 is about 11000 angstroms. The first metal layer is usually formed of a copper-aluminum alloy (AlCu alloy), and in the conventional technique of making a memory cell, the first anti-reflection layer is usually made of titanium nitride (TiN ) Formed "and then use a photo mask to form a photoresist pattern layer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public #) (Please read the precautions on the back before filling this page}
經濟部中央標準局員工消費合作社印製 A7 __ ___B7 五、發明説明（） ^ — 1 3，並以氡化矽蝕刻劑]4對於未受光阻圖案層j 3所遮 蓋的金屬間介電層12進行蝕刻，以同時形成介層連接洞 (via contact)15以及保險絲接觸窗（fuse 9時， 就必須在同一個蝕刻步驟中蝕刻第三複晶矽層間氧化層 6與介層間氧化層7。依據形成介層窗15的傳統方法， 用於触刻金屬間介電層12的蝕刻劑是c4F8、CF4、CH3F 以及Ar，為了移除第一抗反射層彳彳中的原子，仍然使用 與上述相同的蝕刻劑繼續進行蝕刻。當使用C4F8、CF4、 CHsF以及Ar的蝕刻劑一同作為氧化矽蝕刻劑，4，以蝕 刻第一抗反射層11時，曝露出來的氧化矽之蝕刻率大約 為每分鐘5000埃至6000埃。因為在蝕刻第一抗反射層 11時，氬的動量很大，所以第一抗反射層中的原子 會被移除’而且金屬間介電層12中的氧化矽流失厚度大 約為5000埃。其中值得注意的是，在用氧化矽蚀刻劑 14來同時形成介層窗15以及保險絲接觸窗19時，因為 傳統的氧化石夕敍刻劑會造成氧化發之流失，所以就會難 以控制保險絲接觸窗1 9上的氧化層之厚度。 在另一方面來說’當晶圓被用來製作包含有突起型 保險絲（protruding fuse)的結構時，晶圓之剖面圖與圖一 所示者類似’如圖二A所示的晶圓剖面囷是包含有突起 型保險絲之部分晶圓剖面圖，而如圖二B所示之晶圓剖 面圖是包含有要形成銲墊（bonding pad)部分的晶圓剖面 圖。一個稱為銲墊光罩（bonding pad mask)或是銲墊接 觸光罩（bonding contact mask)的遮罩，是用來定義一個 本紙張尺度適用中國國家標準（（^5)/\4規格（2丨0'/ 297公§> (請先閱讀背面之注意事項再填寫本頁) .裝 -一° A7 B7 經濟部中央標準局員工消費合作杜印製 五、發明説明（ 圖樣（pattern) ’藉以進行與已經完成的電路做電性接 觸。上述的這些光阻層中的圖樣使得保護層中得以形成 開口’並且使得這些開口一直蝕刻到已經形成的電路之 金屬層，以形成所謂的銲墊（b〇nCJjng pad)。因為保護層 中的開口被姓刻，所以保護層下的一組金屬圖案就被曝 露出來。這些金屬圏案一般是位於上述的電路之週邊， 也就是所謂的銲墊》而導線被連接到（銲到）上述的銲墊之 金屬’並且被連接到晶片封裝（package)部分。 為了要說明蝕刻具有突起型保險絲的晶圓之金屬 圖案上之第二抗反射層30(圖二B)，此第二抗反射層30 在第二金屬層29(圖二A及圖二B)的正上方，其功用和 圖一之抗反射層11相同，都是用來增加金屬反光層在黃 光對準時的對準精確度《該具有突起型保險絲的晶圓之 剖面圓部分顯示於圖二A以及圖二B中。在囷二A所顯 示的部分晶圓剖面圖中，發底材（Si substrate)上形成有 場氧化層20。而形成在場氧化層20以及矽底材上的是 第一複晶矽層間氧化層（Inter Poly 〇xide)21，並且形成 於第一複晶矽層間氧化層2 1上的是介層間氧化層22， 而第一金屬層23則是被形成並且定義圖樣於介層間氧化 層22上’並且金屬間介電層24被形成在經過圖樣化之 後的第一金屬層23上。接著形成第二金屬層29，並將 其圖樣化在金屬間介電層24上。 然後在整個晶圓表面沉積上一層氮化矽層39，並 且接著形成聚合物圖案層42於整個晶圓表面上。接著， 木紙張尺度適用中國國家標準（CNS ) A4規梢（210XW7公i ) N裝-- C (讀先閲讀背面之注意事項再填寫本頁) 、-° 五、 經濟部中央榡準局貝工消費合作杜印製 A7 B7 ' I- 丨發明説明（） 以聚合物圖案層42作為遮罩，以氮化矽蝕刻劑和氧化發 麵刻劑C^Fe、CF4、CH3F以及Ar作為蝕刻劑45，以對 氣化矽層39進行蝕刻’如圖二A以及圖二B所示，曝露 出來的氮化矽39被去除掉，而且間隙壁（spacer)47形成 在凸起型保險絲（raised fuse)的側壁上。上述的蝕刻步驟 在圖二A以及圖二B中’是同時進行的。為了要形成銲 替’如圖二B所示’在第二金屬層29上的第二抗反射層 30必須被徹底移除。所以使用C4Fe、CF4、CHsF以及 A「作為蝕刻劑的上述之蝕刻步驟，必須要進行至少一分 鐘的過蚀刻（over etching) ’所以上述蝕刻步驟所造成的 第複晶碎層間氧化層21中的氧化發流失量，至少有 5〇〇0埃以上》 在如圖1中的複晶矽保險絲層5上面的氧化矽層必 須維持至少4 5 0 0埃以上，但是上述用傳統蝕刻劑的蝕刻 步驟，會造成難以控制複晶矽保險絲層5上面的氧化矽 層厚度之結果。除此之外，如圖二B所示的第二抗反射 層3 0必須要被完全移除，但是使用傳統的钮刻劑不但會 造成氧化矽的流失，並且無法同時控制氧化矽層的厚 度。氧化矽層的厚度必須加以小心控制，然而為了確保 第一及第二抗反射層（亦即氮化鈦潛）的完全去除所以必 須執行上述所使用的傳統蝕刻劑之過蝕刻步驟，所以保 護層之厚度的控制就極為困難。 5-3發明目的及概述 本紙張尺度適用中國國家標準（CNS ) Μ規格（2ΙΟΧ297公釐〉 (請先閲讀背面之注意事項再填寫本頁} 裝· -訂 經濟部中央標準局員工消費合作社印製 Α7 R7 五、發明説明（） 鑒於上述之發明背景中，用傳統的蝕刻劑之蝕刻步 驟會使得保護層之厚度無法控制’也就是說，對埋入髮 保險絲（embedded fuse)而言，其複晶矽保險絲層上面的 氧化梦層必須維持至少4500埃以上，但是上述用傳統蚀 刻劑的蝕刻步驟’會造成難以控制複晶矽保險絲層5上 面的氧化碎層厚度。保護層中的氧化矽之流失必須加以 小心控制’因為保護層是用來保護半導體晶圓中的元 件。此外，因為抗反射層必須完全被移除，所以用傳統 的蝕刻劑之蝕刻步驟會無法控制複晶矽保險絲層上面的 氧化矽層之厚度。 根據以上所述之目的，本發明提供了 一種控制半導 體元件的保護層厚度之方法，其中的保護層下具有一保 險絲’而且抗反射層下有一金屬層，並且都被埋入在保 護層中’此方法包含下列步驟：第一個步驟是進行第一 蝕刻步驟，以第一蝕刻劑蝕刻此保護層，直到此抗反射 層被曝露。此保護層位於此抗反射層上的第_厚度小於 此保護層位於此保險絲上的第二厚度。其中上述的的保 護層可以是由下列其中之一所組成：氧化矽（si|ic〇n dioxide)以及氮化梦（SiN)。 第二個步称是進行第二蚀刻步驟’以第二蝕刻劑# 刻該抗反射層，直到下方之金屬層被曝露.此第二姓刻 劑包含CI2、〇2、BCI3以及Ar，此第二蚀刻劑對此抗反 射層與此保護層的蝕刻選擇比至少為1 0 » 7 本紙張尺度適用中國國家標準{ CNS ) Λ4規格（210Χ297公f ) (锖先閱讀背面之注意事項再填寫本育) •裝- 订 經濟部中央標準局員工消費合作社印裝 Λ7 _—____B7 五、發明説明（） 5-4圈示簡單說明 圖一為埋入型保險絲（embedded fuse)結構的氧化 矽保護層以傳統蝕刻劑進行蝕刻時的半導體晶圓剖面 圖。 圖二A為另一種凸起型保險絲（rajsecj fuse)結構的 晶圓之部分剖面圖，其中的氮化矽保護層被傳統蝕刻劑 #刻。 圖二B為包含有銲墊（bonding pad)的晶圓之部分 剖面圖，其中氮化矽保護層以及金屬層的抗反射層被傳 統的蚀刻劑钱刻。 圖三A為半導體晶圓之剖面圖，其中氡化矽保護層 被氧化矽蝕刻劑（第一蝕刻劑）蝕刻，直到第一抗反射層被 曝露出來。 圖三B為半導體晶圓之剖面圖，其中抗反射層被金 屬蝕刻劑（第二蝕刻劑）進一步蝕刻，直到第一抗反射層被 完全去除。 5-5發明詳相說明 因為傳統使用氧化矽蝕刻劑，例如用C4Fe、CF4、 CH F3以及氬（Ar)的蝕刻步驟，通常被用來蝕刻保險絲接 觸窗中的氧化矽以及金屬層上的抗反射層（例如氮化鈦 層），所以會產生保護層中的氧化矽層之氧化矽的過度流 失，使得要控制保護層中的氧化矽層之厚度是極不容易 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公f ) (請先閲讀背面之注意事項再填寫本頁) -裝· A7 B7 經濟部中央標準局貝工消費合作社印掣 五、發明説明（ 的。如圓3A所示的半導體晶圓剖面，是用來形成具有埋 入型保險絲（embedded fuse)的動態隨機存取記憶體之 半導體晶圓的剖面圖。其中的保護層是形成在半導體晶 圓表面，而一般常用的保護層材料是用化學氣相沉積法 的麟玻璃（CVD PSG)，或是電漿增強式（p|asma enhanced)化學氣相沉積法的氮化矽。 如囷三A所示的半導體晶圓之剖面圖，是典型的一 個將上述所提及的保險絲埋在半導體晶圓中，所形成的 半導體晶圓之剖面圖，其場氧化層（fie丨d 〇xide>51的厚 度是2150埃（angStroms)，而形成在場氧化層51上的 TEOS氧化層52的厚度大約是10〇〇埃。此外，形成在 TEOS氧化層52上的第一複晶矽層間氡化層（丨nter p〇|y Oxide)53的厚度大約是5100埃，而形成在第一複晶發 層間氧化層5 3上的是第二複晶矽層間氧化層5 4，其厚 度約為1 0 0 0埃。 至於形成在第二複晶梦層間氧化層54上的複晶發 保險絲廣55的厚度大約是1500埃’而形成在複晶發保 險絲層55上的第三複晶矽層間氧化層56的厚度大約是 4000埃，而形成在第三複晶矽層間氧化層56上的介層 間氧化層57的厚度大約是1 1 000埃。形成在介層間氧化 層57上的鈦層58的厚度大約是1 000埃，而且形成在鈦 層58上的氮化鈦層59的厚度大約是600埃，第一金屬 層60是形成於氮化鈦層59上，形成於第一金屬層60上 的第一抗反射層61的厚度大約是300埃，形成於第一抗 Μ氏張尺度適用中國國家標準（CNS M4規格（2]0><297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝- 、-° 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 反射層61上的金屬間介電層62的厚度大約是11000 埃。其中第一金屬層通常是由銅鋁合金（AlCu a丨丨oy)所形 成，而在製作記憶胞的傳統技術上，第一抗反射層通常 是由氮化鈦（TiN)所形成》 然後使用光罩（photo mask)曝光並顯影，以形成光 阻圖案層63，並以氧化梦#刻劑64對於未受光阻圖案 層63所遮蓋的金屬間介電層62進行蚀刻，以同時形成 介層窗（via contact window)65以及保險絲接觸窗（fllse window)69時，就必須在同一個餘刻步驟中蚀刻第三複 晶矽層間氧化層56與介層間氧化層57。依據形成介層 窗6 5的傳統方法’用於蚀刻金屬間介電層6 2的#刻劑 是C4F8、CF4、CHF3以及Ar。為了移除第一抗反射層61 中的氮化鈦抗反射層，仍然使用與前述相同的氧化發蝕 刻劑繼續進行蝕刻。依據本發明的較佳實施例中，當使 用氬（Ar)與CF4、C4Fe、以及CHF3的姓刻劑一同作為氧 化矽蝕刻劑64 ’以蝕刻金屬間介電層62時，是使用時 間模式控制（time mode controlling)的蝕刻步驟，所以在 第一抗反射層61上的氧化矽就會被完全去除掉。 接著由Ch、〇2、BCU以及氬（Ar)所組成的金屬蝕 刻劑73被用在下一個姓刻步驟中，以對第一抗反射層61 進行蚀刻"因為金屬#刻劑73對於抗反射的氮化鈦層以 及氧化梦層的敍刻選擇比至少是10，並且第一抗反射層 的厚度大約只有300埃，所以使得位於保險絲接觸窗69 中的氧化矽流失可以輕易地控制在會少於3〇埃。如圖三 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公^7 (讀先聞讀背面之注意事項再填寫本頁) 裝 訂 經濟部中央標準局貝工消費合作社印裝 A7 ______ 五、發明説明（） B所示’位於介層窗65底部的第一抗反射層61被金屬 蚀刻劑輕易的去除’而且在保險絲接觸窗69中的氧化矽 流失也被控制在極小厚度（小於3 0埃）之内。 根據本發明的較佳實施例中所使用的兩個蝕刻步 驟；依序使用氧化矽蝕刻劑以及金屬蝕刻劑，在保險絲 接觸窗中的氧化矽蝕刻後’厚度就就可以被精確地控制 在製程所需要的規格之内，所以複晶矽保險絲層55上的 氧化矽層厚度也可以維持在5000埃左右。此外，縱然使 用另外的物質，例如鎢（tungSten)、鋁（aluminum)、鈦 (titanium)、相（molybdenum)或是鈷（cobalt)等金屬的氮 化物或是化合物被用來形成抗反射層，依據本發明的較 佳實施例中的金屬蝕刻劑也可以蝕刻這樣的抗反射層。 在依據本發明的較佳實施例中所使用之兩步驟蝕刻以及 金屬蚀刻劑，可以避免氧化碎的流失。特別是在一種為 了節省生產製程成本，只使用一個光罩就形成保險絲接 觸窗的保護層之製程中’在複晶矽保險絲層上的氧化梦 之厚度可以精確的控制在製程規格之内。在本發明的較 佳實施例中，所使用的保護層是由氧化矽所組成，而在 另外的實施例中，如果保護層是由氮化矽所組成，依據 本發明的較佳實施例所提供的方法也可以得到相同的結 果。 ' 特別是當技術進步到超大型積體電路元件時，金導 線連接用的銲墊（bonding pad)密度將越來越密集，同時 銲墊中的開口面積也越來越小。因為依據本發明的較佳 (請先閱讀背面之注意事項再填寫本買) -裝·Printed by A7 __ ___B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () ^ — 1 3, with siliconized silicon etchant] 4 For the intermetallic dielectric layer not covered by the photoresist pattern layer j 3 12 When etching is performed to form a via contact 15 and a fuse contact window (fuse 9), the third polycrystalline silicon interlayer oxide layer 6 and the interlayer oxide layer 7 must be etched in the same etching step. The conventional method for forming the interlayer window 15 is to use c4F8, CF4, CH3F, and Ar as the etchant for etching the intermetal dielectric layer 12, and in order to remove the atoms in the first anti-reflective layer 彳 彳, the same as above is still used. Etchant continues to etch. When C4F8, CF4, CHsF, and Ar are used together as the silicon oxide etchant, 4 when the first antireflection layer 11 is etched, the etch rate of the exposed silicon oxide is about every minute 5000 angstroms to 6000 angstroms. Because the momentum of argon is large when the first antireflection layer 11 is etched, the atoms in the first antireflection layer will be removed 'and the thickness of silicon oxide in the intermetal dielectric layer 12 is lost. About 5000 angstroms It is worth noting that when the silicon oxide etchant 14 is used to form the interlayer window 15 and the fuse contact window 19 at the same time, it will be difficult to control the fuse because the traditional oxide oxide etching agent will cause the loss of oxidation. The thickness of the oxide layer on the contact window 19. On the other hand, when a wafer is used to make a structure including a protruding fuse, the cross-sectional view of the wafer is similar to that shown in FIG. 'The wafer cross section shown in FIG. 2A is a cross-sectional view of a portion of a wafer containing a protruding fuse, and the wafer cross-sectional view shown in FIG. 2B includes a portion to be formed with a bonding pad. Wafer cross-section view. A mask called a bonding pad mask or a bonding contact mask is used to define a paper standard that is applicable to Chinese national standards ((^ 5) / \ 4 specifications (2 丨 0 '/ 297 public § > (Please read the precautions on the back before filling out this page). Packing-1 ° A7 B7 Printed by the Consumer Standards Cooperative Office of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (Pattern) The completed circuit is in electrical contact. The patterns in the photoresist layers described above allow openings to be formed in the protective layer, and these openings are etched all the way to the metal layer of the already formed circuit to form a so-called solder pad (b. nCJjng pad). Because the opening in the protective layer is engraved by the last name, a group of metal patterns under the protective layer are exposed. These metal cases are generally located around the above-mentioned circuit, which is the so-called solder pad. The metal 'is connected to (sold to) the above-mentioned pads and is connected to a chip package portion. In order to explain the etching of the second anti-reflection layer 30 on the metal pattern of the wafer with the bump type fuse (FIG. 2B), the second anti-reflection layer 30 is on the second metal layer 29 (FIG. 2A and FIG. 2B) Just above, its function is the same as that of the anti-reflection layer 11 in FIG. 1, and it is used to increase the alignment accuracy of the metal reflective layer when the yellow light is aligned. The cross-section of the wafer with the protruding fuse is shown in the figure. Second A and Figure B. In a partial cross-sectional view of the wafer shown in FIG. 22A, a field oxide layer 20 is formed on a Si substrate. The first polycrystalline silicon interlayer oxide layer (Inter Poly Oxide) 21 is formed on the field oxide layer 20 and the silicon substrate, and the interlayer oxide layer is formed on the first polycrystalline silicon interlayer oxide layer 21. 22, and the first metal layer 23 is formed and defined on the interlayer oxide layer 22 'and the intermetal dielectric layer 24 is formed on the first metal layer 23 after patterning. Next, a second metal layer 29 is formed and patterned on the intermetal dielectric layer 24. A silicon nitride layer 39 is then deposited on the entire wafer surface, and then a polymer pattern layer 42 is formed on the entire wafer surface. Next, the wood paper scale applies the Chinese National Standard (CNS) A4 gauge (210XW7 male i) N installed-C (read the precautions on the back before filling this page),-° V. Central Ministry of Economic Affairs Industrial and consumer cooperation Du printed A7 B7 'I- 丨 Description of the invention () Use polymer pattern layer 42 as a mask, silicon nitride etchant and oxide surface etching agent C ^ Fe, CF4, CH3F and Ar as etchant 45. To etch the vaporized silicon layer 39, as shown in FIG. 2A and FIG. 2B, the exposed silicon nitride 39 is removed, and a spacer 47 is formed in a raised fuse. ) On the side wall. The above-mentioned etching steps are performed simultaneously in FIG. 2A and FIG. 2B. In order to form a solder replacement, as shown in FIG. 2B, the second anti-reflection layer 30 on the second metal layer 29 must be completely removed. Therefore, using C4Fe, CF4, CHsF, and A "as the etchant, the above-mentioned etching step must be over-etched for at least one minute. Therefore, the second polycrystalline interlayer oxide layer 21 caused by the above etching step The amount of oxidation hair loss is at least 50,000 angstroms or more.> The silicon oxide layer on the polycrystalline silicon fuse layer 5 in FIG. 1 must be maintained at least 4 500 angstroms or more, but the above-mentioned etching step using a conventional etchant Will result in the difficulty of controlling the thickness of the silicon oxide layer on the polycrystalline silicon fuse layer 5. In addition, the second anti-reflection layer 30 shown in FIG. 2B must be completely removed, but using a conventional The nicking agent will not only cause the loss of silicon oxide, but also cannot control the thickness of the silicon oxide layer. The thickness of the silicon oxide layer must be carefully controlled, but in order to ensure the first and second anti-reflection layers (that is, titanium nitride latent) It is necessary to perform the over-etching step of the conventional etchant used above, so the control of the thickness of the protective layer is extremely difficult. 5-3 Purpose of the Invention and Overview China National Standards (CNS) M specifications (2ΙΟ × 297 mm) (Please read the precautions on the back before filling out this page} Installation ·-Order printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 R7 V. Description of the invention () In view of the above In the background of the invention, the thickness of the protective layer cannot be controlled by the conventional etching step of the etchant. That is to say, for an embedded fuse, the oxide dream layer on the polycrystalline silicon fuse layer must be Maintain at least 4500 angstroms or more, but the above-mentioned etching step using a conventional etchant 'will make it difficult to control the thickness of the oxide chip layer on the polycrystalline silicon fuse layer 5. The loss of silicon oxide in the protective layer must be carefully controlled' because the protective layer is It is used to protect the components in the semiconductor wafer. In addition, because the anti-reflection layer must be completely removed, the thickness of the silicon oxide layer on the polycrystalline silicon fuse layer cannot be controlled by the traditional etching step. For the purposes described, the present invention provides a method for controlling the thickness of a protective layer of a semiconductor device. There is a fuse 'and a metal layer under the anti-reflection layer and is buried in the protective layer' This method includes the following steps: The first step is to perform a first etching step and etch the protective layer with a first etchant until The anti-reflection layer is exposed. The thickness of the protective layer on the anti-reflection layer is smaller than the second thickness of the protective layer on the fuse. The above-mentioned protective layer may be composed of one of the following: oxidation Silicon (Si | icon dioxide) and nitride nitride (SiN). The second step is to perform a second etching step 'etch the anti-reflective layer with a second etchant # until the underlying metal layer is exposed. This The second etching agent contains CI2, 02, BCI3, and Ar. The etching selectivity of this anti-reflection layer and the protective layer of this second etchant is at least 1 0 »7 This paper standard is applicable to Chinese national standard {CNS) Λ4 Specifications (210 × 297 Male f) (锖 Please read the notes on the back before filling in this education) • Packing-Order printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives Λ7 ______B7 V. Description of the invention () 5-4 circle brief description Picture one is A cross-sectional view of a semiconductor wafer when a silicon oxide protective layer of an embedded fuse structure is etched with a conventional etchant. Fig. 2A is a partial cross-sectional view of another wafer of a rajsecj fuse structure, in which a silicon nitride protective layer is etched by a conventional etchant. FIG. 2B is a partial cross-sectional view of a wafer including a bonding pad, in which a protective layer of silicon nitride and an anti-reflection layer of a metal layer are etched by a conventional etchant. FIG. 3A is a cross-sectional view of a semiconductor wafer, in which the silicon halide protection layer is etched by a silicon oxide etchant (first etchant) until the first anti-reflection layer is exposed. FIG. 3B is a cross-sectional view of a semiconductor wafer, in which the anti-reflection layer is further etched by a metal etchant (a second etchant) until the first anti-reflection layer is completely removed. The details of the 5-5 invention are explained because the traditional use of silicon oxide etchant, such as C4Fe, CF4, CH F3 and argon (Ar), is usually used to etch the silicon oxide in the fuse contact window and the resistance on the metal layer. Reflective layer (such as titanium nitride layer), so the excessive loss of silicon oxide in the silicon oxide layer in the protective layer will be generated, making it difficult to control the thickness of the silicon oxide layer in the protective layer. This paper applies Chinese national standards. (CNS) Λ4 specification (210X297 male f) (Please read the precautions on the back before filling out this page)-Installed · A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 5. Description of the invention (). The semiconductor wafer cross section shown is a cross-sectional view of a semiconductor wafer used to form a dynamic random access memory with an embedded fuse. The protective layer is formed on the surface of the semiconductor wafer and is generally used. The material of the protective layer is CVD PSG using chemical vapor deposition or silicon nitride using plasma enhanced chemical vapor deposition (p | asma enhanced). The cross-sectional view of a bulk wafer is a typical cross-sectional view of a semiconductor wafer formed by burying the above-mentioned fuse in a semiconductor wafer. The thickness of the field oxide layer (fie 丨 d 〇xide > 51 is 2150 angstroms (angstroms), and the thickness of the TEOS oxide layer 52 formed on the field oxide layer 51 is about 100 angstroms. In addition, the first polycrystalline silicon interlayer halide layer (nter) formed on the TEOS oxide layer 52 p〇 | y Oxide) 53 has a thickness of about 5100 angstroms, and formed on the first polycrystalline interlayer oxide layer 53 is a second polycrystalline silicon interlayer oxide layer 54, which has a thickness of about 100 angstroms. As for the thickness of the polycrystalline silicon fuse layer 55 formed on the second polycrystalline silicon interlayer oxide layer 54, the thickness of the third polycrystalline silicon interlayer oxide layer 56 formed on the polycrystalline silicon fuse layer 55 is about 1500 angstroms. The thickness of the interlayer oxide layer 57 formed on the third polycrystalline silicon interlayer oxide layer 56 is approximately 4000 angstroms. The thickness of the titanium layer 58 formed on the interlayer oxide layer 57 is approximately 1 angstrom. 000 angstroms, and the thickness of the titanium nitride layer 59 formed on the titanium layer 58 is about 600 angstroms, A metal layer 60 is formed on the titanium nitride layer 59. The thickness of the first anti-reflection layer 61 formed on the first metal layer 60 is about 300 angstroms. CNS M4 Specifications (2) 0 > < 297 mm) (Please read the notes on the back before filling out this page) -Installed-,-° Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ( The thickness of the inter-metal dielectric layer 62 on the reflective layer 61 is about 11,000 Angstroms. The first metal layer is usually formed of copper-aluminum alloy (AlCu a 丨 丨 oy), and in the traditional technology of making memory cells, the first anti-reflection layer is usually formed of titanium nitride (TiN). Then use A photo mask is exposed and developed to form a photoresist pattern layer 63, and the intermetal dielectric layer 62 not covered by the photoresist pattern layer 63 is etched with an oxide dream #etcher 64 to form a dielectric layer at the same time In the case of a via contact window 65 and a fuse window 69, the third polycrystalline silicon interlayer oxide layer 56 and the interlayer oxide layer 57 must be etched in the same remaining step. According to the conventional method for forming the dielectric window 65, the #etching agent for etching the intermetal dielectric layer 62 is C4F8, CF4, CHF3, and Ar. In order to remove the titanium nitride anti-reflection layer in the first anti-reflection layer 61, the etching is continued using the same oxidizing etchant as described above. According to a preferred embodiment of the present invention, when argon (Ar) is used together with CF4, C4Fe, and CHF3 as the etchant as the silicon oxide etchant 64 'to etch the intermetal dielectric layer 62, time mode control is used. (Time mode controlling), so the silicon oxide on the first anti-reflection layer 61 is completely removed. Next, a metal etchant 73 composed of Ch, 〇2, BCU, and argon (Ar) is used in the next step of etching to etch the first anti-reflection layer 61. "Because metal # 刻 剂 73 for anti-reflection The etch ratio of the titanium nitride layer and the oxide dream layer is at least 10, and the thickness of the first anti-reflection layer is only about 300 angstroms, so that the silicon oxide loss in the fuse contact window 69 can be easily controlled to be less. At 30 angstroms. As shown in Figure 3, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297K ^ 7 (read the notes on the back and then fill out this page). Binding printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives. ______ V. The description of the invention () B shows that the “first anti-reflection layer 61 located at the bottom of the interlayer window 65 is easily removed by a metal etchant” and the loss of silicon oxide in the fuse contact window 69 is also controlled to a very small thickness (less than 30). A) According to the two etching steps used in the preferred embodiment of the present invention; the silicon oxide etchant and the metal etchant are sequentially used, and after the silicon oxide in the fuse contact window is etched, the thickness can be changed. It is precisely controlled within the specifications required by the process, so the thickness of the silicon oxide layer on the polycrystalline silicon fuse layer 55 can be maintained at about 5000 angstroms. In addition, even if another substance is used, such as tungsten (tungSten), aluminum (aluminum) ), Titanium (titanium), phase (molybdenum), or cobalt (cobalt) and other metal nitrides or compounds are used to form the anti-reflection layer, according to a preferred embodiment of the present invention Metal etchants can also etch such anti-reflection layers. The two-step etching and metal etchants used in the preferred embodiment of the present invention can avoid the loss of oxidation debris. Especially in a process to save production process costs In the process of forming the protective layer of the fuse contact window using only one photomask, the thickness of the oxide dream on the polycrystalline silicon fuse layer can be accurately controlled within the process specifications. In a preferred embodiment of the present invention, The protective layer used is composed of silicon oxide, and in another embodiment, if the protective layer is composed of silicon nitride, the method provided by the preferred embodiment of the present invention can also obtain the same result. '' Especially as technology advances to very large integrated circuit components, the bonding pad density for gold wire connections will become denser and the opening area in the solder pads will become smaller and smaller. Because according to the present invention Better (Please read the notes on the back before filling in this purchase)
*1T 本紙張尺度適用中國國家梯準（CNS ) Λ4規格（ X297公 f ) A7 B7 i、發明説明（） 實施例中的兩個蝕刻步驟以及金屬蝕刻劑可以徹底地去 除抗反射層，同時也精確地控制在保險絲接觸窗中的氧 化發蚀刻後厚度’所以本發明的技術可以符合上述要 求°另外’若半導體晶圓中使用了凸起型保險絲（raised fuse)的結構，則保險絲接觸窗中的氧化矽及氮化矽之厚 度的控制就报重要，因為氧化矽及氮化矽可以保護半導 體晶圓中的元件，免於受到損害或是濕氣所浸蝕。所以 依據本發明的較佳實施例令所使用的兩步驟蝕刻以及金 屬钱刻劑，可以在同時蝕刻抗反射層以及保險絲接觸窗 中的保險絲層上的保護層時，精確地控制保護層的厚 度’免於過度蝕刻》在本發明的較佳實施例中，保護層 位於第一抗反射層上的第一厚度，小於該保護層位於保 險絲上的第二厚度。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明所揭 不之精神下所完成之等效改變或修飾，例如以不同的物 質形成抗反射層’或是以不同的蝕刻劑來蝕刻氮化鈦、 氧化矽以及氮化矽層’以形成保險絲接觸窗以及介層 窗，均應包含在下述之申請專利範圍内。 (請先聞讀背面之注.意事項再填寫本頁) -裝- 訂 經濟、郅中央標準局貝工消費合作社印製 12 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210'〆297公釐）* 1T This paper size is applicable to China National Standard (CNS) Λ4 specification (X297 male f) A7 B7 i. Description of the invention () The two etching steps in the embodiment and the metal etchant can completely remove the anti-reflection layer, and also The thickness of the oxide contact in the fuse contact window after etching is precisely controlled, so the technology of the present invention can meet the above requirements. In addition, if a raised fuse structure is used in the semiconductor wafer, the fuse contact window It is important to control the thickness of silicon oxide and silicon nitride, because silicon oxide and silicon nitride can protect the components in the semiconductor wafer from damage or erosion by moisture. Therefore, according to the preferred embodiment of the present invention, the two-step etching and metal engraving agent used can accurately control the thickness of the protective layer when the anti-reflection layer and the protective layer on the fuse layer in the fuse contact window are etched at the same time. 'Free from overetching' In a preferred embodiment of the present invention, the first thickness of the protective layer on the first anti-reflection layer is smaller than the second thickness of the protective layer on the fuse. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention, such as different Substances that form an anti-reflection layer or etch titanium nitride, silicon oxide, and silicon nitride layers with different etchants to form fuse contact windows and interlayer windows should all be included in the scope of patent applications described below. (Please read the note on the back. Please fill in this page before filling in this page.)-Binding-Ordering economy, 郅 Printed by the Central Standards Bureau, Shellfish Consumer Cooperative, 12 This paper size applies to Chinese National Standard (CNS) Λ4 specification (210'〆297 Mm)