567552567552
發明領域 本發明是相關於一種在半導體製程中形成接觸孔之方 法'特別是有關於一種用以防止在一複晶矽硬罩幕之頂部 上形成矽化鈦（TiSh)及防止一 MOS電晶體之源/汲極區域 氧化之形成接觸孔之方法。 發明背景 我們知道，由於在一半導體基板中之個別裝置及用以連 接該裝置之内連圖案化導電層尺寸之縮小，而使得不斷地 增加該半導體基板上之積體電路密度成為一種趨勢。為了 進一步大大地增加封裝密度，半導體需要具有額外之要 求，例如微影成像技術之改良解析度及改良之電漿蝕刻技 術。 由於積體電路之密度越來越高，所以形成於一内層介電 層中心接觸孔 < 尺寸會變得更小。當接觸孔影像之尺寸小 於〇.2 5μιη時，則必須使用更短波長紫外線來曝露”隱像 (Latent Images)’’於一光阻層中，該光阻層隨後用以做為 該等接觸孔之蚀刻罩幕。結果，下一代製程技術將需要更 薄〈光阻層來完成所需之高解析度。不幸地，該内層介電 曰必λ、保田合理的厚度，以便最小化該内層介電層之電容 量及Rc %路延遲。結果，該等接觸孔需要相當大的縱橫 比（深度/寬度）。因而，當蚀刻接觸孔時，蚀刻深的接觸孔 而不會侵蝕到相對薄的光阻將會變得更困難。 、為了解決上述問題，美國專利第6,025,273號引進一形 成於一薄光阻下方之複晶矽硬罩幕層。然而，在美國專利 ^張尺度適用中@ B家料q χ 29=)---- 567552FIELD OF THE INVENTION The present invention relates to a method for forming contact holes in a semiconductor process, and more particularly to a method for preventing the formation of titanium silicide (TiSh) on the top of a polycrystalline silicon hard mask and preventing a MOS transistor. Method for forming contact holes by oxidizing source / drain regions. BACKGROUND OF THE INVENTION We know that due to the reduction in the size of individual devices in a semiconductor substrate and the interconnected patterned conductive layer used to connect the devices, it has become a trend to continuously increase the density of integrated circuits on the semiconductor substrate. In order to further greatly increase the packaging density, semiconductors need to have additional requirements, such as improved resolution of lithography imaging technology and improved plasma etching technology. As the density of integrated circuits becomes higher and higher, the size of the contact hole formed in the center of an inner dielectric layer will become smaller. When the size of the contact hole image is less than 0.25 μιη, a shorter wavelength ultraviolet light must be used to expose "Latent Images" in a photoresist layer, which is then used as the contact Etching of holes. As a result, the next-generation process technology will require a thinner photoresist layer to achieve the required high resolution. Unfortunately, the inner layer dielectric must be λ and a reasonable thickness of Baotian in order to minimize the inner layer. The capacitance of the dielectric layer and the Rc% path delay. As a result, these contact holes require a considerable aspect ratio (depth / width). Therefore, when the contact holes are etched, the deep contact holes are etched without being eroded to a relatively thin The photoresist will become more difficult. In order to solve the above problems, US Patent No. 6,025,273 introduces a polycrystalline silicon hard cover curtain layer formed under a thin photoresist. However, in the US patent, the standard is applicable @ B 家Q χ 29 =) ---- 567552
第6’025’273號中’做為_硬罩幕之圖案化複晶石夕層氧化 ，為1化♦層16之後，對應於接觸孔15之不被期望之 氧化層19會形成於_第_複晶碎層12中（如圖i所示）， 其中疋件付號1G代表-基板以及元件符號14代表一内層 介電層。結果，該氧化層19下方之第一複晶矽層12會變 薄’進而在纟置正常操作期@容易造成經由鮮一複晶石夕 層12及該基板1〇之漏電流。 發明概要 有鑑於此，本發明目的之一在於提供一種用以防止在一 複晶矽硬罩幕之頂部上形成矽化鈦（Tisi2)及防止一 M〇s 電晶體之源極/汲極區域被氧化的形成接觸孔之方法。 為了完成上述目的，本發明之方法包括下列步驟。提供 一基板’該基板上形成有一複晶矽閘極結構，並且在該複 晶矽閘極結構之兩侧之基板中形成有源/汲極區域。形成一 擴散阻障層於該基板、該複晶矽閘極層及該源極/汲極區域 上。至少一内層介電層形成於該擴散阻障層上。形成一圖 案化之複晶矽層於該内層介電層上，該圖案化之複晶矽層 具有一對應於該源極/汲極區域中之一之開口。使用該圖案 化之複晶碎層做為一硬罩幕，以蚀刻該内層介電層，直到 曝露出該擴散阻障層為止，藉以在該源極/汲極區域中之一 之上方之内層介電層中形成一接觸孔。將該圖案化之複晶 矽層氧化成為一氧化矽層。移除在該源極/汲極區域中之一 上之所曝露之該擴散阻障層。 本發明之上述方法可使不易研磨之TiSh不會形成於該複 _-6- .本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 567552 A7 B7 五、發明説明（ 晶矽硬罩幕之頂部，如此將有利於後續化學機械式研磨之 實施。再者，可有效地防止該源極/沒極區域在該圖案化複 晶矽層之氧化期間被氧化。因為該源/汲極區域不會因氧化 而變薄，所以在該Μ 0 S電晶體操作期間並不會產生經由該 源極/汲極區域及該基板之漏電流。 圖式簡單說明 藉由以下詳細說明及所附圖式將可更了解本發明，然而 下面之詳細說明及所附圖式只是用以做為描述之用，並非 用以限定本發明，其中： 圖1係顯示出依據習知技術之小接觸孔之結構之示意剖 面圖；以及 圖2Α-2Η係顯示出依據本發明之較佳實施例之用以防止 一 Μ 0 S電晶體之源極/汲極區域在接觸孔形成期間受氧化 之方法之示意剖面圖。 發明之詳細說明 圖2Α-2Η係顯示出依據本發明之較佳實施例之用以防止 一 MOS電晶體之源極/汲極區域在接觸孔形成期間受氧化 之方法之示意剖面圖。參考圖2Α ,提供一基板（例如：一 ρ 型矽基板）20，其具有一形成於該基板上之複晶矽問極結構 2 2及形成於該複晶矽閘極結構2 2之兩侧之基板2 〇中之源 極/沒極區域（例如：Ν +型擴散區域）3〇 ' 32。該複晶碎問極 結構22 &括藉由傳統半導體製程（例如：熱氧化法 '化學 氣相沈積、微影成像及乾蝕刻製程）所形成之間隔層2 3、一 氧化層2 4、一複晶石夕層2 6、 wSi層28及一氮化矽層No. 6'025'273 'as the _ patterned polycrystalline spar layer of the hard mask is oxidized. After the layer 16 is formed, the undesired oxide layer 19 corresponding to the contact hole 15 will be formed on the _ In the _th compound crystal layer 12 (as shown in FIG. I), the component code 1G represents a substrate and the component symbol 14 represents an inner dielectric layer. As a result, the first polycrystalline silicon layer 12 under the oxide layer 19 will become thinner ', which will easily cause a leakage current through the fresh polycrystalline stone layer 12 and the substrate 10 during the normal operation period. SUMMARY OF THE INVENTION In view of this, one object of the present invention is to provide a method for preventing the formation of titanium silicide (Tisi2) on the top of a polycrystalline silicon hard cover and preventing the source / drain region of a Mos transistor from being damaged. Method of forming contact holes by oxidation. To accomplish the above object, the method of the present invention includes the following steps. A substrate is provided. The substrate is formed with a polycrystalline silicon gate structure, and active / drain regions are formed in the substrate on both sides of the polycrystalline silicon gate structure. A diffusion barrier layer is formed on the substrate, the polysilicon gate layer, and the source / drain region. At least one inner dielectric layer is formed on the diffusion barrier layer. A patterned polycrystalline silicon layer is formed on the inner dielectric layer. The patterned polycrystalline silicon layer has an opening corresponding to one of the source / drain regions. Use the patterned polycrystalline chip layer as a hard mask to etch the inner dielectric layer until the diffusion barrier layer is exposed, so that the inner layer is over one of the source / drain regions A contact hole is formed in the dielectric layer. The patterned polycrystalline silicon layer is oxidized to a silicon monoxide layer. The exposed diffusion barrier layer on one of the source / drain regions is removed. The above-mentioned method of the present invention can prevent the difficult-to-grind TiSh from forming in this complex. -6. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 567552 A7 B7 V. Description of the invention (crystal The top of the silicon hard mask will facilitate the implementation of subsequent chemical mechanical polishing. Furthermore, the source / electrode region can be effectively prevented from being oxidized during the oxidation of the patterned polycrystalline silicon layer. Because the source The / drain region does not become thin due to oxidation, so no leakage current is generated through the source / drain region and the substrate during the operation of the M 0 S transistor. The diagram is briefly explained by the following detailed description The invention will be better understood with the attached drawings. However, the following detailed description and attached drawings are only used for description, and are not intended to limit the present invention. Among them: FIG. 1 shows the conventional technology. A schematic cross-sectional view of the structure of a small contact hole; and FIGS. 2A-2A show a source / drain region for preventing a M 0 S transistor from being oxidized during contact hole formation according to a preferred embodiment of the present invention. Schematic section of the method DETAILED DESCRIPTION OF THE INVENTION FIGS. 2A-2A are schematic cross-sectional views showing a method for preventing a source / drain region of a MOS transistor from being oxidized during contact hole formation according to a preferred embodiment of the present invention. 2A, a substrate (eg, a p-type silicon substrate) 20 is provided, which has a polycrystalline silicon interrogation structure 22 formed on the substrate and substrates formed on both sides of the polycrystalline silicon gate structure 22 The source / inverted region in 20 (for example: N + -type diffusion region) 3 30 '32. The complex interfacial fragmented structure 22 & includes a conventional semiconductor process (for example: thermal oxidation method' chemical vapor phase) Deposition, lithography, and dry etching processes) spacer layer 2 3, an oxide layer 2 4, a polycrystalline stone layer 26, a wSi layer 28, and a silicon nitride layer
567552 A7 ____ B7 五、發明説明（4 ) ' 一 29 〇 接下來，如圖2B所示，藉由化學氣相沈積法形成一擴散 阻障層（例如：一 SiN或SiON層）34於該基板2〇、該複晶 碎結構22及該源極/沒極區域3〇、32上，該擴散卩且障層具 有一 10-18nm範圍間之厚度。 之後，參考圖2 C，藉由化學氣相沈積法形成一具有 400-600nm厚度之内層介電層36(例如：一 bpsG層）於 該擴散阻障層34上，然後，藉由化學機械式研磨製程平坦 化該擴散阻障層34 ’藉以形成一具有280-350nm厚度之 第一内層介電層36。 在形成該第一内層介電層36步騾之後，藉由化學氣相沈 積法形成一具有220-300 nm厚度之第二内層介電層（例 如：TEOS)38於該第一内層介電層36上（如第2D圖所 示）。 參考圖2 E所示，藉由化學氣相沈積、微影成像及乾蝕刻 製程形成一圖案化之複晶矽層40於該第二内層介電層38 上，該圖案化之複晶矽層40具有一 30-lOOnm之厚度及一 對應於該源極/汲極區域中之一之開口 4 1。 然後參考圖2F，使用該圖案化之複晶矽層40做為一硬 罩幕，乾蝕刻該第一及第二内層介電層36、38,直到曝露 出該擴散阻障層34為止，藉以在該源極/汲極區域30、32 中之一上方之該第一及第二内層介電層中形成一接觸孔 42。隨後，實施熱氧化製程以便將該圖案化之複晶矽層40 氧化成為一氧化矽層40’。 -8 * 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 發明説明（ 在形成該接觸孔42之後，藉由毯覆式乾蝕刻法（Blanket567552 A7 ____ B7 V. Description of the invention (4) '-1 29 〇 Next, as shown in FIG. 2B, a diffusion barrier layer (for example, a SiN or SiON layer) is formed on the substrate by a chemical vapor deposition method 34 20. On the polycrystalline fragment structure 22 and the source / inverted regions 30 and 32, the diffusion layer and the barrier layer have a thickness in a range of 10-18 nm. After that, referring to FIG. 2C, an inner dielectric layer 36 (for example, a bpsG layer) having a thickness of 400-600 nm is formed on the diffusion barrier layer 34 by a chemical vapor deposition method. The polishing process planarizes the diffusion barrier layer 34 ′ to form a first inner layer dielectric layer 36 having a thickness of 280-350 nm. After 36 steps of forming the first inner dielectric layer, a second inner dielectric layer (eg, TEOS) 38 having a thickness of 220-300 nm is formed by chemical vapor deposition on the first inner dielectric layer. 36 (as shown in Figure 2D). Referring to FIG. 2E, a patterned polycrystalline silicon layer 40 is formed on the second inner layer dielectric layer 38 by chemical vapor deposition, lithography imaging, and dry etching processes. The patterned polycrystalline silicon layer 40 has a thickness of 30-100 nm and an opening 41 corresponding to one of the source / drain regions. Referring to FIG. 2F, using the patterned polycrystalline silicon layer 40 as a hard mask, the first and second inner dielectric layers 36 and 38 are dry-etched until the diffusion barrier layer 34 is exposed, thereby A contact hole 42 is formed in the first and second inner dielectric layers above one of the source / drain regions 30, 32. Subsequently, a thermal oxidation process is performed to oxidize the patterned polycrystalline silicon layer 40 into a silicon monoxide layer 40 '. -8 * This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). Description of the invention (After the contact hole 42 is formed, the blanket dry etching method (Blanket
Dry Etching)去除在該源極/汲極區域30、32中之一上及 該接觸孔42中之所曝露之該擴散阻障層34(如圖2G所 示）。 參考圖2H，藉由金屬濺鍍或化學氣相沈積製程形成一具 有20-60nm厚度之Ti/TiN層44於該氧化碎層40,及該接 觸孔42之内壁。接下來，藉由化學氣相沈積法形成一插塞 (例如··一鎢插塞）4 6於該Ti/TiN層44上，並且完全地填 充該接觸孔42。藉由化學機械式研磨製程平坦化該插塞 46、該Ti/TiN層44及該氧化矽層40,。 在本發明之另一實施例中，一種用以防止一圖案化之電 性導電層在接觸孔形成期間受氧化之方法除了提供一具有 一部分已完成之裝置結構之基板，其包括一圖案化電性導 電層外，其包括幾乎與第一實施例完全相同之步驟。該圖 案化之電性導電層對應於該先前實施例之源極/汲極區域。 本發明之優點在於··不易研磨之不會形成於該氧 化矽層40’之頂部，此將有利於於隨後化學機械式研磨之實 施。本發明另外之優點在於··在圖案化之複晶矽層4〇之氧 化期間，在該接觸孔42中所曝露之該擴散阻障層34可防 止该源極/汲極區域30、32之氧化。因為該源極/汲極區域 不會因氧化而變薄，所以在該M〇s電晶體操作時不會產生 經由该源極/汲極區域30、32及該基板20之漏電流。 雖然本發明巳以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技術者，在不脫離本發明之精 567552 A7 B7 五、發明説明（6 ) 神和範圍内，當可做各種之更動與潤飾，而本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)Dry Etching) removes the diffusion barrier layer 34 exposed on one of the source / drain regions 30, 32 and in the contact hole 42 (as shown in FIG. 2G). Referring to FIG. 2H, a Ti / TiN layer 44 having a thickness of 20-60 nm is formed on the oxide chip 40 and the inner wall of the contact hole 42 by a metal sputtering or chemical vapor deposition process. Next, a plug (for example, a tungsten plug) 4 6 is formed on the Ti / TiN layer 44 by the chemical vapor deposition method, and the contact hole 42 is completely filled. The plug 46, the Ti / TiN layer 44 and the silicon oxide layer 40 are planarized by a chemical mechanical polishing process. In another embodiment of the present invention, a method for preventing a patterned electrical conductive layer from being oxidized during contact hole formation. In addition to providing a substrate having a partially completed device structure, the method includes a patterned electrical layer. Outside the conductive layer, it includes almost the same steps as the first embodiment. The patterned electrically conductive layer corresponds to the source / drain region of the previous embodiment. The advantage of the present invention is that it is difficult to grind and will not be formed on top of the silicon oxide layer 40 ', which will facilitate the subsequent implementation of chemical mechanical polishing. Another advantage of the present invention is that during the oxidation of the patterned polycrystalline silicon layer 40, the diffusion barrier layer 34 exposed in the contact hole 42 can prevent the source / drain regions 30, 32 from being exposed. Oxidation. Because the source / drain regions are not thinned by oxidation, no leakage current is generated through the source / drain regions 30, 32 and the substrate 20 during the operation of the MOS transistor. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art will not deviate from the essence of the present invention 567552 A7 B7 V. Description of the invention (6) Within the scope of God Various modifications and retouching can be done, and the protection scope of the present invention shall be determined by the scope of the attached patent application. -10- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)