TWI463601B - Method for fabricating contact hole - Google Patents

Description

Contact hole plug manufacturing method

The present invention relates to a method of fabricating a contact plug, and more particularly to a method of controlling an etch profile of a contact plug.

In the nano-semiconductor process, as the generation of micro-scale processes evolves, the ability to control the profile profile is bound to face challenges. In the prior art, a poly-etching process is often performed by a chemical etching method, and thus a vertical etch profile is a problem that the semiconductor development needs to overcome.

A conventional dynamic access memory (DRAM) system uses a reverse contact plug process to fabricate a contact plug process having a high aspect ratio. The reverse contact plug is first formed by etching a polycrystalline germanium material to define a shape of the contact hole, and then filling the oxide dielectric layer into the gap between the polycrystalline columns. The polycrystalline germanium column is removed by the polycrystalline germanium to remove the polycrystalline germanium column to form a contact hole.

However, a typical polysilicon etch process utilizes fluorine, hydrogen bromide, and oxygen as the etching gas, and the etching profile is adjusted by the hydrogen bromide/oxygen ratio (HBr/O2 ratio). Lowering the hydrogen bromide/oxygen ratio results in a more vertical etch profile but causes the bottom polysilicon compound to remain and the etching stop, creating a contact-to-contact short problem. In addition, increase the hydrogen bromide / oxygen ratio to improve the contact hole plug short circuit problem When the polycrystalline column is subjected to profile notching, the polycrystalline column breaks and the electrical resistance of the contact plug increases, which may adversely affect the component yield or electrical properties.

Accordingly, there is a need in the art for a method of fabricating a contact plug having a high aspect ratio and having a vertical sidewall profile to alleviate the above disadvantages.

An embodiment of the present invention provides a method of fabricating a contact plug, including providing a semiconductor substrate, wherein a plurality of insulators extending along a first direction are disposed, and wherein the semiconductor substrate has a second direction extending a plurality of transistor structures; a plurality of conductive sacrificial layers are deposited; a plurality of hard mask patterns formed on the conductive sacrificial layer, the hard mask patterns are arranged in an array along the first direction and the second direction; a first etching gas is subjected to a first anisotropic etching process to remove a portion of the conductive sacrificial layer not covered by the hard mask patterns until the oxidized protective layer on top of the plurality of transistor structures is exposed; Using a second etching gas, performing a second anisotropic etching process to remove a portion of the conductive sacrificial layer not covered by the hard mask patterns to form a plurality of conductive sacrificial patterns, wherein the conductive sacrificial patterns are a plurality of bottoms are connected to each other; an oxidation process is performed to form plural numbers on the sidewalls of the conductive sacrificial patterns, respectively Oxidation protection layer; using a third etching gas, performing a third anisotropic etching process, removing a plurality of sidewalls of the conductive sacrificial patterns not covered by the hard mask patterns and removing portions of the bottom surfaces The oxide protective layer and some of the conductive sacrificial patterns; performing a fourth anisotropic etching process using a fourth etching gas The above-mentioned bottom portions of the above-mentioned conductive sacrificial patterns which are not covered by the above-mentioned hard mask patterns are connected to each other to form a plurality of conductive sacrificial columns separated from each other.

500‧‧‧Contact hole plug

200‧‧‧Semiconductor substrate

201‧‧‧Shallow trench isolation

202‧‧‧ surface

204‧‧‧Insulation mat

206‧‧‧ Conductive sacrificial layer

206a, 206b, 206c‧‧‧ conductive sacrificial patterns

208‧‧‧hard mask pattern

210, 210a, 210b, 210c, 210d‧‧‧ trench

212, 212a, 212b, 212c‧‧‧ bottom

214, 222‧‧‧ side wall

216, 216a‧‧ ‧ oxidized protective layer

220‧‧‧ Conductive Sacrificial Column

226‧‧‧Optoelectronic structure

228‧‧‧Oxide layer;

232‧‧‧ dielectric materials

232a‧‧‧ dielectric layer

240‧‧‧Contact hole opening

302‧‧‧First direction

304‧‧‧second direction

H1, H2, H3‧‧‧ Depth

T1‧‧‧ thickness

1a-3a are top schematic views showing a method of manufacturing a contact plug according to an embodiment of the present invention.

1b to 3b are schematic cross-sectional views showing a method of manufacturing a contact plug according to an embodiment of the present invention taken along line A-A' of Fig. 1a.

1c to 3c are schematic cross-sectional views showing a method of manufacturing a contact plug according to an embodiment of the present invention taken along line B-B' of Fig. 1a.

4 to 9 are schematic cross-sectional views showing a subsequent process step of the contact hole plug along the A-A' tangent line of Fig. 1a according to the embodiment of the present invention.

1a-3a are top plan views showing a method of manufacturing the contact plug 500 according to the embodiment of the present invention. 1b to 3b are schematic cross-sectional views showing a method of manufacturing a contact plug according to an embodiment of the present invention taken along line A-A' of Fig. 1a. 1c to 3c are schematic cross-sectional views showing a method of manufacturing a contact plug according to an embodiment of the present invention taken along line B-B' of Fig. 1a. In addition, FIGS. 4-9 are schematic cross-sectional views showing a subsequent process step of the contact hole plug along the A-A' tangent line of FIG. 1a according to the embodiment of the present invention. As shown in FIGS. 1a to 1c, a semiconductor substrate 200 is provided. The contact hole plug 500 of the embodiment of the present invention can be used as a contact hole plug of a bit line or a word line of a dynamic access memory (DRAM), and the contact hole plug 500 of the embodiment of the present invention has a high aspect ratio. , for example, greater than or equal to 7:1. In other embodiments, however, the contact plug 500 can also serve as a contact plug for other components. In the present invention In an embodiment, the semiconductor substrate 200 may be a germanium substrate. The semiconductor substrate 200 can be implanted with a p-type or n-type dopant to change its conductivity type for design needs. As shown in FIG. 1b, the semiconductor substrate 200 has a plurality of trenches (located at the occupying position of the shallow trench isolation 201) extending in a first direction 302 (bit line direction), and a plurality of shallow trenches are isolated. The objects 201 are respectively disposed in a plurality of trenches extending along the first direction 302. The shallow trench isolations 201 are used to isolate a plurality of bit lines (not shown) located in the trenches from each other. Further, as shown in FIG. 1c, the semiconductor substrate 200 has a plurality of transistor structures 226 extending in a second direction 304 (word line direction). In an embodiment of the invention, the transistor structure 226 is a vertical transistor structure, where vertical means perpendicular to the normal direction of the surface 202 of the semiconductor substrate 200. The gate of the vertical transistor structure is located on the vertical sidewall of the vertical transistor structure and is used as a word line. The shallow trench isolation 201 and the transistor structure 226 are located at different vertical heights, separated from each other by a plurality of shallow trench isolations 201. As shown in FIG. 1b, an insulating pad layer 204 is disposed on the surface 202 of the semiconductor substrate 200 for isolating the bit line and the transistor structure 226 in the normal direction of the surface 202 of the semiconductor substrate 200, and is used for An etch stop layer for the subsequently formed conductive sacrificial post. In an embodiment of the invention, the insulating pad layer 204 can be yttrium oxide.

Next, a conductive sacrificial layer 206 may be deposited on the insulating underlayer 204 in a manner such as chemical vapor deposition (CVD) to cover the transistor structure 226. In an embodiment of the invention, the conductive sacrificial layer 206 may be a polysilicon.

A plurality of hard mask patterns 208 formed on the conductive sacrificial layer 206 can then be formed using a deposition process and a subsequent patterning process. Such as 1a~1c As shown, the hard mask pattern 208 is arranged in an array along the first direction 302 and the second direction 304, and in the top view as shown in FIG. 1a, the hard mask pattern 208 is located in each of the two crystal structures 226. Side, which is used to define the location at which the contact plug is formed.

Since a layer of native oxide is formed on the surface of the conductive sacrificial layer 206 formed of polysilicon, a native oxide removal process can be performed. Thereafter, as shown in FIGS. 1a to 1c, an anisotropic etching process such as a dry etching process may be performed using an etching gas such as carbon tetrafluoride (CF ₄ ) to remove the unhardened mask pattern 208. A native oxide covering and formed on the surface of the conductive sacrificial layer 206. A portion of the conductive sacrificial layer 206 that is not covered by the hard mask pattern 208 is also removed during the process, thereby forming a trench 210 of depth H1 in the conductive sacrificial layer 206, and the bottom surface 212 of the trench 210 is located on top of the transistor structure 226. Above.

Next, as shown in FIGS. 2a-2c, a conductive sacrificial layer upper patterning process is performed to define a contour of the upper portion of the subsequently formed contact plug, where the upper portion means the contact hole above the transistor structure 226. Plug part. Using a mixture of hydrogen bromide and oxygen (HBr/O ₂ ) as an etching gas, an anisotropic etching process such as a dry etching process is performed to remove a portion of the conductive sacrificial layer not covered by the hard mask patterns. Until the oxidized protective layer 228 on top of the transistor structure 226 is exposed, a conductive sacrificial pattern 206a is formed, wherein the oxidized protective layer 228 can serve as an etch stop layer for the upper patterned process of the conductive sacrificial layer. After the anisotropic etching process as shown in FIGS. 2a-2c, a trench 210a having a depth H2 is formed in the conductive sacrificial pattern 206a, and the bottom surface 212a of the trench 210a and the oxidation protection at the top of the transistor structure 226 Layer 228 is coplanar. During the upper patterning process of the conductive sacrificial layer, the ratio of hydrogen bromide to oxygen (HBr/O ₂ ratio) (for example, HBr/O ₂ = 255/10) can be adjusted to have a vertical profile of the sidewall of the trench 210a ( Even if the upper part of the contact plug has a vertical profile).

Then, as shown in FIGS. 3a-3c, a conductive sacrificial layer lower patterning process is performed to define a contour of a lower portion of the subsequently formed contact plug, where the lower portion means a contact hole under the transistor structure 226. Plug part. Using a mixture of hydrogen bromide and oxygen (HBr/O ₂ ) as an etching gas, performing an anisotropic etching process such as a dry etching process to remove a portion of the conductive sacrificial pattern not covered by the hard mask pattern 208, and The minimum thickness T1 of the conductive sacrificial layer is brought to a predetermined value. After the anisotropic etching process as shown in FIGS. 3a-3c, a plurality of conductive sacrificial patterns 206b are formed, wherein a plurality of bottom portions of the conductive sacrificial patterns 206b (near the bottom surface 212b of the trench 210b) are connected to each other and are electrically conductive. The sacrificial pattern 206b forms a trench 210b of depth H3, and the bottom surface 212b of the trench 210b will be lower than the oxidized protective layer 228 at the top of the transistor structure 226. During the lower patterning process of the conductive sacrificial layer, the ratio of hydrogen bromide to oxygen (HBr/O ₂ ratio) (eg, HBr/O ₂ = 255/10) can be adjusted, for example, as shown in Figures 2a-2c. The isotropic etching process reduces the flow of oxygen to reduce the ratio of hydrogen bromide to oxygen such that the sidewalls of trench 210b continue to have a vertical profile.

In addition, as shown in FIGS. 3b-3c, after the anisotropic etching process, a portion of the hard mask pattern 208 is also removed, so the size of the hard mask pattern 208 as shown in FIGS. 3b-3c is The height is less than the size and height of the hard mask pattern 208 as shown in Figures 2a-2c. And, as shown in Figure 3a, After the anisotropic etch process described above, the exposed oxide layer 228 at the top of the transistor structure 226 will be exposed to an area greater than the exposed area of the oxide layer 228 as shown in FIG. 2a.

In order to protect the upper vertical contour of the conductive sacrificial pattern 206b as shown in FIGS. 3b to 3c, an oxide protective layer may be formed on the sidewall of the conductive sacrificial pattern 206b. Next, as shown in FIG. 4, an oxidation process such as thermal oxidation is performed to form a plurality of oxide protective layers 216 on the sidewalls 214 of the conductive sacrificial patterns 206b, respectively. As shown in FIG. 4, the thickness of the upper portion of the oxidized protective layer 216 near the hard mask pattern 208 may be greater than the thickness of the lower portion near the bottom of the conductive sacrificial pattern 206b.

Thereafter, the conductive sacrificial pattern 206b may be further subjected to an anisotropic etching process to finely adjust the contour of the lower portion of the conductive sacrificial pattern 206b such that the upper and lower portions of the conductive sacrificial pattern 206b have a vertical profile. Nitrogen trifluoride (NF ₃ ) can be used as an etching gas for an anisotropic etching process such as dry etching, which is not covered by the hard mask pattern 208 as shown in FIG. A portion of the oxide protective layer 216 and a portion of the conductive sacrificial pattern 206b are removed from the sidewall 214 and the bottom surface 212b of the conductive sacrificial pattern 206b to form the conductive sacrificial pattern 206c and the oxidized protective layer 216a as shown in FIG. After the above-described anisotropic etching process as shown in FIG. 5, the thickness of the oxide protective layer 216a is lowered, and since the thickness of the lower portion of the oxide protective layer 216a is smaller than the thickness of the upper portion, the bottom surface 212c of the trench 210c and the conductive portion are electrically conductive. The sidewall 214 of the sacrificial pattern 206c near the bottom surface 212c is exposed from the oxidized protective layer 216a. In addition, after the anisotropic etching process described above, the foot portion of the conductive sacrificial pattern 206c (that is, the portion of the conductive sacrificial pattern 206c near the bottom surface 212c of the trench 210c) is removed. Therefore, the width of the lower portion of the conductive sacrificial pattern 206c near the bottom surface 212 of the trench 210c may be equal to or greater than the width of the upper portion of the hard mask pattern 208.

Then, after fine-tuning the outline of the lower portion of the conductive sacrificial pattern, an anisotropic etching process may be further performed to form a plurality of conductive sacrificial pillars that are separated from each other and straight. As shown in FIG. 6, a mixture of hydrogen bromide and oxygen (HBr/O ₂ ) may be used as an etching gas, and an anisotropic etching process such as a dry etching process may be performed to remove the unmasked pattern 208. The covered oxide protective layer 216a and the electrically conductive sacrificial pattern 206c (as shown in FIG. 5) are connected to each other until the insulating mat 204 is exposed (or when the insulating mat 204 is exposed, the non-continuous non-continuation is performed. The isotropic etching process is performed for a period of time (ie, over etching) to form a plurality of conductive sacrificial pillars 220 separated by trenches 210d, and the sidewalls 222 of the conductive sacrificial pillars 220 have a vertical profile. In an embodiment, the conductive sacrificial post 220 has a high aspect ratio, such as greater than or equal to 7: 1. Additionally, the ratio of hydrogen bromide to oxygen (HBr/O ₂ ratio) can be readjusted during the conductive sacrificial post patterning process ( For example, HBr/O ₂ =255/5), for example, the anisotropic etching process as shown in Figures 3a to 3c reduces the flow rate of oxygen, increases the ratio of hydrogen bromide to oxygen, and prevents the residual of polycrystalline germanium at the bottom. Causes an electrical short circuit.

Thereafter, as shown in FIG. 7, a dielectric material 232 may be filled and the dielectric material 232 may be planarized by a deposition method such as spin-on and a subsequent etching back step. The top surface of the dielectric material 232 is coplanar with the top surface of the hard mask pattern 208. In an embodiment of the invention, the dielectric material 232 can be tantalum oxide.

Next, as shown in FIG. 8, an anisotropic etching step, such as dry etching, is performed to remove the hard mask pattern 208, the conductive sacrificial post 220, and a portion of the dielectric material 232 until the surface 202 of the semiconductor substrate 200 is exposed. Thus, a plurality of contact hole openings 240 are formed, and a dielectric layer 232a having a lower height than the dielectric material 232 is formed.

Then, as shown in FIG. 9, a chemical vapor deposition (CVD) deposition method and a subsequent etch back step may be used to fill a contact hole opening 240 with a conductive material such as metal and planarize the conductive material. The surface is coplanar with the top surface of the dielectric layer 232a. After the above process, a plurality of straight contact plugs 500 are formed, separated from each other by a dielectric layer 232a.

Embodiments of the present invention provide a method of fabricating a contact hole plug having a high aspect ratio, which is particularly suitable for a reverse contact plug process. In order to avoid the formation of a conductive sacrificial post for defining a contact plug, the conductive sacrificial post is broken due to a long etching process and insufficient protection of the sidewall of the conductive sacrificial post. Therefore, during the conductive sacrificial column patterning process, an etching gas having a lower hydrogen bromide/oxygen ratio (HBr/O ₂ ratio) (ie, a higher oxygen flow rate) is first used to maintain a vertical profile of the upper portion of the conductive sacrificial column. . In addition, in order to protect the vertical profile of the upper portion of the conductive sacrificial column, the contact hole plug of the embodiment of the present invention is fabricated by adding an oxidation process and an anisotropic chemical etching process after etching to form the bottom interconnected conductive sacrificial post. The oxidation process is formed on the sidewall of the conductive sacrificial post to form an oxide layer, and the upper portion of the oxide layer is thicker than the lower portion to protect the subsequent anisotropic chemical etching process from lateral etching of the upper portion of the conductive sacrificial column. Side wall profile. The anisotropic chemical etching process can correct the sidewall profile of the lower portion of the conductive sacrificial column, so that the lower portion of the conductive sacrificial column also has a vertical profile. Finally, an anisotropic etching process is performed with a higher hydrogen bromide/oxygen ratio (HBr/O ₂ ratio) etching gas (ie, a lower oxygen flow rate) to form a high aspect ratio with vertical sidewalls. The conductive sacrificial column can avoid the problem that the contact hole plug short circuit or the contact hole plug resistance is too high in the conventional process, and the electrical or yield of the component is improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application.

200‧‧‧Semiconductor substrate

201‧‧‧Shallow trench isolation

202‧‧‧ surface

204‧‧‧Insulation mat

206b‧‧‧ Conductive sacrificial pattern

208‧‧‧hard mask pattern

210b‧‧‧ trench

212b‧‧‧ bottom

214‧‧‧ side wall

216‧‧‧Oxidation protective layer

Claims (8)

A method of manufacturing a contact plug includes the steps of: providing a semiconductor substrate, wherein a plurality of insulators extending along a first direction are disposed, and wherein the semiconductor substrate has a plurality of transistors extending in a second direction a plurality of hard mask layers are formed on the conductive sacrificial layer, the hard mask patterns are arranged in an array along the first direction and the second direction; using a first etching gas Performing a first anisotropic etching process to remove a portion of the conductive sacrificial layer not covered by the hard mask patterns until an oxidized protective layer on top of the plurality of transistor structures is exposed; using a second etch And performing a second anisotropic etching process to remove a portion of the conductive sacrificial layer not covered by the hard mask patterns to form a plurality of conductive sacrificial patterns, wherein the plurality of bottom portions of the conductive sacrificial patterns are mutually Connecting, performing an oxidation process to form a plurality of oxide protective layers on sidewalls of the conductive sacrificial patterns respectively; using a third etching gas, Performing a third anisotropic etching process, removing a plurality of sidewalls of the conductive sacrificial patterns that are not covered by the hard mask patterns, and removing portions of the oxide protective layers and portions of the conductive sacrificial portions from the bottom surfaces And using a fourth etching gas to perform a fourth anisotropic etching process to remove the bottom portions of the conductive sacrificial patterns not covered by the hard mask patterns to form a separation from each other A plurality of conductive sacrificial columns. The method for manufacturing a contact hole plug according to claim 1, wherein the conductive sacrificial layer is made of polysilicon, and the hard mask patterns are made of tantalum nitride. The method for manufacturing a contact plug according to claim 1, wherein the conductive sacrificial layer has a native oxide thereon, and before the performing the first anisotropic etching process, the method further comprises: using a fifth etching The gas is subjected to a fifth anisotropic etch process to remove the native oxide that is not covered by the hard mask patterns. The method of manufacturing the contact hole plug of claim 1, wherein the width of the first portion of the conductive sacrificial pattern adjacent to the bottom portions before the third anisotropic etching process is greater than the harder The width of the second portion of the mask pattern. The method for manufacturing a contact plug according to claim 4, wherein a thickness of the third portion of the oxidized protective layer adjacent to the hard mask patterns is greater than a thickness of the oxidized protective layer adjacent to the conductive sacrificial patterns. The thickness of the fourth portion of the bottom portion. The method for manufacturing a contact hole plug according to claim 1, wherein after the third anisotropic etching process, the bottom portions of the conductive sacrificial patterns and the portions adjacent to the bottom portions are sidewalls It is exposed from the oxidized protective layers. The method for manufacturing a contact plug according to claim 1, wherein the conductive sacrificial pillars have an aspect ratio greater than or equal to 7:1. The method for manufacturing a contact hole plug according to claim 1, further comprising: Fully filling a dielectric material and coplaning a top surface of the dielectric material with the top surface of the hard mask patterns; removing the hard mask patterns and the conductive sacrificial pillars to form a plurality Contact holes are opened; and a conductive material is filled in the contact hole openings to form a plurality of contact hole plugs.