KR20110119047A - Forming method of semiconductor having buried gate - Google Patents

Forming method of semiconductor having buried gate Download PDF

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KR20110119047A
KR20110119047A KR1020100038522A KR20100038522A KR20110119047A KR 20110119047 A KR20110119047 A KR 20110119047A KR 1020100038522 A KR1020100038522 A KR 1020100038522A KR 20100038522 A KR20100038522 A KR 20100038522A KR 20110119047 A KR20110119047 A KR 20110119047A
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storage node
node contact
buried gate
contact hole
device isolation
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최백일
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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Abstract

PURPOSE: A method for manufacturing a semiconductor device with a buried gate is provided to easily secure a contact area of a storage node contact by reducing an etching rate of the device isolation layer. CONSTITUTION: A buried gate(112) is formed in an active area(102) and a device isolation layer(104). A bit line is connected to the active area between the buried gates. An interlayer dielectric layer(128) includes the bit line. A storage node contact hole(130) is formed by etching the interlayer dielectric layer. Impurities are implanted into the device isolation layer exposed by the storage node contact hole. A storage node contact fills the storage node contact hole.

Description

매립 게이트를 갖는 반도체 소자의 제조 방법{Forming method of semiconductor having buried gate}Forming method of semiconductor having buried gate

본 발명은 매립 게이트를 갖는 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 스토리지노드콘택(SNC)과 매립 게이트 간의 브릿지 발생을 최소화하면서 스토리지노드콘택의 접촉 면적을 확보할 수 있는 매립 게이트(buried gate)를 갖는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device having a buried gate, and more particularly, to a buried gate capable of securing a contact area of the storage node contact while minimizing the occurrence of a bridge between the storage node contact (SNC) and the buried gate. A method for manufacturing a semiconductor device having a gate).

현재 반도체 공정에서 미세화가 진행됨에 따른 여러 가지 소자특성과 공정 구현이 힘들어 지고 있다. 특히 40nm 이하로 갈수록 게이트 구조, 비트라인 구조, 콘택 구조 등의 형성이 한계를 보이고 있고, 가령 구조가 형성된다 하더라도 소자특성에 만족할 수 있는 저항특성이나 리프레시(refresh), 로우페일(low fail) 확보, 파괴전압(BV) 특성 등의 어려움이 존재하고 있다. 이에 최근에는 매립 게이트(Buried gate)(또는 매립 워드라인)를 적용하여 반도체 장치의 신뢰성 및 집적도를 확보하는 다양한 방법들이 시도되고 있다.As micronization progresses in the semiconductor process, various device characteristics and process implementations are becoming difficult. In particular, the formation of the gate structure, the bit line structure, and the contact structure is showing a limit as it goes down to 40 nm or less. For example, even if the structure is formed, it is possible to secure a resistance characteristic, a refresh (refresh) or a low fail that can satisfy the device characteristics. And breakdown voltage (BV) characteristics are present. Recently, various methods for securing reliability and integration of semiconductor devices by applying a buried gate (or buried word line) have been attempted.

매립 게이트는 게이트를 반도체 기판의 내부에 매립함으로써 게이트(워드라인)와 비트라인 간의 기생 정전용량(Parasitic Capacitance)을 현저히 줄일 수 있다. 따라서 매립 게이트를 적용하면 메모리 장치의 센싱마진(Sensing Margin)을 크게 향상시킬 수 있는 장점이 있다.The buried gate can significantly reduce the parasitic capacitance between the gate (word line) and the bit line by embedding the gate inside the semiconductor substrate. Therefore, the application of the buried gate has an advantage of significantly improving the sensing margin of the memory device.

이러한 매립 게이트를 갖는 반도체 소자를 제조시, 스토리지노드콘택(SNC)과 활성 영역의 접촉 면적을 넓히기 위해 스토리지노드 콘택홀을 형성한 후 그 하부를 추가 식각하여 확장시키는 공정을 진행한다.In manufacturing a semiconductor device having such a buried gate, a process of forming a storage node contact hole to expand the contact area between the storage node contact (SNC) and the active region and further etching the lower portion thereof is performed.

그런데, 이러한 식각 공정시에는 층간 절연막뿐만 아니라 소자분리막도 함께 식각되면서 후속 공정에서 스토리지노드콘택과 게이트 간의 브릿지를 유발하는 문제가 발생되고 있다. 즉, 스토리지노드 콘택홀의 하부를 측면 방향으로 확장(lateral widening)하기 위해 층간 절연을 식각하는 과정에서 그 하부의 소자분리막도 함께 식각되는데, 일반적으로 층간 절연막으로 사용되는 물질보다 소자분리막으로 사용되는 물질의 식각 속도가 빠르기 때문에 측면 방향으로의 식각보다도 아래 방향으로의 식각이 더 많이 이루어져 후속 공정에서 형성되는 스토리지노드콘택과 소자분리막에 매립된 게이트 사이의 거리를 가깝게 만드는 결과를 초래하게 되며 경우에 따라 이들 간의 브릿지가 발생될 수 있게 된다.However, in such an etching process, not only the interlayer insulating film but also the device isolation film are etched together, which causes a bridge between the storage node contact and the gate in a subsequent process. That is, in the process of etching the interlayer insulation to laterally widen the lower portion of the storage node contact hole, the device isolation layer is also etched together, which is generally used as the device isolation film rather than the material used as the interlayer insulation film. Because the etching speed of is faster, the etching in the downward direction is more than that in the lateral direction, resulting in a close distance between the storage node contact formed in a subsequent process and the gate embedded in the device isolation layer. A bridge between them can be generated.

본 발명의 목적은 스토리지노드와 매립 게이트 간의 브릿지 발생을 최소화하면서 스토리지노드콘택의 접촉 면적을 확보하고자 한다.An object of the present invention is to secure the contact area of the storage node contact while minimizing the occurrence of bridge between the storage node and the buried gate.

본 발명의 반도체 소자 제조 방법은 활성영역 및 소자분리막 내에 제 1 방향으로 전극 물질을 매립하여 매립 게이트를 형성하는 단계, 상기 활성영역에서 인접한 상기 매립 게이트들 사이의 활성영역과 연결되며 제 2 방향으로 연장되는 비트라인을 형성하는 단계, 상기 비트라인을 포함하는 층간 절연막을 형성하는 단계, 상기 층간 절연막을 식각하여 스토리지노드 콘택홀을 형성하는 단계, 상기 스토리지노드 콘택홀에 의해 노출된 상기 소자분리막에 불순물을 주입하는 단계, 상기 스토리지노드 콘택홀의 저면을 확장시키는 단계 및 상기 스토리지노드 콘택홀을 매립하는 스토리지노드콘택을 형성하는 단계를 포함한다.In the semiconductor device fabrication method of the present invention, a buried gate is formed by filling an electrode material in an active region and a device isolation layer in a first direction, and connected to an active region between the buried gates adjacent to the active region in a second direction. Forming an extending bit line, forming an interlayer insulating film including the bit line, etching the interlayer insulating film to form a storage node contact hole, and forming a storage node contact hole in the device isolation layer exposed by the storage node contact hole. Implanting impurities, expanding a bottom surface of the storage node contact hole, and forming a storage node contact to fill the storage node contact hole.

이처럼 본 발명은 스토리지노드 콘택홀시 노출된 소자분리막에 불순물을 주입하여 소자분리막의 식각율을 감소시킴으로써 스토리지노드 콘택홀의 하부를 확장시 소자분리막이 덜 식각되도록 하여 스토리지노드와 매립 게이트 간의 브릿지 발생을 최소화하면서 스토리지노드콘택의 접촉 면적을 확보할 수 있도록 해준다.As such, the present invention reduces the etch rate of the device isolation layer by injecting impurities into the device isolation layer exposed during the storage node contact hole so that the device isolation layer is less etched when the lower portion of the storage node contact hole is expanded to minimize the bridge between the storage node and the buried gate. This ensures that the contact area of the storage node contacts is secured.

본 발명에서 상기 불순물 주입 단계는 불활성 가스의 이온을 주입하며, 불활성 가스는 아르곤(Ar) 가스가 사용될 수 있다.In the present invention, the impurity implantation step injects ions of the inert gas, argon (Ar) gas may be used as the inert gas.

본 발명에서는 경사 이온 주입을 통해 상기 불순물을 주입할 수 있다.In the present invention, the impurity may be implanted through gradient ion implantation.

본 발명에서 상기 스토리지노드 콘택홀의 저면을 확장시키는 단계는 NH3, HF, Ar 가스를 이용한 비플라즈마(non plasma) 방식의 건식 식각(Dry cleaning) 방법이 사용될 수 있다.In the present invention, the step of expanding the bottom of the storage node contact hole may be a dry plasma method using a non plasma method using NH 3 , HF, and Ar gas.

본 발명에서 상기 소자분리막은 SOD(Spin On Dielectric)를 포함하며, 상기 층간 절연막은 LPTEOS(Low Pressure Tetra Ethyl Ortho Silicate)를 포함할 수 있다.In an embodiment, the device isolation layer may include spin on dielectric (SOD), and the interlayer insulating layer may include low pressure tetra ethyl ortho silicate (LPTEOS).

본 발명은 스토리지노드와 매립 게이트 간의 브릿지 발생을 최소화하면서 스토리지노드콘택의 접촉 면적을 보다 용이하게 확보할 수 있다.The present invention can more easily secure the contact area of the storage node contact while minimizing the occurrence of bridge between the storage node and the buried gate.

도 1은 본 발명의 일 실시 예에 따른 반도체 소자가 적용되는 4F2 구조를 나타내는 평면도
도 2 내지 도 10은 본 발명의 일 실시 예에 따른 반도체 소자를 제조하는 방법을 설명하기 위한 공정 단면도들1 is a plan view showing a 4F 2 structure to which a semiconductor device according to an embodiment of the present invention is applied
2 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1은 본 발명의 일 실시 예에 따른 반도체 소자가 적용되는 4F2 구조를 나타내는 평면도이며, 도 2 내지 도 10은 본 발명의 일 실시 예에 따른 반도체 소자를 제조하는 방법을 설명하기 위한 공정 단면도들이다. 이때, 도 2 내지 도 10에서, (a)는 도 1에서 X-X' 방향에 따른 단면도이며 (b)는 도 1에서 Y-Y' 방향에 따른 단면도이다.1 is a plan view showing a 4F 2 structure to which a semiconductor device according to an embodiment of the present invention is applied, and FIGS. 2 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. admit. 2 to 10, (a) is a cross-sectional view taken along the XX 'direction in Figure 1 (b) is a cross-sectional view taken along the YY' direction in FIG.

도 2를 참조하면, STI(Shallow Trench Isolation) 공정을 이용하여 소자분리영역의 반도체 기판(100)을 일정 깊이 식각하여 트렌치(미도시)를 형성한 후 트렌치가 매립되도록 절연막(SOD:Spin On Dielectric)을 형성함으로써 활성 영역(102)을 정의하는 소자분리막(104)을 형성한다. 반도체 기판(100) 상에 소자분리막(104)이 형성되는 깊이는 대략 3000 Å 정도이다.Referring to FIG. 2, a trench (not shown) is formed by etching a semiconductor substrate 100 in a device isolation region by using a shallow trench isolation (STI) process to form a trench (not shown), so that the trench is filled with an insulating film (SOD). Is formed to form the device isolation film 104 defining the active region 102. The device isolation film 104 is formed on the semiconductor substrate 100 to have a depth of about 3000 GPa.

도 3을 참조하면, 활성 영역(102) 및 소자분리막(104) 상에 절연막(106)을 형성한 후 절연막(106) 상에 매립 게이트 영역을 정의하는 감광막 패턴(미도시)을 형성한다.Referring to FIG. 3, an insulating film 106 is formed on the active region 102 and the device isolation film 104, and then a photoresist pattern (not shown) defining a buried gate region is formed on the insulating film 106.

이어서, 감광막 패턴을 식각 마스크로 절연막(106)을 식각하여 절연막 패턴(106)을 형성하고, 절연막 패턴(106)을 식각 마스크로 활성 영역(102) 및 소자분리막(104)을 식각하여 리세스(110)를 형성한다. 이때, 리세스(110)는 1100 ~ 1300 Å의 깊이로 형성되며, 하나의 활성 영역에는 두 개의 리세스(110)가 형성되고 활성 영역(102) 사이의 소자분리막(104)에는 하나의 리세스(110)가 형성된다.Subsequently, the insulating layer 106 is etched using the photoresist pattern as an etch mask to form the insulating layer pattern 106, and the active region 102 and the device isolation layer 104 are etched using the insulating layer pattern 106 as an etch mask to form a recess. 110). At this time, the recess 110 is formed to a depth of 1100 ~ 1300 Å, two recesses 110 are formed in one active region and one recess in the device isolation film 104 between the active regions 102. 110 is formed.

다음에, 리세스(110) 내부면을 포함한 반도체 기판 전체 상부에 장벽금속막(108)을 형성한다. 장벽 금속막(108)은 후속 공정에서 매립 게이트가 금속 물질로 형성될 때 금속 이온이 활성 영역(102) 및 소자분리막(104)으로 확산되는 것을 방지하기 위함이다. 이때, 장벽금속막(108)은 TiN을 포함하며, 장벽금속막(108)을 형성하기 전, 리세스(108)의 하부에 불순물을 이온 주입하여 채널 영역을 형성하고 리세스(108)의 하부 및 측벽에 게이트 절연막을 형성한다.Next, a barrier metal film 108 is formed over the entire semiconductor substrate including the inner surface of the recess 110. The barrier metal film 108 is intended to prevent the diffusion of metal ions into the active region 102 and the device isolation film 104 when the buried gate is formed of a metal material in a subsequent process. In this case, the barrier metal film 108 includes TiN, and before the barrier metal film 108 is formed, an ion is implanted into the lower portion of the recess 108 to form a channel region and the lower portion of the recess 108. And a gate insulating film on the sidewalls.

다음에 도 4를 참조하면, 리세스(108)가 매립되도록 장벽금속막(108) 상에 도전 물질을 형성한 후 도전 물질을 에치백(etch-back)하여 리세스(108)의 하부에만 도전 물질이 남도록 함으로써 매립 게이트(112)를 형성한다. 이때, 매립 게이트 형성을 위한 도전 물질은 텅스텐(W) 등과 같은 금속 물질을 포함할 수 있다. 매립 게이트(112)로 금속 물질을 사용하는 이유는 금속과 실리콘 간의 전하 이동 등과 관련된 물리적 성질의 차이를 이용하여 게이트의 문턱전압의 마진을 확보하는데 유리하기 때문이다.Referring next to FIG. 4, after the conductive material is formed on the barrier metal film 108 so that the recess 108 is buried, the conductive material is etched back to conduct only the lower portion of the recess 108. The buried gate 112 is formed by allowing material to remain. In this case, the conductive material for forming the buried gate may include a metal material such as tungsten (W). The reason for using the metal material as the buried gate 112 is that it is advantageous to secure the margin of the threshold voltage of the gate by using a difference in physical properties related to charge transfer between the metal and silicon.

이러한 에치백 공정에서 절연막 패턴(106)의 상부 및 리세스(108) 상부 측벽에 있던 장벽금속막(108)도 대부분 식각되어 제거되나 금속 잔유물을 제거하기 위해 에치백 공정 이후 클리닝 공정을 수행한다.In such an etch back process, most of the barrier metal layer 108 on the upper sidewall of the insulating layer pattern 106 and the recess 108 is also etched and removed, but a cleaning process is performed after the etch back process to remove metal residues.

다음에 도 5를 참조하면, 리세스(110)가 매립되도록 매립 게이트(112) 상부에 실링 절연막(114)을 형성한 후 이를 평탄화(CMP)함으로써 리세스(110) 내부의 매립 게이트(112) 상부에만 실링 절연막(114)이 형성되도록 한다. 이때, 절연막(112)은 산화막 또는 질화막을 포함할 수 있다.Next, referring to FIG. 5, the buried gate 112 is formed in the recess 110 by forming a sealing insulating layer 114 on the buried gate 112 so that the recess 110 is buried, and then planarizing it (CMP). The sealing insulating layer 114 is formed only on the upper portion. In this case, the insulating film 112 may include an oxide film or a nitride film.

다음에 도 6을 참조하면, 절연막(114)을 포함하는 활성영역(102) 및 소자분리막(104) 상부에 층간절연막(116)을 형성한다. 이때, 층간절연막(116)은 LPTEOS(Low Pressure Tetra Ethyl Ortho Silicate)를 포함한다.Next, referring to FIG. 6, an interlayer insulating layer 116 is formed over the active region 102 including the insulating layer 114 and the device isolation layer 104. In this case, the interlayer insulating layer 116 includes LPTEOS (Low Pressure Tetra Ethyl Ortho Silicate).

다음에 층간절연막(116) 상부에 비트라인콘택 영역을 정의하는 감광막 패턴(미도시)을 형성한 후 이를 식각 마스크로 활성 영역(102)이 노출되도록 층간절연막(116)을 식각하여 비트라인 콘택홀(미도시)을 형성한다. 이어서, 비트라인 콘택홀이 매립되도록 콘택 물질(예컨대, 폴리실리콘)(118)을 형성한다.Next, a photoresist pattern (not shown) defining a bit line contact region is formed on the interlayer insulating layer 116, and the interlayer insulating layer 116 is etched to expose the active region 102 using an etch mask, thereby etching the bit line contact hole. (Not shown) is formed. Subsequently, a contact material (eg, polysilicon) 118 is formed to fill the bit line contact holes.

다음에 도 7을 참조하면, 층간절연막(116)이 노출되도록 콘택 물질(118)을 평탄화함으로써 비트라인콘택(119)을 형성한다.Next, referring to FIG. 7, the bit line contact 119 is formed by planarizing the contact material 118 to expose the interlayer insulating layer 116.

다음에, 비트라인콘택(119) 상부에 비트라인 전극물질(120) 및 하드마스크막(122)을 순차적으로 형성한 후 비트라인 영역을 정의하는 감광막 패턴(미도시)을 식각 마스크로 하드마스크막(122) 및 비트라인 전극물질(120)을 패터닝하여 비트라인(124)을 형성한다. 이어서, 비트라인(124)의 측벽에 비트라인 스페이서(126)를 형성한다. 이때, 비트라인 스페이서(126)는 질화막을 포함한다.Next, the bit line electrode material 120 and the hard mask film 122 are sequentially formed on the bit line contact 119, and then a photoresist pattern (not shown) defining the bit line region is formed by using the hard mask film as an etching mask. The bit line 124 is formed by patterning the 122 and the bit line electrode material 120. Next, the bit line spacer 126 is formed on the sidewall of the bit line 124. In this case, the bit line spacer 126 includes a nitride film.

다음에, 층간절연막(116) 상부에 비트라인(124)을 포함하는 층간절연막(128)을 형성한 후 하드마스크(122)가 노출되도록 층간절연막(128)을 평탄화한다. 이때, 층간절연막(128)은 BPSG(Boron Phosphorus Silicate Glass)를 포함한다.Next, after the interlayer insulating layer 128 including the bit lines 124 is formed on the interlayer insulating layer 116, the interlayer insulating layer 128 is planarized to expose the hard mask 122. In this case, the interlayer insulating film 128 includes BPSG (Boron Phosphorus Silicate Glass).

다음에 도 8을 참조하면, 스토리지노드콘택 영역을 정의하는 감광막 패턴(미도시)을 식각 마스크로 활성영역(102)이 노출될 때까지 층간절연막(128, 116)을 식각하여 스토리지노드 콘택홀(130)을 형성한다. 이때, 스토리지노드 콘택홀(130)은 층간절연막(128, 116)과 비트라인 스페이서(126)의 식각선택비를 이용하여 형성될 수 있으며, 활성영역(102) 뿐만 아니라 소자분리막(104)도 노출될 수 있다.Next, referring to FIG. 8, the interlayer insulating layers 128 and 116 are etched using the photoresist pattern (not shown) defining the storage node contact region until the active region 102 is exposed using an etching mask. 130). In this case, the storage node contact hole 130 may be formed using an etch selectivity of the interlayer insulating layers 128 and 116 and the bit line spacer 126, and may expose the device isolation layer 104 as well as the active region 102. Can be.

다음에 도 9를 참조하면, 스토리지노드 콘택홀(130)를 통해 불활성 가스(예컨대, Ar 가스) 이온을 소자분리막(104)에 주입한다. 즉, 본 발명에서는 소자분리막(104)의 식각율을 감소시키기 위해 불활성 가스 이온을 소자분리막(104)에 주입한다. 불활성 가스는 소자의 특성에 영향을 주지 않으므로 이온 주입시 활성영역(102)에 이온이 주입되어도 무방하나, 가스 이온이 가능한 소자분리막(104)에 집중될 수 있도록 경사 이온 주입 방법이 이용될 수 있다.Next, referring to FIG. 9, inert gas (eg, Ar gas) ions are implanted into the device isolation layer 104 through the storage node contact hole 130. That is, in the present invention, inert gas ions are implanted into the device isolation film 104 to reduce the etch rate of the device isolation film 104. Since the inert gas does not affect the characteristics of the device, ions may be implanted into the active region 102 during ion implantation, but a gradient ion implantation method may be used so that gas ions may be concentrated on the device isolation film 104. .

본 실시 예에서와 같이 불활성 가스 이온이 소자분리막에 주입되는 경우 소자분리막의 식각율은 가스 주입 전에 비해 대략 20 ∼ 30 ％ 정도 감소 됨을 실험을 통해 알 수 있었다. 본 실시 예에서는 아르곤 이온을 주입하고 있으나 소자 특성에 영향을 주지 않으면서 소자분리막(104)의 식각율을 감소시킬 수 있는 다른 불순물을 주입할 수도 있다.As in the present embodiment, when the inert gas ions are injected into the device isolation film, the etching rate of the device isolation film is reduced by about 20 to 30% compared to before the gas injection. In the present exemplary embodiment, argon ions are implanted, but other impurities may be implanted to reduce the etching rate of the device isolation layer 104 without affecting device characteristics.

다음에 도 10을 참조하면, 아르곤 이온의 주입이 완료된 후 스토리지노드 콘택홀(130)의 하부를 식각하여 영역 'C'와 같이 스토리지노드 콘택홀(130)의 저면을 확장시킨다. 이때 식각 공정은 NH3, HF, Ar 가스를 이용한 비플라즈마(non plasma) 방식의 건식 식각(Dry cleaning) 방법이 사용될 수 있다.Next, referring to FIG. 10, after the implantation of argon ions is completed, the bottom surface of the storage node contact hole 130 is etched to extend the bottom surface of the storage node contact hole 130 as shown in region 'C'. At this time, the etching process may be a non-plasma dry cleaning method using NH 3 , HF, and Ar gas.

이때 본 실시 예에서는, 도 9에서와 같이, 스토리지노드 콘택홀(130)의 저면을 확장시키기 이전에 스토리지노드 콘택홀(130)에 의해 노출된 소자분리막(104)에 불활성 가스(Ar) 이온을 주입하여 소자분리막(102)의 식각율을 감소시킨 상태이므로, 기존과 동일한 조건으로 식각을 진행하는 경우 소자분리막(104) 보다 층간절연막(116)이 상대적으로 더 많이 식각됨으로써 스토리지노드와 매립 게이트 간의 브릿지 발생을 최소화하면서 스토리지노드콘택의 접촉 면적을 보다 확보할 수 있게 된다.In this embodiment, as shown in FIG. 9, inert gas (Ar) ions are applied to the device isolation layer 104 exposed by the storage node contact hole 130 before the bottom surface of the storage node contact hole 130 is expanded. Since the etching rate of the device isolation layer 102 is reduced by implantation, when the etching process is performed under the same conditions as before, the interlayer insulating layer 116 is etched relatively more than the device isolation layer 104, so that the gap between the storage node and the buried gate is increased. The contact area of the storage node contact can be more secured while minimizing the occurrence of bridges.

다음에, 스토리지노드 콘택홀(130)이 매립되도록 콘택 물질(plug poly)을 형성한 후 이를 평탄화함으로써 스토리지노드콘택(SNC)(132)을 형성한다.Next, a storage node contact (SNC) 132 is formed by forming a contact poly (plug poly) to planarize the storage node contact hole 130 and then planarizing it.

후속 공정으로 스토리지노드콘택 상부에 캐패시터를 형성하는 공정은 종래와 같은 방법으로 이루어질 수 있으므로 이에 대한 설명은 생략한다.Since a process of forming a capacitor on the storage node contact as a subsequent process may be made in the same manner as the conventional method, a description thereof will be omitted.

100 : 반도체 기판 102 : 활성영역
104 : 소자분리막 106 : 절연막 패턴
108 : 장벽금속막 110 : 리세스
112 : 매립 게이트 114 : 실링 절연막
116, 128 : 층간 절연막 118 : 콘택 물질
119 : 비트라인콘택 120 : 비트라인 전극물질
122 : 하드마스크막 124 : 비트라인
126 : 비트라인 스페이서 130 : 스토리지노드 콘택홀
132 : 스토리지노드콘택(SNC)100 semiconductor substrate 102 active region
104: device isolation layer 106: insulating film pattern
108: barrier metal film 110: recess
112: buried gate 114: sealing insulating film
116, 128: interlayer insulating film 118: contact material
119: bit line contact 120: bit line electrode material
122: hard mask 124: bit line
126: bit line spacer 130: storage node contact hole
132: storage node contact (SNC)

Claims (6)

활성영역 및 소자분리막 내에 제 1 방향으로 전극 물질을 매립하여 매립 게이트를 형성하는 단계;
상기 활성영역에서 인접한 상기 매립 게이트들 사이의 활성영역과 연결되며 제 2 방향으로 연장되는 비트라인을 형성하는 단계;
상기 비트라인을 포함하는 층간 절연막을 형성하는 단계;
상기 층간 절연막을 식각하여 스토리지노드 콘택홀을 형성하는 단계;
상기 스토리지노드 콘택홀에 의해 노출된 상기 소자분리막에 불순물을 주입하는 단계;
상기 스토리지노드 콘택홀의 저면을 확장시키는 단계; 및
상기 스토리지노드 콘택홀을 매립하는 스토리지노드콘택을 형성하는 단계를 포함하는 매립 게이트를 갖는 반도체 소자 제조 방법.Filling the electrode material in the first direction in the active region and the isolation layer to form a buried gate;
Forming a bit line connected to an active region between the buried gates adjacent to the active region and extending in a second direction;
Forming an interlayer insulating film including the bit line;
Etching the interlayer insulating layer to form a storage node contact hole;
Implanting impurities into the device isolation layer exposed by the storage node contact hole;
Extending a bottom of the storage node contact hole; And
And forming a storage node contact to fill the storage node contact hole. 제 1항에 있어서, 상기 불순물 주입 단계는
불활성 가스의 이온을 주입하는 것을 특징으로 하는 매립 게이트를 갖는 반도체 소자 제조 방법.The method of claim 1, wherein the impurity implantation step
A method of manufacturing a semiconductor device having a buried gate, characterized by implanting ions of an inert gas. 제 2항에 있어서, 상기 불활성 가스는
아르곤(Ar) 가스인 것을 특징으로 하는 매립 게이트를 갖는 반도체 소자 제조 방법.The method of claim 2, wherein the inert gas
A method of manufacturing a semiconductor device having a buried gate, which is an argon (Ar) gas. 제 1항에 있어서, 상기 불순물 주입 단계는
경사 이온 주입을 수행하는 것을 특징으로 하는 매립 게이트를 갖는 반도체 소자 제조 방법.The method of claim 1, wherein the impurity implantation step
A method of manufacturing a semiconductor device having a buried gate, characterized in that for performing a gradient ion implantation. 제 1항에 있어서, 상기 스토리지노드 콘택홀의 저면을 확장시키는 단계는
NH3, HF, Ar 가스를 이용한 비플라즈마(non plasma) 방식의 건식 식각(Dry cleaning) 방법이 사용되는 것을 특징으로 하는 매립 게이트를 갖는 반도체 소자 제조 방법.The method of claim 1, wherein the extending of the bottom of the storage node contact hole comprises:
A method of manufacturing a semiconductor device with a buried gate, characterized in that a non-plasma dry cleaning method using NH 3 , HF, and Ar gas is used. 제 1항에 있어서, 상기 층간 절연막은
LPTEOS(Low Pressure Tetra Ethyl Ortho Silicate)를 포함하는 것을 특징으로 하는 매립 게이트를 갖는 반도체 소자 제조 방법.The method of claim 1, wherein the interlayer insulating film
A method of manufacturing a semiconductor device having a buried gate, characterized in that it comprises Low Pressure Tetra Ethyl Ortho Silicate (LPTEOS).
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Publication number Priority date Publication date Assignee Title
US9165859B2 (en) 2013-04-08 2015-10-20 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US9202774B2 (en) 2013-07-31 2015-12-01 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US9419000B2 (en) 2013-11-13 2016-08-16 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices
US9508726B2 (en) 2014-08-18 2016-11-29 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10037996B2 (en) 2016-07-12 2018-07-31 Samsung Electronics Co., Ltd. Semiconductor device includes a substrate having conductive contact structures thereon

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165859B2 (en) 2013-04-08 2015-10-20 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US9202774B2 (en) 2013-07-31 2015-12-01 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US9419000B2 (en) 2013-11-13 2016-08-16 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices
US9953981B2 (en) 2013-11-13 2018-04-24 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices
US9508726B2 (en) 2014-08-18 2016-11-29 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10037996B2 (en) 2016-07-12 2018-07-31 Samsung Electronics Co., Ltd. Semiconductor device includes a substrate having conductive contact structures thereon

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