KR20110119047A - Forming method of semiconductor having buried gate - Google Patents

Forming method of semiconductor having buried gate Download PDF

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Publication number
KR20110119047A
KR20110119047A KR1020100038522A KR20100038522A KR20110119047A KR 20110119047 A KR20110119047 A KR 20110119047A KR 1020100038522 A KR1020100038522 A KR 1020100038522A KR 20100038522 A KR20100038522 A KR 20100038522A KR 20110119047 A KR20110119047 A KR 20110119047A
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KR
South Korea
Prior art keywords
storage node
node contact
buried gate
semiconductor
contact hole
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KR1020100038522A
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Korean (ko)
Inventor
최백일
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주식회사 하이닉스반도체
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Priority to KR1020100038522A priority Critical patent/KR20110119047A/en
Publication of KR20110119047A publication Critical patent/KR20110119047A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/06Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2252Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10885Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors
    • H01L29/66348Vertical insulated gate bipolar transistors with a recessed gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

PURPOSE: A method for manufacturing a semiconductor device with a buried gate is provided to easily secure a contact area of a storage node contact by reducing an etching rate of the device isolation layer. CONSTITUTION: A buried gate(112) is formed in an active area(102) and a device isolation layer(104). A bit line is connected to the active area between the buried gates. An interlayer dielectric layer(128) includes the bit line. A storage node contact hole(130) is formed by etching the interlayer dielectric layer. Impurities are implanted into the device isolation layer exposed by the storage node contact hole. A storage node contact fills the storage node contact hole.

Description

Forming method of semiconductor having buried gate
The present invention relates to a method of manufacturing a semiconductor device having a buried gate, and more particularly, to a buried gate capable of securing a contact area of the storage node contact while minimizing the occurrence of a bridge between the storage node contact (SNC) and the buried gate. A method for manufacturing a semiconductor device having a gate).
As micronization progresses in the semiconductor process, various device characteristics and process implementations are becoming difficult. In particular, the formation of the gate structure, the bit line structure, and the contact structure is showing a limit as it goes down to 40 nm or less. For example, even if the structure is formed, it is possible to secure a resistance characteristic, a refresh (refresh) or a low fail that can satisfy the device characteristics. And breakdown voltage (BV) characteristics are present. Recently, various methods for securing reliability and integration of semiconductor devices by applying a buried gate (or buried word line) have been attempted.
The buried gate can significantly reduce the parasitic capacitance between the gate (word line) and the bit line by embedding the gate inside the semiconductor substrate. Therefore, the application of the buried gate has an advantage of significantly improving the sensing margin of the memory device.
In manufacturing a semiconductor device having such a buried gate, a process of forming a storage node contact hole to expand the contact area between the storage node contact (SNC) and the active region and further etching the lower portion thereof is performed.
However, in such an etching process, not only the interlayer insulating film but also the device isolation film are etched together, which causes a bridge between the storage node contact and the gate in a subsequent process. That is, in the process of etching the interlayer insulation to laterally widen the lower portion of the storage node contact hole, the device isolation layer is also etched together, which is generally used as the device isolation film rather than the material used as the interlayer insulation film. Because the etching speed of is faster, the etching in the downward direction is more than that in the lateral direction, resulting in a close distance between the storage node contact formed in a subsequent process and the gate embedded in the device isolation layer. A bridge between them can be generated.
An object of the present invention is to secure the contact area of the storage node contact while minimizing the occurrence of bridge between the storage node and the buried gate.
In the semiconductor device fabrication method of the present invention, a buried gate is formed by filling an electrode material in an active region and a device isolation layer in a first direction, and connected to an active region between the buried gates adjacent to the active region in a second direction. Forming an extending bit line, forming an interlayer insulating film including the bit line, etching the interlayer insulating film to form a storage node contact hole, and forming a storage node contact hole in the device isolation layer exposed by the storage node contact hole. Implanting impurities, expanding a bottom surface of the storage node contact hole, and forming a storage node contact to fill the storage node contact hole.
As such, the present invention reduces the etch rate of the device isolation layer by injecting impurities into the device isolation layer exposed during the storage node contact hole so that the device isolation layer is less etched when the lower portion of the storage node contact hole is expanded to minimize the bridge between the storage node and the buried gate. This ensures that the contact area of the storage node contacts is secured.
In the present invention, the impurity implantation step injects ions of the inert gas, argon (Ar) gas may be used as the inert gas.
In the present invention, the impurity may be implanted through gradient ion implantation.
In the present invention, the step of expanding the bottom of the storage node contact hole may be a dry plasma method using a non plasma method using NH 3 , HF, and Ar gas.
In an embodiment, the device isolation layer may include spin on dielectric (SOD), and the interlayer insulating layer may include low pressure tetra ethyl ortho silicate (LPTEOS).
The present invention can more easily secure the contact area of the storage node contact while minimizing the occurrence of bridge between the storage node and the buried gate.
1 is a plan view showing a 4F 2 structure to which a semiconductor device according to an embodiment of the present invention is applied
2 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
1 is a plan view showing a 4F 2 structure to which a semiconductor device according to an embodiment of the present invention is applied, and FIGS. 2 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. admit. 2 to 10, (a) is a cross-sectional view taken along the XX 'direction in Figure 1 (b) is a cross-sectional view taken along the YY' direction in FIG.
Referring to FIG. 2, a trench (not shown) is formed by etching a semiconductor substrate 100 in a device isolation region by using a shallow trench isolation (STI) process to form a trench (not shown), so that the trench is filled with an insulating film (SOD). Is formed to form the device isolation film 104 defining the active region 102. The device isolation film 104 is formed on the semiconductor substrate 100 to have a depth of about 3000 GPa.
Referring to FIG. 3, an insulating film 106 is formed on the active region 102 and the device isolation film 104, and then a photoresist pattern (not shown) defining a buried gate region is formed on the insulating film 106.
Subsequently, the insulating layer 106 is etched using the photoresist pattern as an etch mask to form the insulating layer pattern 106, and the active region 102 and the device isolation layer 104 are etched using the insulating layer pattern 106 as an etch mask to form a recess. 110). At this time, the recess 110 is formed to a depth of 1100 ~ 1300 Å, two recesses 110 are formed in one active region and one recess in the device isolation film 104 between the active regions 102. 110 is formed.
Next, a barrier metal film 108 is formed over the entire semiconductor substrate including the inner surface of the recess 110. The barrier metal film 108 is intended to prevent the diffusion of metal ions into the active region 102 and the device isolation film 104 when the buried gate is formed of a metal material in a subsequent process. In this case, the barrier metal film 108 includes TiN, and before the barrier metal film 108 is formed, an ion is implanted into the lower portion of the recess 108 to form a channel region and the lower portion of the recess 108. And a gate insulating film on the sidewalls.
Referring next to FIG. 4, after the conductive material is formed on the barrier metal film 108 so that the recess 108 is buried, the conductive material is etched back to conduct only the lower portion of the recess 108. The buried gate 112 is formed by allowing material to remain. In this case, the conductive material for forming the buried gate may include a metal material such as tungsten (W). The reason for using the metal material as the buried gate 112 is that it is advantageous to secure the margin of the threshold voltage of the gate by using a difference in physical properties related to charge transfer between the metal and silicon.
In such an etch back process, most of the barrier metal layer 108 on the upper sidewall of the insulating layer pattern 106 and the recess 108 is also etched and removed, but a cleaning process is performed after the etch back process to remove metal residues.
Next, referring to FIG. 5, the buried gate 112 is formed in the recess 110 by forming a sealing insulating layer 114 on the buried gate 112 so that the recess 110 is buried, and then planarizing it (CMP). The sealing insulating layer 114 is formed only on the upper portion. In this case, the insulating film 112 may include an oxide film or a nitride film.
Next, referring to FIG. 6, an interlayer insulating layer 116 is formed over the active region 102 including the insulating layer 114 and the device isolation layer 104. In this case, the interlayer insulating layer 116 includes LPTEOS (Low Pressure Tetra Ethyl Ortho Silicate).
Next, a photoresist pattern (not shown) defining a bit line contact region is formed on the interlayer insulating layer 116, and the interlayer insulating layer 116 is etched to expose the active region 102 using an etch mask, thereby etching the bit line contact hole. (Not shown) is formed. Subsequently, a contact material (eg, polysilicon) 118 is formed to fill the bit line contact holes.
Next, referring to FIG. 7, the bit line contact 119 is formed by planarizing the contact material 118 to expose the interlayer insulating layer 116.
Next, the bit line electrode material 120 and the hard mask film 122 are sequentially formed on the bit line contact 119, and then a photoresist pattern (not shown) defining the bit line region is formed by using the hard mask film as an etching mask. The bit line 124 is formed by patterning the 122 and the bit line electrode material 120. Next, the bit line spacer 126 is formed on the sidewall of the bit line 124. In this case, the bit line spacer 126 includes a nitride film.
Next, after the interlayer insulating layer 128 including the bit lines 124 is formed on the interlayer insulating layer 116, the interlayer insulating layer 128 is planarized to expose the hard mask 122. In this case, the interlayer insulating film 128 includes BPSG (Boron Phosphorus Silicate Glass).
Next, referring to FIG. 8, the interlayer insulating layers 128 and 116 are etched using the photoresist pattern (not shown) defining the storage node contact region until the active region 102 is exposed using an etching mask. 130). In this case, the storage node contact hole 130 may be formed using an etch selectivity of the interlayer insulating layers 128 and 116 and the bit line spacer 126, and may expose the device isolation layer 104 as well as the active region 102. Can be.
Next, referring to FIG. 9, inert gas (eg, Ar gas) ions are implanted into the device isolation layer 104 through the storage node contact hole 130. That is, in the present invention, inert gas ions are implanted into the device isolation film 104 to reduce the etch rate of the device isolation film 104. Since the inert gas does not affect the characteristics of the device, ions may be implanted into the active region 102 during ion implantation, but a gradient ion implantation method may be used so that gas ions may be concentrated on the device isolation film 104. .
As in the present embodiment, when the inert gas ions are injected into the device isolation film, the etching rate of the device isolation film is reduced by about 20 to 30% compared to before the gas injection. In the present exemplary embodiment, argon ions are implanted, but other impurities may be implanted to reduce the etching rate of the device isolation layer 104 without affecting device characteristics.
Next, referring to FIG. 10, after the implantation of argon ions is completed, the bottom surface of the storage node contact hole 130 is etched to extend the bottom surface of the storage node contact hole 130 as shown in region 'C'. At this time, the etching process may be a non-plasma dry cleaning method using NH 3 , HF, and Ar gas.
In this embodiment, as shown in FIG. 9, inert gas (Ar) ions are applied to the device isolation layer 104 exposed by the storage node contact hole 130 before the bottom surface of the storage node contact hole 130 is expanded. Since the etching rate of the device isolation layer 102 is reduced by implantation, when the etching process is performed under the same conditions as before, the interlayer insulating layer 116 is etched relatively more than the device isolation layer 104, so that the gap between the storage node and the buried gate is increased. The contact area of the storage node contact can be more secured while minimizing the occurrence of bridges.
Next, a storage node contact (SNC) 132 is formed by forming a contact poly (plug poly) to planarize the storage node contact hole 130 and then planarizing it.
Since a process of forming a capacitor on the storage node contact as a subsequent process may be made in the same manner as the conventional method, a description thereof will be omitted.
100 semiconductor substrate 102 active region
104: device isolation layer 106: insulating film pattern
108: barrier metal film 110: recess
112: buried gate 114: sealing insulating film
116, 128: interlayer insulating film 118: contact material
119: bit line contact 120: bit line electrode material
122: hard mask 124: bit line
126: bit line spacer 130: storage node contact hole
132: storage node contact (SNC)

Claims (6)

  1. Filling the electrode material in the first direction in the active region and the isolation layer to form a buried gate;
    Forming a bit line connected to an active region between the buried gates adjacent to the active region and extending in a second direction;
    Forming an interlayer insulating film including the bit line;
    Etching the interlayer insulating layer to form a storage node contact hole;
    Implanting impurities into the device isolation layer exposed by the storage node contact hole;
    Extending a bottom of the storage node contact hole; And
    And forming a storage node contact to fill the storage node contact hole.
  2. The method of claim 1, wherein the impurity implantation step
    A method of manufacturing a semiconductor device having a buried gate, characterized by implanting ions of an inert gas.
  3. The method of claim 2, wherein the inert gas
    A method of manufacturing a semiconductor device having a buried gate, which is an argon (Ar) gas.
  4. The method of claim 1, wherein the impurity implantation step
    A method of manufacturing a semiconductor device having a buried gate, characterized in that for performing a gradient ion implantation.
  5. The method of claim 1, wherein the extending of the bottom of the storage node contact hole comprises:
    A method of manufacturing a semiconductor device with a buried gate, characterized in that a non-plasma dry cleaning method using NH 3 , HF, and Ar gas is used.
  6. The method of claim 1, wherein the interlayer insulating film
    A method of manufacturing a semiconductor device having a buried gate, characterized in that it comprises Low Pressure Tetra Ethyl Ortho Silicate (LPTEOS).
KR1020100038522A 2010-04-26 2010-04-26 Forming method of semiconductor having buried gate KR20110119047A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165859B2 (en) 2013-04-08 2015-10-20 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US9202774B2 (en) 2013-07-31 2015-12-01 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US9419000B2 (en) 2013-11-13 2016-08-16 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices
US9508726B2 (en) 2014-08-18 2016-11-29 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10037996B2 (en) 2016-07-12 2018-07-31 Samsung Electronics Co., Ltd. Semiconductor device includes a substrate having conductive contact structures thereon

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165859B2 (en) 2013-04-08 2015-10-20 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US9202774B2 (en) 2013-07-31 2015-12-01 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
US9419000B2 (en) 2013-11-13 2016-08-16 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices
US9953981B2 (en) 2013-11-13 2018-04-24 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices
US9508726B2 (en) 2014-08-18 2016-11-29 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10037996B2 (en) 2016-07-12 2018-07-31 Samsung Electronics Co., Ltd. Semiconductor device includes a substrate having conductive contact structures thereon

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