KR20170043683A - Method for manufaturing semiconductor device - Google Patents

Method for manufaturing semiconductor device Download PDF

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Publication number
KR20170043683A
KR20170043683A KR1020150142516A KR20150142516A KR20170043683A KR 20170043683 A KR20170043683 A KR 20170043683A KR 1020150142516 A KR1020150142516 A KR 1020150142516A KR 20150142516 A KR20150142516 A KR 20150142516A KR 20170043683 A KR20170043683 A KR 20170043683A
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South Korea
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layer
forming
trench
hard mask
silicon nitride
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KR1020150142516A
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Korean (ko)
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김진웅
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에스케이하이닉스 주식회사
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Priority to KR1020150142516A priority Critical patent/KR20170043683A/en
Publication of KR20170043683A publication Critical patent/KR20170043683A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3211—Nitridation of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention provides a method of manufacturing a semiconductor device capable of preventing critical dimension and bending of an active region, and a method of manufacturing a semiconductor device according to the present invention includes: forming a device isolation layer defining an active region on a semiconductor substrate; Forming a hard mask having a line-shaped opening that simultaneously traverses a portion of the active region and a portion of the device isolation layer; Etching the active region and the device isolation layer through the opening of the hard mask to form a trench; Forming a silicon nitride layer overlying the top surface and sidewalls of the hard mask and the sides and bottom surface of the trench; Oxidizing the silicon nitride layer to form a gate oxide layer covering the sides and the bottom surface of the trench and a protective layer covering the hard mask; Forming a gate layer on the gate oxide layer and the passivation layer to fill the trench; And recessing the gate layer to form a gate electrode in the trench having a lower level than the top surface of the semiconductor substrate.

Description

[0001] METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [0002]

The present invention relates to a semiconductor device manufacturing method, and more particularly, to a semiconductor device manufacturing method including a gate insulating layer.

A semiconductor device including integrated circuits can be applied to various electronic devices. The semiconductor device may include a plurality of transistors.

A gate dielectric layer of the transistor may be formed of an oxide layer formed by thermally oxidizing the active region. During thermal oxidation of the active region, silicon loss may result. Silicon loss can result in critical dimension reduction and bending of the active area. As a result, the performance of the transistor may be deteriorated.

Embodiments of the present invention provide a semiconductor device manufacturing method capable of preventing the threshold number of active regions and bending.

Embodiments of the present invention provide a method of manufacturing a semiconductor device capable of improving the performance of a transistor.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a device isolation layer for defining an active region on a semiconductor substrate; Forming a hard mask having a line-shaped opening that simultaneously traverses a portion of the active region and a portion of the device isolation layer; Etching the active region and the device isolation layer through the opening of the hard mask to form a trench; Forming a silicon nitride layer overlying the top surface and sidewalls of the hard mask and the sides and bottom surface of the trench; Oxidizing the silicon nitride layer to form a gate oxide layer covering the sides and the bottom surface of the trench and a protective layer covering the hard mask; Forming a gate layer on the gate oxide layer and the passivation layer to fill the trench; And recessing the gate layer to form a gate electrode in the trench having a lower level than the top surface of the semiconductor substrate.

A method of fabricating a semiconductor device according to an embodiment of the present invention includes: etching a semiconductor substrate to form a first trench defining an active region; Forming a first silicon nitride layer overlying the first trench; Oxidizing the first silicon nitride layer to form a silicon oxide liner covering the first trench; Forming a device isolation layer on the silicon oxide liner to fill the first trench; Forming a hard mask having a line-shaped opening that simultaneously traverses a portion of the active region and a portion of the device isolation layer; Etching the active region and the device isolation layer through the opening of the hard mask to form a second trench; Forming a second silicon nitride layer overlying the top surface and sidewalls of the hard mask and sides and bottom surface of the trench; And oxidizing the second silicon nitride layer to form a gate oxide layer covering the sides and the bottom surface of the second trench and a protective layer covering the top surface and sidewalls of the hard mask.

According to the present technology, since the active region is not oxidized and the sacrificial liner is oxidized, the silicon loss of the active region can be suppressed. This makes it possible to secure the threshold value of the active region.

Further, according to the present technology, since the atomic layer deposition of the sacrificial liner and the oxidation process of the sacrificial liner proceed in situ, a cleaning process for removing the fumes is not required. Therefore, the process is simplified and the cost is reduced.

Further, according to the present technology, bending of the active region can be prevented since silicon is not oxidized and the nitride layer is oxidized.

Further, according to the present technology, it is possible to suppress the profile defect of the hard mask, thereby preventing the contact sick opening phenomenon.

1A to 1I illustrate an example of a method of manufacturing a semiconductor device according to the first embodiment.
1J is a view for explaining a semiconductor device according to a modification of the first embodiment.
2A is a plan view illustrating an active region and an element isolation layer according to the first embodiment.
2B is a plan view for explaining a second trench according to the first embodiment.
2C is a plan view for explaining the sacrificial liner according to the first embodiment.
2D is a plan view for explaining the gate insulating layer according to the first embodiment.
3A to 3E illustrate an example of a method of manufacturing the semiconductor device according to the second embodiment.
4A to 4I illustrate a method of manufacturing a memory cell according to the present embodiments.
5 is a view showing a semiconductor device according to a comparative example.

The embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

1A to 1I illustrate an example of a method of manufacturing a semiconductor device according to the first embodiment. 2A is a plan view illustrating an active region and an element isolation layer according to the first embodiment. 1A to 1I illustrate a manufacturing method according to line A-A 'and line B-B' in FIG. 2A.

As shown in FIG. 1A, a device isolation layer 12 may be formed on a semiconductor substrate 11. A plurality of active regions 13 can be defined by the device isolation layer 12. [ The semiconductor substrate 11 may be a silicon-containing material, i.e., a silicon-based material. The semiconductor substrate 11 may be a silicon substrate or a silicon germanium substrate.

The device isolation layer 12 may be formed by, for example, an STI (Shallow Trench Isolation) process. In order to form the first trench 14, the semiconductor substrate 11 can be etched. The first trench 14 may be filled with an insulating layer. The insulating layer may be exposed to a planarization process such as CMP (Chemical Mechanical Polishing). The device isolation layer 12 can be formed by such a planarized insulating layer. The device isolation layer 12 may be a single material, and the single material may be an oxide base material. In some embodiments, the device isolation layer 12 may comprise a nitride base material or a combination of an oxide base material and a nitride base material. For example, the device isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the device isolation layer 12 may include SiO 2, SOD (Spin on Dielectric ), Si 3 N 4 or a combination thereof.

2A, a plurality of active regions 13 may be defined as an island-shaped or a bar-shaped by the device isolation layer 12. The plurality of active regions 13 may have a minor axis in the first direction X and a major axis in the second direction Y, respectively. The major axis may have a first width W1 and the minor axis may have a second width W2. The plurality of active regions 13 may be repeatedly formed in a state of being spaced apart from each other along the first direction (X direction) and the second direction (Y direction). The pair of active regions 13Y adjacent to each other along the second direction Y among the plurality of active regions 13 are arranged in a direction opposite to each other along the first direction X so as to overlap only a part along the second direction Y They can be shifted and aligned to be shifted from each other. The first direction X and the second direction Y may be perpendicular to each other. The plurality of active regions 13 can be inclined in an oblique direction with respect to the third direction X1 and the fourth direction Y1. The third direction X1 and the fourth direction Y1 may be perpendicular to each other. As will be described later, the gate electrode (or buried word line) may be formed to extend in the third direction X1, and the bit line may extend to extend in the fourth direction Y1. The spacing of neighboring active regions 13 along the first direction X may be greater than the spacing of neighboring active regions 13 along the second direction.

A hard mask 15 may be formed on the semiconductor substrate 11, as shown in FIG. The hard mask 15 may be formed to include a plurality of line-shaped openings 15A. The plurality of openings 15A may define an area in which the gate electrodes are disposed.

The hard mask 15 may be formed to expose a part of the active region 13 and a part of the device isolation layer 12. [ The hard mask 15 may be referred to as an etch mask. As will be described later, the hard mask 15 may serve as an interlayer insulating layer for the bit line contact plugs and the storage node contact plugs. The hard mask 15 may comprise silicon oxide. The hard mask 15 may be TEOS (Tetra-Ethyl-Ortho-Silicate) based silicon oxide. The hard mask 15 may be a line / space-shaped pattern. A part of the active region 13 can be exposed by the opening 15A of the hard mask 15. [

To form a plurality of second trenches 16, the portions exposed by the hard mask 15 may be etched. That is, to form the second trench 16, the exposed portion of the active region 13 and the exposed portion of the device isolation layer 12 may be etched. The bottom surface of the second trench 16 may be at a lower level than the upper surface of the active region 13. The second trenches 16 may be line-shaped. The second trenches 16 extend across the active region 13 and the device isolation layer 12. When a plurality of gate electrodes (or buried word lines) are formed in the plurality of second trenches 16, the effective channel length is increased, thereby reducing the short channel effect.

And the second trenches 16 may extend in the third direction X1. The second trench 16 may include a first portion 16A and a second portion 16B. The first portion 16A of the second trench 16 may be formed in the active region 13 and the second portion 16B of the second trench 16 may be formed in the device isolation layer 12 . The bottom and sidewalls of the first portion 16A of the second trench 16 may be the surface of the silicon base material. The bottom and sidewalls of the second portion 16B of the second trench 16 may be the surface of silicon oxide. In another embodiment, when the device isolation layer 12 comprises silicon nitride, the bottom and sidewalls of the second portion 16B of the second trench 16 may be the surface of silicon nitride.

By the second trench 16, the device isolation layer 12 may include an un-etched isolation layer 12A and an etched isolation layer 12B. The non-etched device isolation layer 12A may be covered by the hard mask 15. [

2B is a plan view for explaining the second trench.

Referring to FIGS. 1B and 2B, by the second trench 16, the active region 13 may include a first portion 13A, a second portion 13B and a third portion 13C. The second trench 16 may be located between the first portion 13A and the second portion 13B of the active region 13 and the second portion 13B and the third portion 13B of the active region 13 13C. ≪ / RTI > The first portion 13A of the active region 13 may be located at the center of the active region 13. [ The first portion 13A, the second portion 13B and the third portion 13C of the active region 13 are formed apart from each other by the second trench 16 along the second direction Y . The first part 13A, the second part 13B and the third part 13C of the active area 13 may have the same or different threshold values CD. The first portion 13A of the active region 13 has a first width W11 and the second portion 13B of the active region 13 has a second width W12 along the third direction X1. And the third portion 13C of the active region 13 may have a third width W13. The first portion 13A of the active region 13 has a first width W11 'and the second portion 13B of the active region 13 has a second width W12 , And the third portion 13C of the active region 13 may have a third width W13 '. A bit line may be connected to the first portion 13A of the active region 13 and a memory element may be connected to the second portion 13B and the third portion 13C of the active region 13, .

As shown in FIG. 1C, the etched isolation layer 12B may be recessed to form an active fin 13F. For example, the bottom surface of the second portion 16B of the second trench 16 may be deeper than the bottom surface of the first portion 16A. Therefore, the second trench 16 can include the recessing portion 16R by recessing the etched isolation layer 12B. The recessing portion 16R may be a portion where the bottom surface of the second portion 16B of the second trench 16 extends downward. Thus, the second portion 16B of the second trench can have a lower level of bottom surface than the first portion 16A. The recessing portion 16R and the active pin 13F may have the same height. The recessed device isolation layer 12F may remain under the recessing portion 16R. Subsequently, a gay electrode (or buried word line) may be filled in the second trench 16. In this way, a saddle fin type transistor can be formed. The active pin 13F can be used as the channel region of the saddle-pin type transistor. By forming the active pin 13F, the channel width of the saddle pin type transistor can be increased. The channel width of the saddle-pinned transistor can be increased relative to a conventional buried gate-type transistor. By forming the transistor to include the active pin 13F as the channel region, the electrical characteristics of the transistor can be improved. The active pin 13F may include a top surface F1, a first sidewall F2 and a second sidewall F3. The upper surface F1 of the active pin 13F may be the underside of the first portion 16A of the first trench 16. The active pin 13F may have an arbitrary width F11 along the third direction X1. The width F11 of the active pin 13F may be equal to the width W11 of the first portion 13A of the active region.

As described above, the active region 13 may include the first portion 16A of the second trench 16 and the active pin 13F. The isolation layer 12 may include a second portion 16B of the second trench 16 having a recessed portion 16R. The second portion 16B of the second trench 16 has a lower level lower surface than the bottom surface of the first portion 16A and the upper surface F1 of the active pin 13F by the recessing portion 16R .

As shown in Fig. 1D, a sacrificial liner 17 may be formed. The sacrificial liner 17 may be formed on the front surface of the semiconductor substrate 11 including the second trench 16. The sacrificial liner 17 may conformally be formed along the surface profile of the first portion 16A and the second portion 16B of the second trench 16. That is, the sacrificial liner 17 may cover the bottom and sidewalls of the second trench 16, the top surface F1 of the active pin 13F and the sidewalls F2 and F3. The sacrificial liner 17 may prevent sidewall oxidation of the active area 13 during subsequent oxidation processes. Therefore, the silicon loss at the side wall of the active region 13 can be suppressed. The sidewalls and top surface of the hard mask 15 can also be covered by the sacrificial liner 17.

2C is a plan view for illustrating the sacrificial liner.

Referring to FIGS. 1D and 2C, the sacrificial liner 17 may comprise a material that can be converted to an oxidizing material by a subsequent oxidation process. That is, the sacrificial liner 17 may comprise a material that can be oxidized during the subsequent oxidation process. The sacrificial liner 17 may comprise a nitride layer deposited by atomic layer deposition. This may be referred to as an " ALD-nitride layer ". The sacrificial liner 17 may comprise a Si 3 N 4 layer deposited by atomic layer deposition (ALD). This is referred to as an 'ALD-Si 3 N 4 layer'.

As a comparative example, the sacrificial liner 17 may comprise a nitride layer deposited by other deposition methods. For example, the sacrificial liner 17 according to the comparative example may be formed of a Si 3 N 4 layer (referred to as an LP-Si 3 N 4 layer) deposited by low pressure chemical vapor deposition (LPCVD). The LP-Si 3 N 4 layer can also suppress silicon loss during subsequent oxidation processes. However, fumes may occur during the deposition of LP-Si 3 N 4 . Therefore, a cleanning process must be performed to remove the fume after the deposition. In addition, since LP-Si 3 N 4 has poor step coverage as compared with ALD-Si 3 N 4 , oxidation uniformity may be lowered in the subsequent oxidation process. That is, it is disadvantageous in terms of oxidation uniformity compared with the case of oxidizing ALD-Si 3 N 4 . The step coverage is determined by the thickness of the sacrificial liner 17, that is, the thickness D1 at the top of the second trench 16, the thickness D2 at the side wall of the second trench 16, And the thickness D3 at the bottom surface of the substrate. Middle step coverage may refer to the ratio of the thickness D2 at the sidewall of the second trench 16 to the thickness D1 at the top of the second trench 16. [ The bottom step coverage may refer to the ratio of the thickness D3 at the bottom of the second trench 16 to the thickness at the top of the second trench 16. [ For example, if the thickness D1 at the top of the second trench 16 is 100 ANGSTROM and the thickness D3 at the bottom of the second trench 16 is 90 ANGSTROM, then the bottom step coverage may be 90% have. More than 90% means good step coverage. On the other hand, when the thickness D1 at the top of the second trench 16 is 100 Å and the thickness D3 at the bottom of the second trench 16 is 70 Å, the bottom step coverage can be 70%. 70% can mean poor step coverage. As described above, when the step coverage is poor, the oxidation uniformity may also deteriorate.

As described above, the sacrificial liner 17 according to the present embodiment is formed by the atomic layer deposition method, and hence the step coverage can be excellent. The sacrificial liner 17 has a thickness D1 at the top of the second trench 16, a thickness D2 at the sidewalls of the second trench 16, a thickness D3 at the bottom of the second trench 16 ) May be the same.

The sacrificial liner 17 may be exposed to the oxidation process 18, as shown in FIG. By oxidizing the sacrificial liner 17, the gate insulating layer 19 can be formed. The deposition process of the oxidation process 18 of the sacrificial liner 17 and the sacrificial liner 17 may proceed in-situ. During the oxidation process 18 of the sacrificial liner 17, oxidation of the sidewalls of the active region 13 can be suppressed. That is, oxidation can be suppressed in the bottom surface and sidewalls of the first portion 16A of the second trench 16. In addition, oxidation can be suppressed in the upper surface and sidewalls of the active pin 13F. Thus, silicon loss can be prevented.

The first portion 13A, the second portion 13B and the third portion 13C of the active region 13 are each subjected to the oxidation process 18 because the sacrificial liner 17 is oxidized by the oxidation process 18. [ The previous threshold value can be maintained. The first portion 13A, the second portion 13B and the third portion 13C of the active region 13 do not suffer sidewall losses since no silicon loss occurs in the sidewalls of the second trenches 16 .

2D is a plan view for explaining the gate insulating layer.

The first portion 13A of the active region 13 has a first width W11 and a second width W11 after the oxidation process 18 has been performed to form the gate insulating layer 19, The second portion 13B of the active region 13 can maintain the second width W12 and W12 'and the third portion 13C of the active region 13 can maintain the third width 13' (W13, W13 '). As a result, the first portion 13A, the second portion 13B, and the third portion 13C of the active region 13 can maintain the initial threshold value as it is.

Further, since the sacrificial liner 17 is oxidized by the oxidation step 18, the active pin 13F can maintain the width F11 before the oxidation step 18. [

The gate insulating layer 19 may be of the same thickness or thicker than the sacrificial liner 17. However, the thickness of the second trench 16 can be controlled to 60 Å or less in order to prevent a gap fill defect in the gate electrode.

By the oxidation process 18, the sacrificial liner 17 can be converted to an oxidizing material. Thus, the gate insulating layer 19 may be silicon oxide. The gate insulating layer 19 may be a fully oxidized SiO 2 layer of ALD-Si 3 N 4 . That is, the gate insulating layer 19 may be SiO 2 that is nitrogen-free.

The gate insulating layer 19 may include a first portion 19A covering the sidewalls of the second trench 16 and the active pin 13F and a second portion 19B covering the hard mask 15. [ have. The first portion 19A and the second portion 19B of the gate insulating layer 19 may be continuous. The first portion 19A of the gate insulating layer 19 may be an oxidized portion of the sacrificial liner 17 directly contacting the sidewalls of the second trench 16 and the active pin 13F. The first portion 19A of the gate insulating layer 19 can cover the top surface and the side wall of the active pin 13F since the sacrificial liner 17 covers the top surface and the side wall of the active pin 13F . Therefore, it is possible to prevent the silicon loss at the sidewalls of the active pin 13F, and thus to maintain the height and width of the active pin 13F before the oxidation process 18.

The oxidation process 18 for forming the gate insulating layer 19 can be performed using a radical oxidation process capable of effectively converting the sacrificial liner 17 into an oxidized material while suppressing the silicon loss.

When the sacrificial liner 17 comprises a-Si 3 N 4 layer ALD, a N 4 layer ALD-Si 3 by a radical oxidation process may be converted into a SiO 2 layer. By applying the radical oxidation process, nitrogen can be contained in the SiO 2 layer (nitrogen-free) and the nitrogen content can be minimized. On the other hand, the high nitrogen content in the SiO 2 may generate a defect at the interface of the second trench 16 and the SiO 2.

SiO 2 , which is oxidized by the radical oxidation process of the ALD-Si 3 N 4 layer, is a hard material. Accordingly, the second portion 19B of the gate insulating layer 19 can function as a passivation layer covering the hard mask 15. [ Hereinafter, the second portion 19B of the gate insulating layer 19 will be referred to as a "protective layer 19B". The hard mask 15 exposed to the radical oxidation process can be densified. That is, the hard mask 15 can be hardened. By the radical oxidation process, the hard mask 15 can be modified with cured silicon oxide. By hardening the hard mask 15 while forming the protective layer 19B in this way, loss of the hard mask 15 does not occur during the recessing process of the subsequent gate layer.

As shown in Fig. 1F, a gate layer 20A may be formed on the gate insulating layer 19 and the protective layer 19B. The gate layer 20A may be formed to fill the second trench 16 on the gate insulating layer 19. [ The gate layer 20A may be formed on the entire surface of the semiconductor substrate 11 including the second trench 16. In order to lower the resistance of the gate electrode, the gate layer 20A may comprise a low resistance metal. For example, the gate layer 20A may comprise tungsten (W), titanium nitride (TiN), or a combination thereof.

As shown in FIG. 1G, a gate electrode 20 may be formed. In order to form the gate electrode 20, the gate layer 20A may be recessed. The upper surface 20G of the gate electrode 20 may be at a lower level than the upper surface of the semiconductor substrate 11. [ The recessing of the gate layer 20A can be performed by a planarization process and an etch-back process. The gate electrode 20 may be referred to as a buried word line. The gate electrode 20 may comprise a high-k dielectric material. Thus, the channel dose can be reduced.

During the recessing of the gate layer 20A as described above, the hard mask 15 can be protected by the protective layer 19B. Thus, loss of the hard mask 15 (refer to 15R) can be prevented. As a result, the hard mask 15 can maintain the width and thickness before the recessing of the gate layer 20A.

The gate capping layer 21 may be formed on the gate electrode 20, as shown in FIG. To form the gate capping layer 21, the gate trench 16 may be filled with a capping layer (not shown) on the gate electrode 20. Subsequently, the capping layer may be planarized by a CMP or etch back process. The planarized capping layer may be a gate capping layer 21. The planarizing process of the capping layer is stopped at the protective layer 19B. Thus, the width and thickness of the hard mask 15 are not reduced.

According to the first embodiment described above, the gate insulating layer 19 can be formed by the sacrificial liner 17 deposition and oxidation process 18. Thereby, the number of thresholds of the active region 13 can be reduced and bending can be prevented.

The first doped region 22 and the second doped region 23 may be formed in the active region 13 as shown in FIG. The first doped region 22 and the second doped region 23 may be formed by a doping process such as implantation. A first doped region 22 may be formed in the first portion 13A of the active region. The second doped region 23 may be formed in the second portion 13B and the third portion 13C of the active region 13, respectively.

1J is a view for explaining a semiconductor device according to a modification of the first embodiment.

Referring to FIG. 1J, a barrier 24 and a low-ohmic layer 25 may be further formed on the gate electrode 20. FIG. The barrier layer 24 may comprise titanium nitride. The functional layer 25 may include an N-type work function material. The buffer layer 25 may comprise an N-doped polysilicon doped with an N-type dopant. The buffer layer 25 may overlap the first doped region 22 and the second doped region 23. As a result, the GIDL (Gate Induced Drain Leakage) can be improved by the low temperature function layer 25.

3A to 3E illustrate an example of a method of manufacturing the semiconductor device according to the second embodiment. In Figs. 3A to 3E, the same reference numerals as in Figs. 1A to 1I denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

As shown in FIG. 3A, a first trench 14 may be formed in the semiconductor substrate 11. In FIG. A plurality of active regions 13 can be defined by the first trenches 14. [ In order to form the first trench 14, the semiconductor substrate 11 can be etched using the element isolation mask 31. [

In the above-described etching process for forming the first trench 14, etching damage may occur on the surface of the first trench 14. [ In order to heal etch damage, a sidewall oxidation process is generally performed by thermall oxidation. However, the second embodiment applies a sacrificial liner deposition and oxidation process without applying thermal oxidation.

3B, a sacrificial liner 32 may be formed. The sacrificial liner 32 may be formed on the front surface of the semiconductor substrate 11 including the first trench 14. The sacrificial liner 32 may be conformally formed along the surface profile of the first trench 14. That is, the sacrificial liner 32 may cover the bottom and sidewalls of the first trench 14. The sacrificial liner 32 can prevent oxidation of the active area 13 during subsequent oxidation processes. Therefore, the silicon loss in the active region 13 can be suppressed. The element isolation mask 31 can also be covered by the sacrificial liner 32. [

The sacrificial liner 32 may be the same material as the sacrificial liner 17 according to the first embodiment. The first sacrificial liner 32 may comprise a material that can be converted to an oxidizing material by a subsequent oxidation process. That is, the sacrificial liner 32 may comprise a material that may be oxidized during a subsequent oxidation process. The sacrificial liner 32 may comprise an ALD-nitride layer. Sacrificial liner 32 may include a-Si 3 N 4 layer ALD. ALD-Si 3 N 4 has better step coverage than LP-Si 3 N 4 . The sacrificial liner 32 may be formed to have the same thickness at the top of the first trench 14, the side wall of the first trench 14, and the bottom of the first trench 14. [

The sacrificial liner 32 may be exposed to the oxidation process 33, as shown in Fig. 3C. By oxidizing the sacrificial liner 32, an oxide liner 34 can be formed. The deposition process of the oxidation process 33 of the sacrificial liner 32 and the sacrificial liner 32 can proceed in situ. During the oxidation process 33 of the sacrificial liner 32, oxidation of the sidewalls of the active region 13 can be suppressed. Thus, silicon loss can be prevented. Since the sacrificial liner 32 is oxidized by the oxidation process 33, the active region 13 can maintain the critical number before the oxidation process 33. [ The oxide liner 34 may be as thick as the sacrificial liner 32.

By the oxidation step 33, the sacrificial liner 32 can be converted to an oxidizing material. The oxidation process 33 can be performed using a radical oxidation process that can effectively convert the sacrificial liner 32 into an oxidizing material while suppressing silicon loss.

When the sacrificial liner 32 comprises a-Si 3 N 4 layer ALD, a N 4 layer ALD-Si 3 by a radical oxidation process may be converted into a SiO 2 layer. By applying the radical oxidation process, nitrogen may be included in the SiO 2 layer, or the nitrogen content may be minimized. On the other hand, SiO 2 May cause a defect in the interface between the first trench 14 and the SiO 2 .

As shown in Fig. 3D, a device isolation layer 12 may be formed. The device isolation layer 12 may comprise an insulating material filling the first trench 14. The device isolation layer 12 may be made of a single material, and the single material may be an oxide. In another embodiment, the device isolation layer 12 may comprise silicon nitride or a combination of silicon oxide and silicon nitride. In order to form the element isolation layer 12, after the element isolation trench is filled with an insulating material, a planarization process can be performed. Subsequently, it may be recessed to be flush with the top surface of the active region 13.

Next, the element isolation mask 31 can be removed. In addition, a portion of the oxide liner 34 covering the side walls and the upper surface of the element isolation mask 31 can be removed. Thus, the oxide liner 34 may remain only on the bottom and sidewalls of the first trench 14.

As described above, according to the second embodiment, the oxide liner 34 can be formed in the element isolation process. By forming the oxide liner 34, the etch damage generated in the etch process for forming the first trench 14 can be healed. Although not shown, in the first embodiment, the oxide liner can be formed by a known method, that is, a liner silicon layer deposition and oxidation process (i.e., radical oxidation).

In addition, the second embodiment can form the oxide liner 34 without sacrificing the silicon by the sacrificial liner 32 deposition and oxidation process 33. Therefore, it is possible to prevent the threshold number of active regions 13 from decreasing.

Subsequently, a second trench formation process, a sacrificial liner deposition process, an oxidation process, a gate electrode formation process, and a gate capping layer formation process may be performed similarly to the first embodiment.

In order to form the second trench 16 and the active pin 13F, a series of processes shown in Figs. 1B and 1C can be performed.

In order to form the gate insulating layer 19, the sacrificial liner 17 deposition and oxidation process 18 may be advanced in situ, as shown in Figs. 1D and 1E.

As shown in FIG. 3E, to form the gate electrode 20 and the gate capping layer 21, a gate layer 20A is deposited and recessed, capping layer deposition and A planarizing process can be performed.

Next, the first doped region 22 and the second doped region 23 can be formed.

According to the second embodiment described above, the oxide liner 34 can be formed without a silicon loss by the sacrificial liner 32 deposition and oxidation process 33. In addition, the gate insulating layer 19 can be formed by a sacrificial liner 17 deposition and oxidation process 18. Thereby, the number of thresholds of the active region 13 can be reduced and bending can be prevented. In addition, by forming the protective layer 19B by the oxidation step 18, it is possible to prevent the loss of the hard mask 15 from the subsequent process.

As a comparative example of the first embodiment and the second embodiment, a liner silicon layer deposition and oxidation process can be performed to form the gate insulating layer. However, when the liner silicon layer is oxidized, the channel characteristics may deteriorate because the surface roughness between the gate insulating layer and the second trench surface is poor.

4A to 4I illustrate a method of manufacturing a semiconductor device according to the present embodiments. 4A to 4I illustrate a method of manufacturing a memory cell. Hereinafter, for convenience of explanation, a manufacturing method according to the line A-A 'will be described.

As shown in FIG. 4A, a first contact hole 41 may be formed. The protective layer 19B and the hard mask 15 may be etched using a contact mask (not shown) to form the first contact hole 41. [ Hereinafter, the protective layer 19B and the hard mask 15 can function as an interlayer insulating layer. The first contact hole 41 may have a circular shape or an elliptical shape when viewed in a plan view. A part of the active region 13 is exposed by the first contact hole 41. The first contact hole 41 may have a diameter controlled to a certain line width. For example, the first doped region 22 is exposed by the first contact hole 41. The first contact hole 41 has a diameter larger than the width of the minor axis of the active region 13. Therefore, in the etching process for forming the first contact hole 41, the first doped region 22 and part of the device isolation layer 12 can be etched. That is, the first doped region 22 and the device isolation layer 12 under the first contact hole 41 can be recessed to a certain depth. Thus, the bottom of the first contact hole 41 can be expanded.

As shown in Fig. 4B, a spare plug 42A is formed. A method of forming the preliminary plug 42A will be described below. First, a first conductive layer (not shown) filling the first contact hole 41 is formed on the entire surface of the semiconductor substrate 11 including the first contact hole 41. Next, the first conductive layer may be etched so that the surface of the protective layer 19B is exposed. Thereby, a preliminary plug 42A filling the first contact hole 41 is formed. The surface of the preliminary plug 42A may be coplanar with the surface of the protective layer 19B, or may be a lower height. Subsequently, the preliminary plug 42A can be doped with an impurity by a doping process such as an implant. In this embodiment, the preliminary plug 42A may comprise polysilicon doped with a dopant.

Next, the second conductive layer 43A and the capping layer 44A may be laminated. The second conductive layer 43A and the capping layer 44A may be sequentially stacked on the preliminary plug 42A and the protective layer 19B. The second conductive layer 43A includes a metal-containing material. The second conductive layer 43A may comprise a metal, a metal nitride, a metal suicide, or a combination thereof. In this embodiment, the second conductive layer 43A may include tungsten (W). In another embodiment, the second conductive layer 43A may comprise a layer of titanium nitride and tungsten (TiN / W). At this time, the titanium nitride can serve as a barrier. The capping layer 44A may be formed of an insulating material having an etch selectivity to the second conductive layer 43A and the preliminary plug 42A. The capping layer 44A may comprise silicon oxide or silicon nitride. In this embodiment, the capping layer 44A is formed of silicon nitride.

As shown in FIG. 4C, a bit line structure BL and a bit line contact plug 42 are formed. The bit line structure BL and the bit line contact plug 42 may be formed by an etching process using a bit line mask. The capping layer 44A and the second conductive layer 43A are etched using a bit line mask (not shown) as an etching barrier. Accordingly, a bit line structure BL including the bit line 43 and the bit line capping layer 44 is formed. The bit line 43 may be formed by etching the second conductive layer 43A. The bit line capping layer 44 is formed by etching the capping layer 44A.

Subsequently, the preliminary plug 42A is etched with the same line width as that of the bit line 43. A bit line contact plug 42 is thus formed. A bit line contact plug 42 is formed on the first doped region 22. The bit line contact plug 42 interconnects the first doped region 22 and the bit line 43. A bit line contact plug 44 is formed in the first contact hole 41. The line width of the bit line contact plug 42 is smaller than the diameter of the first contact hole 41. Thus, a gap can be formed around the bit line contact plug 42. [

As shown in Figs. 4D to 4F, a spacer element 45A may be formed. The spacer element 45A may be located on the sidewalls of the bit line contact plug 42 and the bit line structure BL. The spacer element 45A may be composed of a plurality of spacers. A portion of the spacer element 45A may fill the gap around the bit line contact plug 42.

Next, the plug separation layer 48 and the second contact hole 49 may be formed. The plug isolation 48 is gapped between the bit line structures BL. The plug separation layer 48 includes silicon nitride. A damascene process may be applied to form the second contact hole 49. For example, after filling the sacrificial layer 46A between the bit line structures BL, a part of the sacrificial layer 46A is etched to form a plug separating portion 47. [ Next, the plug separating portion 48 is filled with the plug separating portion 47. Thereafter, the second contact hole 49 can be formed by removing the remaining sacrificial layer 46. The plug separation layer 48 may be formed by forming silicon nitride and then planarizing. A dip-out process may be applied to remove the sacrificial layer 46. The second contact hole 49 may have a rectangular shape when viewed in a plan view.

As shown in FIG. 4G, the etching process is performed so that the second doped region 23 is exposed. This is called a widening process of the second contact hole 49. For example, the spacer element 45A in the second contact hole 49 may be etched to form the spacer 45 on the sidewall of the bit line structure BL. Subsequently, the protective layer 19B and the hard mask 15 may be etched by self-aligning the spacer 45. [ The bottom portion of the second contact hole 49 is expanded by the exposing process so that the second doped region 23 is exposed. A part of the second doped region 23 and the element isolation layer 12 can be recessed to a certain depth subsequently. The bottom portion of the second contact hole 49 may have a round profile (see R) by etching selectivity difference. Such a round profile R can increase the contact area of the subsequent storage node contact plugs.

The extension process of the second contact hole 53 can proceed not only in the depth direction but also in the horizontal direction. For this purpose, an isotropic etching process can be performed. The protective layer 19B and the hard mask 15 may be isotropically etched by an isotropic etching process.

In this embodiment, since the loss of the hard mask 15 is not generated during the formation of the gate electrode 20, an interval (refer to ' S ') can be sufficiently secured. As a comparative example, when loss of the hard mask 15 is generated, a bridge may be generated between neighboring second contact holes 49 by the expansion process.

As shown in Fig. 4H, a silicon plug 50 may be formed to partially fill the second contact hole 49. [0050] As shown in Fig. In order to form the silicon plug 50, a polysilicon layer may be formed to fill the second contact hole 49. Next, the polysilicon layer may be recessed to a lower height than the top surface of the bit line structure BL. Thus, the silicon plug 50 can be formed in the second contact hole 49. The silicon plug 50 may be referred to as a " polysilicon plug ". The silicon plug may be doped with a dopant.

Next, the metal silicide 51 may be formed by a silicide-metal layer deposition and a thermal process. A metal silicide 51 may be formed on the silicon plug 50. After the thermal process, the unreacted silicide-metal layer can be removed.

The metal silicide 51 may include cobalt silicide, but is not limited to cobalt silicide. For example, another metal (for example, titanium, nickel, or the like) capable of reacting with silicon to form a silicide may be used to form a metal silicide.

The second contact hole 49 can be filled with the conductive layer. The conductive layer may be a material that is lower in resistance than the silicon plug 50. For example, the conductive layer may be a metallic material. After the conductive layer is filled, a CMP process can be performed. Thus, the metal plug 52 can be formed in the second contact hole 49. [

According to the above description, a storage node contact plug can be formed. The storage node contact plug may include a silicon plug 50, a metal silicon side 51, and a metal plug 52.

As shown in FIG. 4I, a memory element 53 may be formed on the metal plug 52. The memory element 53 may comprise a capacitor.

5 is a view showing a semiconductor device according to a comparative example. The comparative example is a case in which thermal oxidation or radical oxidation is directly applied without forming a sacrificial liner to form a gate insulating layer. Therefore, in the comparative example, the hard mask 15 may be lost in the etch-back process for forming the gate electrode 20. [

5, it is difficult to maintain a sufficient gap S1 between the neighboring second contact holes 49 during the extension process of the second contact hole 49 due to the loss of the hard mask 15 . The interval S1 is narrower than the interval S1 in Fig. 4G. Thus, bridges between adjacent second contact holes 49 can be generated.

The semiconductor device according to the above-described embodiments may be applied to a dynamic random access memory (DRAM), and the present invention is not limited thereto. For example, a static random access memory (SRAM), a flash memory, a ferroelectric random access memory (FeRAM) (Magnetic Random Access Memory), and a PRAM (Phase Change Random Access Memory).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

11: semiconductor substrate 12: device isolation layer
13: active region 13: first trench
15: hard mask 16: second trench
17: sacrificial liner 19: gate insulating layer

Claims (16)

Forming an element isolation layer for defining an active region on a semiconductor substrate;
Forming a hard mask having a line-shaped opening that simultaneously traverses a portion of the active region and a portion of the device isolation layer;
Etching the active region and the device isolation layer through the opening of the hard mask to form a trench;
Forming a silicon nitride layer overlying the top surface and sidewalls of the hard mask and the sides and bottom surface of the trench;
Oxidizing the silicon nitride layer to form a gate oxide layer covering the sides and the bottom surface of the trench and a protective layer covering the hard mask;
Forming a gate layer on the gate oxide layer and the passivation layer to fill the trench; And
Recessing the gate layer to form a gate electrode in the trench having a lower level than the top surface of the semiconductor substrate,
≪ / RTI >
The method according to claim 1,
Wherein the step of forming the silicon nitride layer and the step of oxidizing the silicon nitride layer proceed in situ.
The method according to claim 1,
Wherein the step of forming the silicon nitride layer is performed by atomic layer deposition.
The method according to claim 1,
Wherein forming the gate oxide layer comprises:
A method of manufacturing a semiconductor device using a radical oxidation process.
The method according to claim 1,
Wherein forming the silicon nitride layer comprises:
The thickness formed on the upper surface and the sidewalls of the hard mask, and the thickness formed on the side surfaces and the bottom surface of the trench are the same.
The method according to claim 1,
Wherein the hard mask comprises TEOS.
Etching the semiconductor substrate to form a first trench defining an active region;
Forming a first silicon nitride layer overlying the first trench;
Oxidizing the first silicon nitride layer to form a silicon oxide liner covering the first trench;
Forming a device isolation layer on the silicon oxide liner to fill the first trench;
Forming a hard mask having a line-shaped opening that simultaneously traverses a portion of the active region and a portion of the device isolation layer;
Etching the active region and the device isolation layer through the opening of the hard mask to form a second trench;
Forming a second silicon nitride layer overlying the top surface and sidewalls of the hard mask and sides and bottom surface of the trench; And
Oxidizing the second silicon nitride layer to form a gate oxide layer covering the sides and the bottom surface of the second trench and a protective layer covering the top surface and sidewalls of the hard mask
≪ / RTI > 8. The method of claim 7,
Wherein the step of forming the first silicon nitride layer and the step of oxidizing the first silicon nitride layer proceed in situ.
8. The method of claim 7,
Wherein the step of forming the second silicon nitride layer and the step of oxidizing the second silicon nitride layer proceed in situ.
8. The method of claim 7,
Wherein the first silicon nitride layer and the second silicon nitride layer are formed by atomic layer deposition.
8. The method of claim 7,
Wherein forming the silicon oxide liner and gate oxide layer comprises:
And each of which is a radical oxidation process.
8. The method of claim 7,
After forming the second trench,
Further etching the device isolation layer so as to have a lower level than the bottom surface of the trench to form an active fin on the bottom surface of the second trench;
≪ / RTI >
8. The method of claim 7,
After the step of forming the gate oxide layer and the protective layer,
Forming a gate layer on the gate oxide layer and the passivation layer to fill the trench;
Recessing the gate layer to form a gate electrode having a lower level than an upper surface of the semiconductor substrate; And
Forming a gate capping layer on the gate electrode
≪ / RTI >
14. The method of claim 13,
After forming the gate capping layer,
Etching the hard mask and the passivation layer to form a first contact hole exposing a first portion of the active region;
Forming a preliminary plug in the first contact hole;
Forming a bit line on the pre-plug;
Etching the preliminary plug to form a bit line contact plug having the same line width as the bit line;
Forming a spacer element on a sidewall of the bit line contact plug and the bit line structure;
Etching the hard mask and the passivation layer to form a second contact hole exposing a second portion of the active region;
Expanding the second contact hole by isotropic etching; And
Forming a storage node contact plug in the extended second contact hole
≪ / RTI >
15. The method of claim 14,
Wherein forming the storage node contact plug comprises:
Forming a silicon plug partially filling the extended second contact hole;
Forming a metal silicide on the silicon plug; And
Forming a metal plug on the metal silicide
≪ / RTI >
8. The method of claim 7,
Wherein the hard mask comprises TEOS.
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CN109524399A (en) * 2017-09-18 2019-03-26 三星电子株式会社 Semiconductor storage unit and its manufacturing method
CN111063733A (en) * 2018-10-17 2020-04-24 长鑫存储技术有限公司 Preparation method and structure of grid oxide layer and preparation method of grid
KR20200067214A (en) * 2017-11-03 2020-06-11 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. Semiconductor device and manufacturing method thereof
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US11462546B2 (en) 2017-11-03 2022-10-04 Varian Semiconductor Equipment Associates, Inc. Dynamic random access device including two-dimensional array of fin structures
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