KR20170096250A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20170096250A KR20170096250A KR1020160017003A KR20160017003A KR20170096250A KR 20170096250 A KR20170096250 A KR 20170096250A KR 1020160017003 A KR1020160017003 A KR 1020160017003A KR 20160017003 A KR20160017003 A KR 20160017003A KR 20170096250 A KR20170096250 A KR 20170096250A
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- South Korea
- Prior art keywords
- layer
- trench
- forming
- liner
- isolation structure
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title abstract description 23
- 238000004519 manufacturing process Methods 0.000 title abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 84
- 239000000463 material Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 49
- 229910052710 silicon Inorganic materials 0.000 claims description 49
- 239000010703 silicon Substances 0.000 claims description 49
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 27
- 230000009969 flowable effect Effects 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims description 13
- 239000012530 fluid Substances 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 238000005452 bending Methods 0.000 abstract description 21
- 230000003647 oxidation Effects 0.000 description 37
- 238000007254 oxidation reaction Methods 0.000 description 37
- 238000003860 storage Methods 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000010079 rubber tapping Methods 0.000 description 2
- BIVNKSDKIFWKFA-UHFFFAOYSA-N N-propan-2-yl-N-silylpropan-2-amine Chemical compound CC(C)N([SiH3])C(C)C BIVNKSDKIFWKFA-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
Abstract
Description
The present invention relates to a semiconductor device, and more particularly, to a device isolation structure and a manufacturing method thereof.
As the semiconductor device is highly integrated, a device isolation structure having a small width is required. The device isolation structure can be formed by forming a trench in the substrate and filling the trench with an insulating material. An active region can be defined by a device isolation structure.
However, as the number of thresholds of the active region decreases, a lining phenomenon or a bending phenomenon occurs in the active region.
Embodiments of the present invention provide a device isolation structure capable of preventing a lining phenomenon and a bending phenomenon of an active region, a fabrication method thereof, and a semiconductor device fabrication method having the same.
A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: etching a substrate to form a first trench defining an active region; Forming a flowable material such that the first trench is filled by underfilling to a level lower than an upper surface of the substrate; Forming a gap fill layer filling the first trench on the fluid material; Planarizing the gap fill layer to form a device isolation structure including the fluid material and the gap fill layer; Etching the active region and the gap fill layer of the device isolation structure to form a second trench that traverses the active region and the device isolation structure; And forming a gate electrode in the second trench. In the forming of the second trench, the height of the second trench may be equal to or lower than the height of the gap fill layer. The flowable material may comprise a flowable silicon oxide. The gap fill layer may comprise silicon nitride.
A method for fabricating a semiconductor device according to an embodiment of the present invention includes: etching the substrate to form a first trench defining a first active region and a second trench defining a second active region; Forming a fluidic oxide such that the first and second trenches are filled by underfilling to a level lower than an upper surface of the substrate; Forming a capillary filling the first and second trenches on the fluid oxide; Forming a first device isolation structure and a second device isolation structure in the first trench and the second trench, the first device isolation structure and the second device isolation structure including the flowable oxide and the gap filler, respectively; Etching the gap fill layer of the first active region and the first device isolation structure to form a second trench that traverses the first active region and the first device isolation structure; And forming a first gate electrode in the second trench.
The technology underfills the trench using a flowable material prior to the gapfil process, thereby preventing bending of the active region during the gapfil process.
1 shows a semiconductor device according to a first embodiment.
2A to 2E illustrate an example of a method of manufacturing the semiconductor device according to the first embodiment.
3A to 3C show an example of a semiconductor device manufacturing method according to a modification of the first embodiment.
4A to 4F show a method of manufacturing a memory cell as an application example of the first embodiment.
Figure 5 is a top view illustrating an array of memory cells according to Figure 4f.
6 shows a semiconductor device according to the second embodiment.
7A to 7E illustrate an example of a method of manufacturing the semiconductor device according to the second embodiment.
8A to 8C show modifications of the second embodiment.
Fig. 9 shows a memory cell as an application example of the second embodiment.
The embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic views of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.
1 shows a semiconductor device according to a first embodiment.
Referring to FIG. 1, the
The
The device isolation structure 108 may be formed in the
The
The
As described above, the device isolation structure 108 may include the
2A to 2E illustrate an example of a method of manufacturing the semiconductor device according to the first embodiment.
As shown in FIG. 2A, a
The
As shown in FIG. 2B, a
The
As shown in FIG. 2C, a
The
A
As shown in FIG. 2D, the
Since the recessed
As shown in FIG. 2E, the planarization process can be performed until the upper surface of the
The
3A to 3C show an example of a semiconductor device manufacturing method according to a modification of the first embodiment. A modification of the first embodiment may be similar to the method shown in Figs. 2A to 2E.
First, as shown in FIG. 3A, a
The
Next, a
The
A
The
Since the
The
By
The
The lining phenomenon of the
The trench in which the
As shown in FIG. 3C, the gap fill process and the planarization process can be sequentially performed. Accordingly, the gap fill layer 17 ', the
The
4A to 4F show a method of manufacturing a memory cell as an application example of the first embodiment. 4A to 4F illustrate a method according to the line A-A 'in FIG.
First, as shown in Figs. 2A to 2E, a
Next, as shown in FIG. 4A, the
The opening of the
The portions exposed by the opening of the
The
As shown in FIG. 4B, a
An example for forming the
Another example for forming the
Another example for forming the
As described above, when the
A
As shown in FIG. 4D, a buried
As shown in FIG. 4E, a
Next,
As shown in FIG. 4F, a bit
A storage node contact plug 38 connected to the storage
Figure 5 is a top view illustrating an array of memory cells according to Figure 4f.
Referring to FIGS. 5 and 4F, the
A plurality of
The storage
6 shows a semiconductor device according to the second embodiment.
Referring to FIG. 6, the
The first
The first and second stress buffer layers 208 'and 208 "may be located below the first and second gap fill layers 209' and 209 ", respectively. The first stress buffer layer 208 'may partially fill the
The first
The first and second
7A to 7E illustrate an example of a method of manufacturing the semiconductor device according to the second embodiment.
As shown in Fig. 7A, a
The
As shown in FIG. 7B, a
The
As shown in FIG. 7C, a
The
As shown in Fig. 7D, the
Since the recessed
7E, a planarization process may be performed until the top surface of the
The first
The first
The second
8A to 8C show a manufacturing method according to a modification of the second embodiment.
The width of the
7D, since the width of the
Fig. 8C shows a second
Fig. 9 shows a memory cell as an application example of the second embodiment. The first region R1 may be a memory cell region, and the second region R2 may be a peripheral circuit region. A plan view of the memory cell will be described with reference to FIG.
First, as shown in FIGS. 7A to 7E, the first and
Next, the
Subsequently, a bit
Subsequently, a bit
A storage node contact plug 78 connected to the storage
The semiconductor device according to the above-described embodiments may be applied to a dynamic random access memory (DRAM), and the present invention is not limited thereto. For example, a static random access memory (SRAM), a flash memory, a ferroelectric random access memory (FeRAM) (Magnetic Random Access Memory), and a PRAM (Phase Change Random Access Memory).
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.
11: substrate 12: hard mask layer
13: trench 14: active area
15: liner layer 16: stress buffer layer
17: gap fill layer 18: element isolation structure
Claims (20)
Forming a flowable material such that the first trench is filled by underfilling to a level lower than an upper surface of the substrate;
Forming a gap fill layer filling the first trench on the fluid material;
Planarizing the gap fill layer to form a device isolation structure including the fluid material and the gap fill layer;
Etching the active region and the gap fill layer of the device isolation structure to form a second trench that traverses the active region and the device isolation structure; And
Forming a gate electrode in the second trench;
≪ / RTI >
In forming the second trench,
And the height of the second trench is equal to or lower than the height of the gap fill layer.
Wherein the flowable material comprises a flowable silicon oxide.
Wherein the gap fill layer comprises silicon nitride.
Before the step of forming the flowable material,
And forming a liner layer lining the first trench.
Wherein the liner layer comprises silicon oxide.
Wherein the liner layer comprises a silicon layer,
Further comprising performing a thermal process to convert the silicon layer to a silicon oxide layer after forming the flowable material.
Before the step of forming the gate electrode,
And forming a gate insulating layer on bottoms and sidewalls of the second trench.
Wherein forming the gate insulating layer comprises:
Forming a liner silicon layer on the bottom and sidewalls of the second trench;
Performing a thermal process to convert the liner silicon layer to a liner silicon oxide layer
≪ / RTI >
Forming a fluidic oxide such that the first and second trenches are filled by underfilling to a level lower than an upper surface of the substrate;
Forming a capillary filling the first and second trenches on the fluid oxide;
Forming a first device isolation structure and a second device isolation structure in the first trench and the second trench, the first device isolation structure and the second device isolation structure including the flowable oxide and the capillary, respectively;
Etching the gap fill layer of the first active region and the first device isolation structure to form a second trench that traverses the first active region and the first device isolation structure; And
Forming a first gate electrode in the second trench;
≪ / RTI >
In forming the second trench,
And the height of the second trench is equal to or lower than the height of the gap fill layer.
Wherein the flowable oxide comprises a flowable silicon oxide.
Wherein the gap fill nitride comprises silicon nitride.
Before the step of forming the fluid oxide,
And forming a liner layer lining the first trench and the second trench, respectively.
Wherein the liner layer comprises silicon oxide.
Wherein the liner layer comprises a silicon layer,
Further comprising performing a thermal process to convert the silicon layer to a silicon oxide layer after the step of forming the flowable oxide.
Before the step of forming the first gate electrode,
And forming a first gate insulating layer on the bottom and sidewalls of the second trench.
Wherein forming the first gate insulating layer comprises:
Forming a liner silicon layer on the bottom and sidewalls of the second trench;
Performing a thermal process to convert the liner silicon layer to a liner silicon oxide layer
≪ / RTI >
After forming the first gate electrode,
And forming a second gate electrode on the second active region.
Wherein the first device isolation structure is formed in a memory cell region and the second device isolation structure is formed in a peripheral circuit region for operation of the memory cell region.
Priority Applications (1)
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KR1020160017003A KR20170096250A (en) | 2016-02-15 | 2016-02-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020160017003A KR20170096250A (en) | 2016-02-15 | 2016-02-15 | Method for manufacturing semiconductor device |
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