KR20170096250A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20170096250A
KR20170096250A KR1020160017003A KR20160017003A KR20170096250A KR 20170096250 A KR20170096250 A KR 20170096250A KR 1020160017003 A KR1020160017003 A KR 1020160017003A KR 20160017003 A KR20160017003 A KR 20160017003A KR 20170096250 A KR20170096250 A KR 20170096250A
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South Korea
Prior art keywords
layer
trench
forming
liner
isolation structure
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KR1020160017003A
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Korean (ko)
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김진웅
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에스케이하이닉스 주식회사
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Priority to KR1020160017003A priority Critical patent/KR20170096250A/en
Publication of KR20170096250A publication Critical patent/KR20170096250A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)

Abstract

The present invention provides a device isolation structure capable of preventing a leaning phenomenon and a bending phenomenon of an active region, a fabrication method thereof, and a fabrication method of a semiconductor device having the same. According to the present invention, the fabrication method of a semiconductor device may comprise the steps of: etching a substrate so as to form a first trench defining an active region; forming a material having fluidity such that the first trench is filled by an underfill process to a level lower than an upper surface of the substrate; forming a gap fill layer filling the first trench on the material having fluidity; flattening the gap fill layer to form a device isolation structure including the material having fluidity and the gap fill layer; etching the active region and the gap fill layer of the device isolation structure to form a second trench which traverses the active region and the device isolation structure; and forming a gate electrode in the second trench.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a semiconductor device,

The present invention relates to a semiconductor device, and more particularly, to a device isolation structure and a manufacturing method thereof.

As the semiconductor device is highly integrated, a device isolation structure having a small width is required. The device isolation structure can be formed by forming a trench in the substrate and filling the trench with an insulating material. An active region can be defined by a device isolation structure.

However, as the number of thresholds of the active region decreases, a lining phenomenon or a bending phenomenon occurs in the active region.

Embodiments of the present invention provide a device isolation structure capable of preventing a lining phenomenon and a bending phenomenon of an active region, a fabrication method thereof, and a semiconductor device fabrication method having the same.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: etching a substrate to form a first trench defining an active region; Forming a flowable material such that the first trench is filled by underfilling to a level lower than an upper surface of the substrate; Forming a gap fill layer filling the first trench on the fluid material; Planarizing the gap fill layer to form a device isolation structure including the fluid material and the gap fill layer; Etching the active region and the gap fill layer of the device isolation structure to form a second trench that traverses the active region and the device isolation structure; And forming a gate electrode in the second trench. In the forming of the second trench, the height of the second trench may be equal to or lower than the height of the gap fill layer. The flowable material may comprise a flowable silicon oxide. The gap fill layer may comprise silicon nitride.

A method for fabricating a semiconductor device according to an embodiment of the present invention includes: etching the substrate to form a first trench defining a first active region and a second trench defining a second active region; Forming a fluidic oxide such that the first and second trenches are filled by underfilling to a level lower than an upper surface of the substrate; Forming a capillary filling the first and second trenches on the fluid oxide; Forming a first device isolation structure and a second device isolation structure in the first trench and the second trench, the first device isolation structure and the second device isolation structure including the flowable oxide and the gap filler, respectively; Etching the gap fill layer of the first active region and the first device isolation structure to form a second trench that traverses the first active region and the first device isolation structure; And forming a first gate electrode in the second trench.

The technology underfills the trench using a flowable material prior to the gapfil process, thereby preventing bending of the active region during the gapfil process.

1 shows a semiconductor device according to a first embodiment.
2A to 2E illustrate an example of a method of manufacturing the semiconductor device according to the first embodiment.
3A to 3C show an example of a semiconductor device manufacturing method according to a modification of the first embodiment.
4A to 4F show a method of manufacturing a memory cell as an application example of the first embodiment.
Figure 5 is a top view illustrating an array of memory cells according to Figure 4f.
6 shows a semiconductor device according to the second embodiment.
7A to 7E illustrate an example of a method of manufacturing the semiconductor device according to the second embodiment.
8A to 8C show modifications of the second embodiment.
Fig. 9 shows a memory cell as an application example of the second embodiment.

The embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic views of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

1 shows a semiconductor device according to a first embodiment.

Referring to FIG. 1, the semiconductor device 100 may include a substrate 101. A device isolation structure 108 may be formed on the substrate 101 to define a plurality of active regions 104.

The active region 104 may be defined as an island-shaped or a bar-shaped. A hardmask layer 102 may be formed on the active region 104.

The device isolation structure 108 may be formed in the trench 103. The trenches 103 may be formed by etching the substrate 101 using the hard mask layer 102. The device isolation structure 108 may include a liner layer 105, a stress buffer layer 106, and a gap fill layer 107. The bottom and sidewalls of the trench 103 may be lined with a liner layer 105 and the lined trench 103 may be completely filled with the stress buffer layer 106 and the gap fill layer 107. [ The liner layer 105 may comprise silicon oxide. As such, the device isolation structure 108 may be a single oxide liner structure.

The stress buffer layer 106 of the element isolation structure 108 may be located under the gap fill layer 107. [ The stress buffer layer 106 may partially fill the bottom and sidewalls of the trench 103 on the liner layer 105. The stress buffer layer 106 may comprise a flowable material. For example, the stress buffer layer 106 may comprise a flowable silicon oxide.

The gap fill layer 107 of the device isolation structure 108 may comprise silicon oxide, silicon nitride, or a combination thereof.

As described above, the device isolation structure 108 may include the stress buffer layer 106 to prevent bending and lining of the active region 104.

2A to 2E illustrate an example of a method of manufacturing the semiconductor device according to the first embodiment.

As shown in FIG. 2A, a trench 13 may be formed. At least one trench 13 may be formed in the substrate 11. The active region 14 can be defined by the trenches 13. To form the trenches 13, a hard mask layer 12 may be formed on the substrate 11. The hardmask layer 12 may include an opening (not numbered). The opening may define an area in which the trenches 13 are disposed. The substrate 11 may include a semiconductor substrate. The substrate 11 may be silicon containing material, i.e., a silicon-based material. The substrate 11 may be a silicon substrate, a silicon germanium substrate, or an SOI substrate. The hardmask layer 12 may comprise a material having an etch selectivity relative to the substrate 11. The hardmask layer 12 may comprise an oxide, a nitride, or a combination thereof. For example, the hardmask layer 12 may comprise silicon oxide such as TEOS.

The trench 13 may have a first height H1 and a first width W1.

As shown in FIG. 2B, a liner layer 15 may be formed. The liner layer 15 may be conformally formed on the substrate 11. The liner layer 15 may lining the bottom and sidewalls of the trench 13. In addition, the liner layer 15 may cover the sidewalls and top surface of the hardmask layer 12.

The liner layer 15 according to this embodiment can have excellent step coverage. The trench 13 in which the liner layer 15 is formed may be referred to as a " lined trench ". The liner layer may be formed by CVD. In some embodiments, the liner layer 15 may be formed of an oxygen-containing material, which may be referred to as a silicon oxide-containing liner. In another embodiment, the liner layer 15 may be formed of a silicon-containing material, which may be referred to as a silicon-containing liner. In yet another embodiment, the liner layer 15 may be formed of a silicon nitride-containing material, which may be referred to as a silicon nitride-containing liner.

As shown in FIG. 2C, a stress buffer layer 16 may be formed. For example, a stress buffer layer 16 may be formed on the liner layer 15. The stress buffer layer 16 may comprise a flowable material. The stress buffer layer 16 may comprise a flowable oxide. The stress buffer layer 16 may comprise a flowable silicon oxide-containing material such that the line-trench 13 may be partially filled with a flowable silicon oxide-containing material. That is, the line trench 13 can be filled by the underfill of the stress buffer layer 16 so as to be lower in height than the upper surface of the substrate 11. As a comparative example, filling the line trench 13 with an overfill of the stress buffer layer 16 may result in bending of the active region 14. [

The stress buffer layer 16 may have a bottom-up shape and fill the bottom of the trench 13. The upper surface of the stress buffer layer 16 may be at a lower level than the upper surface of the active region 14. [ The stress buffer layer 16 may not be formed on the upper sidewall of the trench 13 and on the hard mask layer 12 as the stress buffer layer 16 is formed of a flowable oxide. The stress buffer layer 16 may be non-conformal. Thus, the stress buffer layer 16 may not stress the sidewalls of the active region 14. As a result, the stress buffer layer 16 formed of a flowable oxide can suppress the bending of the active region 14. The stress buffer layer 16 may be formed of a silazane-base material. As a comparative example, if the stress buffer layer 16 is conformally formed on the bottom and sidewalls of the trench 13, it may be stressed to cause bending of the active region 14.

A recess portion 16R may be defined above the stress buffer layer 16. The recess portion 16R may be a gap fill space at the time of the next gap filling. The aspect ratio of the gap fill space where the gap fill layer 17 is to be formed by the stress buffer layer 16 can be reduced. That is, the aspect ratio of the trench 13 can be reduced by the stress buffer layer 16. As the stress buffer layer 16 is formed, the recess portion 16R may have a second height H2 and a second width W2. The second height H2 may be less than the first height H1 of the trench 13. The second height H2 may be less than or equal to one-half of the first height H1 of the trench 13. The second width W2 may be less than the first width W1 of the trench 13. The second width W2 of the recess portion 16R can be made smaller than the first width W1 of the trench 13 by the liner layer 15. [ As such, the recessed portion 16R can have a smaller aspect ratio than the trench 13. In general, in the tapping process, an aspect ratio smaller than a large aspect ratio is easier to capture. Therefore, the aspect ratio can be reduced during the subsequent gapfil process, and bending of the active region 14 can be suppressed.

As shown in FIG. 2D, the gap fill layer 17 can be formed by the gap fill process. The gap fill layer 17 may be formed on the stress buffer layer 16. The gap fill layer 17 may fill the trench 13 in which the stress buffer layer 16 and the liner layer 15 are formed. The gap fill layer 17 may comprise an oxide, a nitride, or a combination thereof. In this embodiment, the gap fill layer 17 may comprise a silicon nitride-containing material, so that the trench 13 may be filled with a silicon nitride-containing material. In another embodiment, the gap fill layer 17 may comprise a silicon oxide-containing material. When the silicon nitride-containing material is formed as the gap fill layer 17, for example, the refreshment of the DRAM can be improved.

Since the recessed portion 16R is filled with the gap fill layer 17, the aspect ratio of the gap fill process is reduced, and the bending of the active region 14 can be suppressed.

As shown in FIG. 2E, the planarization process can be performed until the upper surface of the hard mask layer 12 is exposed. For example, the gap fill layer 17 and the liner layer 15 can be removed from the top of the hard mask layer 12. Accordingly, the gap fill layer 17 ', the stress buffer layer 16, and the liner layer 15' may remain in the trench 13.

The device isolation structure 18 may be formed in the trench 13 by the above-described series of steps. The device isolation structure 18 may include a liner layer 15'formed on the bottom and sidewalls of the trench 13 and a gap fill layer 17'filling the trench 13 on the liner layer 15 ' . The element isolation structure 18 may further include a stress buffer layer 16 and the stress buffer 16 may be located below the gap fill layer 17 '. When the gap fill layer 17 'includes an oxide, the device isolation structure 18 can be a structure completely filled with an oxide-containing material. When the gap fill layer 17 'comprises nitride, the device isolation structure 18 may be completely filled with an oxide-containing material and a nitride-containing material.

3A to 3C show an example of a semiconductor device manufacturing method according to a modification of the first embodiment. A modification of the first embodiment may be similar to the method shown in Figs. 2A to 2E.

First, as shown in FIG. 3A, a trench 13 may be formed in the substrate 11. A plurality of active regions 14 may be defined by the trenches 13. The trenches 13 may be formed by etching the substrate 11 using the hard mask layer 12. A liner silicon layer 19 may be formed on the bottom and sidewalls of the trench 13. The liner silicon layer 19 may be conformally formed on the substrate 11 on which the trenches 13 are formed. The liner silicon layer 19 may cover the bottom and sidewalls of the trench 13. In addition, the liner silicon layer 19 may cover the sidewalls and top surface of the hardmask layer 12. The liner silicon layer 19 can prevent sidewall oxidation of the active region 14 during subsequent oxidation processes. Therefore, the silicon loss at the side wall of the active region 14 can be suppressed. The liner silicon layer 19 may be converted into an oxidizing material by a subsequent oxidation process. That is, the liner silicon layer 19 is a material that can be oxidized during the subsequent oxidation process. The liner silicon layer 19 may be formed of an amorphous silicon layer. The liner silicon layer 19 may be deposited by low pressure chemical vapor deposition (LPCVD). In order to improve roughness, a seed layer (not shown) may first be deposited and then a liner silicon layer 19 may be deposited. The seed layer may be deposited using a diisopropylamino silane (DIPAS) gas. That is, the seed layer may be a silicon layer. The liner silicon layer 19 may be deposited using a disilane (Si 2 H 6 ) gas. On the other hand, when the liner silicon layer 19 is directly deposited without the seed layer, the roughness is poor and the uniformity of the subsequent oxidation process may deteriorate.

The liner silicon layer 19 according to the present embodiment can have excellent step coverage. The liner silicon layer 19 may have the same thickness at the top of the trench 13, at the sidewalls of the trench 13, and at the bottom of the trench 13.

Next, a stress buffer layer 16 may be formed. For example, a stress buffer layer 16 may be formed on the liner silicon layer 19. The stress buffer layer 16 may comprise a flowable material. The stress buffer layer 16 may comprise a flowable oxide. The stress buffer layer 16 may comprise a flowable silicon oxide-containing material such that the line-trench 13 may be partially filled with a flowable silicon oxide-containing material. That is, the line trench 13 can be filled by underfilling of the stress buffer layer 16 to be lower than the upper surface of the substrate. As a comparative example, filling the line trench 13 with an overfill of the stress buffer layer 16 may result in bending of the active region 14. [

The stress buffer layer 16 may have a bottom-up shape and fill the bottom of the trench 13. The upper surface of the stress buffer layer 16 may be at a lower level than the upper surface of the active region 14. [ The stress buffer layer 16 may not be formed on the upper sidewall of the trench 13 and on the hard mask layer 12 as the stress buffer layer 16 is formed of a flowable oxide. The stress buffer layer 16 may be non-conformal. Thus, the stress buffer layer 16 may not stress the sidewalls of the active region 14. As a result, the stress buffer layer 16 formed of a flowable oxide can suppress the bending of the active region 14. The stress buffer layer 16 may be formed of a silazane-base material. As a comparative example, if the stress buffer layer 16 is conformally formed on the bottom and sidewalls of the trench 13, it may be stressed to cause bending of the active region 14.

A recess portion 16R may be defined above the stress buffer layer 16. The recess portion 16R may be a gap fill space at the time of the next gap filling. The aspect ratio of the gap fill space where the gap fill layer 17 is to be formed by the stress buffer layer 16 can be reduced. That is, the aspect ratio of the trench 13 can be reduced by the stress buffer layer 16. As the stress buffer layer 16 is formed, the recess portion 16R may have a second height H2 and a second width W2. The second height H2 may be less than the first height H1 of the trench 13. The second height H2 may be less than or equal to one-half of the first height H1 of the trench 13. The second width W2 may be less than the first width W1 of the trench 13. The second width W2 of the recess portion 16R can be made smaller than the first width W1 of the trench 13 by the liner silicon layer 19. [ As such, the recessed portion 16R can have a smaller aspect ratio than the trench 13. In general, in the tapping process, an aspect ratio smaller than a large aspect ratio is easier to capture. Therefore, the aspect ratio can be reduced during the subsequent gapfil process, and bending of the active region 14 can be suppressed.

The liner silicon layer 19 can be converted into the oxide liner layer 21, as shown in Fig. 3B. Converting may include an oxidation process 20. The liner silicon layer 19 may be exposed to the oxidation process 20. The etching damage generated in the trench 13 formation process by the oxidation process 20 can be cured. The liner silicon layer 19 can be oxidized by the oxidation step 20. [ Thus, an oxide liner layer 21 can be formed. During the oxidation process 20 of the liner silicon layer 19, sidewall oxidation of the active region 14 can be suppressed. That is, oxidation can be suppressed in the sidewalls of the trench 13. Thus, silicon loss can be prevented.

Since the liner silicon layer 19 is oxidized by the oxidation process 20, the active region 14 can maintain the critical number before the oxidation process 20 as it is. No loss of silicon occurs in the sidewalls of the trenches 13, so that the sidewall loss of the active region 14 does not occur. The oxide liner layer 21 may be formed to be thinner than the oxide liner layer formed by performing a direct oxidation process in a state where the trench 13 is formed. For example, since the deposition thickness adjustment of the liner silicon layer 19 is easy, the oxide liner layer 21 can also be formed to a thin thickness. Here, the direct oxidation process refers to a general wall thermal oxidation process. In the case of forming the oxide liner by side wall thermal oxidation, the thickness adjustment is not easy and the side wall loss of the active region 14 is caused .

The oxide liner layer 21 may be the same thickness or thicker as the liner silicon layer 19. The inner space of the trench 13 may not become narrower even if the oxide liner layer 21 is formed by the oxidation process 20 since the liner silicon layer 19 is already formed.

By oxidation step 20, the liner silicon layer 19 can be converted to an oxide liner layer 21. Thus, the oxide liner layer 21 may be silicon oxide. The oxide liner layer 21 may be the liner silicon layer 19 fully oxidized SiO 2 . The oxide liner layer 21 may cover the sidewalls and top surface of the hardmask layer 12.

The oxidation process 20 for forming the oxide liner layer 21 is performed using a radical oxidation process that can effectively convert the liner silicon layer 19 to an oxidized material while suppressing the sidewall loss of the active region 14 . The radical oxidation process may be performed at 750 to 900 占 폚. In another embodiment, the oxidation process 20 may be performed using a dry oxidation process of an oxygen atmosphere. The dry oxidation process may be performed at 800 to 900 占 폚.

The lining phenomenon of the active region 14 may occur during the oxidation process 20 of the liner silicon layer 19 as described above. The present embodiment forms the stress buffer layer 16 before the oxidation process 20 in order to prevent the lining phenomenon. The stress buffer layer 16 may serve as a support for preventing the lining of the active region 14.

The trench in which the oxide liner layer 21 is formed may be referred to as a " lined trench. &Quot;

As shown in FIG. 3C, the gap fill process and the planarization process can be sequentially performed. Accordingly, the gap fill layer 17 ', the stress buffer layer 16, and the oxide liner layer 21' may remain in the trench 13. The material of the gap fill layer 17 'and the forming method thereof will be described with reference to FIGS. 2D and 2E.

The element isolation structure 22 can be formed in the trench 13 by the series of steps as described above. The device isolation structure 22 includes an oxide liner layer 21 'formed on the bottom and sidewalls of the trench 13 and a gap fill layer 17' filling the trench 13 on the oxide liner layer 21 ' . The device isolation structure 22 may further include a stress buffer layer 16 and the stress buffer 16 may be located below the gap fill layer 17 '.

4A to 4F show a method of manufacturing a memory cell as an application example of the first embodiment. 4A to 4F illustrate a method according to the line A-A 'in FIG.

First, as shown in Figs. 2A to 2E, a device isolation structure 18 and an active region 14 may be formed.

Next, as shown in FIG. 4A, the hard mask layer 12 may be patterned. Accordingly, the hard mask layer 12 can be patterned to include a plurality of line-shaped openings (not shown). The plurality of openings may define an area in which the gate electrodes are disposed.

The opening of the hard mask layer 12 may be formed to expose a portion of the active region 14 and a portion of the device isolation structure 18. [

The portions exposed by the opening of the hardmask layer 12 may be etched to form at least one second trench, i. That is, to form the gate trench 31, the exposed portion of the active region 14 and the exposed portion of the device isolation structure 18 may be etched. In the etching of the element isolation structure 18, the gap fill layer 17 'may be etched to form the gate trench 31. The bottom surface of the gate trench 31 may be at a lower level than the upper surface of the active region 14. [ The gate trench 31 may be line-shaped. The gate trench 31 may extend across the active region 14 and the device isolation structure 18. When the buried gate electrode (or the buried word line) is formed in the gate trench 31, the effective channel length is increased, so that the short channel effect can be reduced.

The gate trench 31 may extend in either direction. The gate trench 31 may traverse the active region 14 and the device isolation structure 18. The gate trench 31 may have a third height H3 and a third width W3. The third height H3 of the gate trench 31 may be less than the first height H1 of the trench 13. [ The third height H3 of the gate trench 31 may be equal to the second height H2 of the gap fill space. That is, the recess portion (16R in Fig. 2C) above the stress buffer layer 16 may have the same height as the gate trench 31. [

As shown in FIG. 4B, a gate insulating layer 32 may be formed. The gate insulating layer 32 may be formed by a thermal oxidation process. In addition to the thermal oxidation process, the gate insulating layer 32 can be formed by various methods as follows.

An example for forming the gate insulating layer 32 may be an oxidation process after forming the oxide liner. That is, a high-temperature oxide can be deposited and then exposed to a radical oxidation process.

Another example for forming the gate insulating layer 32 may be an oxidation process after forming the liner polysilicon layer. That is, the liner polysilicon layer may be deposited and then exposed to a radical oxidation process. Thus, the liner polysilicon layer can be completely oxidized and converted into the gate insulating layer 32. The liner polysilicon layer can be formed using a seed layer.

Another example for forming the gate insulating layer 32 can be an oxidation process after forming the nitride liner. That is, the nitride liner can be completely oxidized by the radical oxidation process to form the gate insulating layer 32.

As described above, when the gate insulating layer 32 is formed by using the oxide liner, the liner polysilicon layer, or the nitride liner, the sidewall loss of the active region 14 can be minimized or prevented. As a result, even if the process of forming the element isolation structure 18 and the process of forming the gate insulating layer 32 proceed, the active region 14 can be formed stably without lining and bending.

A gate layer 33A may be formed on the gate insulating layer 32, as shown in Fig. 4C. The gate layer 33A may be formed to fill the gate trench 31 on the gate insulating layer 32. [ The gate layer 33A may cover the top of the hardmask layer 12. In order to lower the resistance of the gate electrode, the gate layer 33A may comprise a low resistance metal. For example, the gate layer 33A may comprise tungsten (W), titanium nitride (TiN), or a combination thereof.

As shown in FIG. 4D, a buried gate electrode 33 may be formed. In order to form the buried gate electrode 33, the gate layer 33A may be recessed. The upper surface of the buried gate electrode 33 may be at a lower level than the upper surface of the substrate 11. The recessing of the gate layer 33A can be performed by a planarization process and an etch-back process. The buried gate electrode 33 may be referred to as a buried word line. The buried gate electrode 33 may comprise a high dielectric constant material. Thus, the channel dose can be reduced.

As shown in FIG. 4E, a gate capping layer 34 may be formed on the buried gate electrode 33. To form the gate capping layer 34, the gate trench 31 may be filled with a capping material (not shown) on the buried gate electrode 33. Subsequently, the capping material may be planarized by a CMP or etch back process. The planarized capping material may be a gate capping layer 34.

Next, doped regions 35 and 36 may be formed. The doped regions 35 and 36 may be formed by a doping process such as an implant. The doped regions 35 and 36 may comprise an N-type dopant or a P-type dopant. The doped region 35 may be referred to as a " bit line contact node 35 ". The other doped region 36 may be referred to as a 'storage node contact node 36'.

As shown in FIG. 4F, a bit line contact plug 37 connected to the bit line contact node 35 may be formed. A bit line 39, which is subsequently connected to the bit line contact plug 37, may be formed. The bit line contact plug 37 may be connected to the bit line contact node 35 through the hard mask layer 12.

A storage node contact plug 38 connected to the storage node contact node 36 may be formed. The storage node contact plug 38 may be connected to the doped region 36 through the hard mask layer 12. A memory element 40, which is subsequently connected to the storage node contact plug 38, may be formed. The memory element 40 may comprise a capacitor.

Figure 5 is a top view illustrating an array of memory cells according to Figure 4f.

Referring to FIGS. 5 and 4F, the active region 14 may be defined as an island-shaped or a bar-shaped. The plurality of active regions 14 may have a short axis in the first direction X and a long axis in the second direction Y, respectively. The plurality of active regions 14 may be repeatedly formed in a state of being spaced apart from each other along the first direction (X direction) and the second direction (Y direction). The active areas neighboring each other along the second direction Y among the plurality of active areas 14 shift in opposite directions along the first direction X so as to overlap only partly along the second direction Y. [ So that they can be aligned with each other. The first direction X and the second direction Y may be perpendicular to each other. The plurality of active regions 14 may be inclined in an oblique direction with respect to the third direction X1 and the fourth direction Y1. The third direction X1 and the fourth direction Y1 may be perpendicular to each other.

A plurality of gate electrodes 33 may be formed to extend in the third direction X1 and a plurality of bit lines 39 may extend to extend in the fourth direction Y1. Each active region 14 may include a bit line contact node 35 and a storage node contact node 36. The bit line contact node 35 may be formed at the center of the active region 14. The storage node contact nodes 36 may be formed at the edges of the active region 14, respectively.

The storage node contact nodes 36 neighboring each other along the first direction X of the plurality of storage node contact nodes 36 may be separated by the element isolation structure 18. [ The bit line contact nodes 35 neighboring each other along the first direction X of the plurality of bit line contacts 35 may be separated by the device isolation structure 18. [ Thus, the spacing between neighboring storage node contact nodes 36 may be narrower than the spacing between the bit line contact nodes 35.

6 shows a semiconductor device according to the second embodiment.

Referring to FIG. 6, the semiconductor device 200 may include a substrate 201. The substrate 201 may include a first region R1 and a second region R2. A first isolation structure 210 may be formed in the first region R1 to define a plurality of first active regions 205. [ A second device isolation structure 211 that defines a second active region 206 in the second region R2 may be formed. A hardmask layer 202 may be formed on the first active region 205 and the second active region 206.

The first device isolation structure 210 may be formed in the first trench 203 and the second device isolation structure 211 may be formed in the second trench 204. The first and second trenches 203 and 204 may be formed by etching the substrate 201 using the hard mask layer 202. The first device isolation structure 210 and the second device isolation structure 211 may be made of the same material. The first device isolation structure 210 may include a first liner layer 207 ', a first stress buffer layer 208', and a first gap fill layer 209 '. The second element isolation structure 211 may include a second liner layer 207 ", a second stress buffer layer 208" and a second gap fill layer 209 ".

The first and second stress buffer layers 208 'and 208 "may be located below the first and second gap fill layers 209' and 209 ", respectively. The first stress buffer layer 208 'may partially fill the first trenches 203 on the first liner layer 207'. A second stress buffer layer 208 "may partially fill the second trenches 204 on the second liner layer 207 ". The first and second stress buffer layers 208 ', 208 "may comprise a flowable oxide. For example, the first and second stress buffer layers 208', 208" .

The first device isolation structure 210 may be narrower than the second device isolation structure 211. The first gap fill layer 209 'of the first device isolation structure 210 may be smaller in width than the second gap fill layer 209 "of the second device isolation structure 211. The first and second gap fill layers 209, 209 ") may comprise silicon oxide, silicon nitride, or a combination thereof.

The first and second device isolation structures 210 and 211 include first and second stress buffer layers 208 'and 208 ", respectively, thereby forming first and second active regions 205 and 206, It is possible to prevent the bending and the lining.

7A to 7E illustrate an example of a method of manufacturing the semiconductor device according to the second embodiment.

As shown in Fig. 7A, a substrate 51 can be prepared. The substrate 51 may comprise a semiconductor substrate. The substrate 51 may be a silicon-containing material, i.e., a silicon-base material. The substrate 51 may be a silicon substrate, a silicon germanium substrate, or an SOI substrate. The substrate 51 may include a first region R1 and a second region R2. The first region R1 may be a region where the first element isolation structure is to be formed and the second region R2 may be a region where the second element isolation structure is to be formed. The first region R1 may be a memory cell region, and the second region may be a region formed around the memory cell region. The second region may be referred to as a peripheral circuit region. A peripheral circuit for operation of the memory cell region may be formed in the peripheral circuit region.

Trenches 53 and 54 may be formed. At least one trench (53, 54) may be formed in the substrate (51). Active regions 55,56 may be defined by trenches 53,54. A hard mask layer 52 may be formed on the substrate 51 to form the trenches 53 and 54. [ The hardmask layer 52 may include at least one opening (not numbered). The opening of the hardmask layer 52 may define an area in which the trenches 53 and 54 are disposed. The hard mask layer 52 may comprise a material having an etch selectivity to the substrate 51. [ The hardmask layer 52 may comprise an oxide, a nitride, or a combination thereof. For example, the hardmask layer 52 may comprise silicon oxide such as TEOS. The first trench 53 and the first active region 55 may be formed in the first region R1 and the second trench 54 and the second active region 56 may be formed in the second region R2. . The first active region 55 may be formed at a higher density than the second active region 56. That is, a plurality of first active regions 55 may be formed in the first region Rl, and an array of the first active regions 55 may be more dense than the second active regions 56. [

The first trenches 53 may have a first height H11 and a first width W11. The second trench 54 may have a second height H12 and a second width W12. The first height H11 and the second height H12 may be the same or the second height H12 may be greater than the first height H11. The first width W11 may be smaller than the second width W12.

As shown in FIG. 7B, a liner layer 57 may be formed. The liner layer 57 may be conformally formed on the substrate 51. The liner layer 57 may lining the bottom and sidewalls of the first and second trenches 53, 54. In addition, the liner layer 57 may cover the sidewalls and top surface of the hard mask layer 52.

The liner layer 57 according to the present embodiment can have excellent step coverage. The first trench 53 and the second trench 54 in which the liner layer 57 is formed may be referred to as a "lined first trench and a line second trench", respectively. The liner layer 57 may be formed by CVD. In some embodiments, the liner layer 57 may be formed of an oxygen-containing material, which may be referred to as a silicon oxide-containing liner. In another embodiment, the liner layer 57 may be formed of a silicon-containing material, which may be referred to as a silicon-containing liner. In yet another embodiment, the liner layer 57 may be formed of a silicon nitride-containing material, which may be referred to as a silicon nitride-containing liner. Referring again to Figures 3A-3C, the silicon-containing liner may be exposed to an oxidation process in a subsequent process, and thus may be converted to a silicon oxide-containing liner.

As shown in FIG. 7C, a stress buffer layer 58 may be formed. For example, a stress buffer layer 58 may be formed on the liner layer 57. The stress buffer layer 58 may be filled in the first trench 53 and the second trench 54 simultaneously. The stress buffer layer 58 may comprise a silicon oxide-containing material such that the first and second trenches 53 and 54 may be partially filled with a silicon oxide-containing material. That is, the lined first trench 53 and the second trench 54 can be filled by the underfill of the stress buffer layer 58 so as to be lower in height than the upper surface of the substrate 51. As a comparative example, filling the lined first and second trenches 53, 54 with the overfill of the stress buffer layer 58 can result in bending of the active areas 55, 56.

The stress buffer layer 58 may comprise a flowable oxide. The stress buffer layer 58 may have a bottom-up shape and fill the bottoms of the first and second trenches 53 and 54. The upper surface of the stress buffer layer 58 may be at a lower level than the upper surface of the first and second active areas 55, 56. The stress buffer layer 58 may not be formed on the upper sidewalls of the first and second trenches 53 and 54 and the hard mask layer 52 have. The stress buffer layer 58 may be non-conformal. Thus, the stress buffer layer 58 may not stress the sidewalls of the first and second active regions 55, 56. As a result, the stress buffer layer 58 formed of a flowable oxide can suppress the bending of the active regions 55 and 56. The stress buffer layer 58 may be formed of a silazane-based material. As a comparative example, when the stress buffer layer 58 is conformally formed on the bottom and sidewalls of the first and second trenches 53 and 54, stress is applied to the first and second active regions 55 and 56, Which may result in bending.

Recess portions 58R and 58R 'may be defined above the stress buffer layer 58. [ The recessed portions 58R and 58R 'may be gap fill spaces at the time of the next gap filling. The stress buffer layer 58 can reduce the aspect ratio of the gap fill space in which the gap fill layer (59 in Fig. 7D) is to be formed. In other words, the aspect ratio of the first trenches 53 can be reduced by the stress buffer layer 58. As the stress buffer layer 58 is formed, the recess 58R formed in the first region Rl may have a third height H13 and a third width W13. The recess portion 58R 'formed in the second region R2 may have a fourth height H14 and a fourth width W14. The third height H13 and the fourth height H14 may be smaller than the first height H11 of the first trench 53. [ The recess portion 58R formed in the first region R1 may have a smaller aspect ratio than the first trench 53. [ The recess portion 58R 'formed in the second region R2 may have a smaller aspect ratio than the second trench 54. [ Therefore, the aspect ratio is reduced during the subsequent gapfil process, and the bending of the first and second active regions 55 and 56 can be suppressed.

As shown in Fig. 7D, the gap fill layer 59 can be formed by the gap fill process. A gap fill layer 59 may be formed on the stress buffer layer 58. The gap fill layer 59 may fill the first and second trenches 53 and 54 where the stress buffer layer 58 and the liner layer 57 are formed. The gap fill layer 59 may comprise an oxide, a nitride, or a combination thereof. In this embodiment, the gap fill layer 59 may comprise a silicon nitride-containing material, so that the first and second trenches 53, 54 may be filled with a silicon nitride-containing material. In another embodiment, the gap fill layer 59 may comprise a silicon oxide-containing material. When the silicon nitride-containing material is formed as the gap fill layer 59, for example, the refresh of the DRAM can be improved.

Since the recessed portions 58R and 58R 'are filled with the gap fill layer 59, the aspect ratio of the gap filling process is reduced, and bending of the first and second active regions 55 and 56 can be suppressed.

7E, a planarization process may be performed until the top surface of the hardmask layer 52 is exposed. For example, the gap fill layer 59, the stress buffer layer 58 and the liner layer 57 can be removed from the top of the hard mask layer 52. Accordingly, the gap fill layer 59, the stress buffer layer 58, and the liner layer 57 may remain in the first and second trenches 53 and 54.

The first device isolation structure 60 can be formed in the first trench 53 and the second device isolation structure 61 is formed in the second trench 54 by the series of steps described above .

The first device isolation structure 60 includes a first liner 57 'formed on the bottom and sidewalls of the first trench 53 and a first gap 57' filling the first trench 53 on the first liner 57 ' And a fill layer 59 '. The first device isolation structure 50 may further include a first stress buffer layer 58 'and a first stress buffer layer 58' may be located below the first gap fill layer 59 '. When the first gap fill layer 59 'includes an oxide, the first device isolation structure 60 may be a structure fully filled with an oxide-containing material. If the first gap fill layer 59 'comprises nitride, the first isolation structure 50 may be completely filled with an oxide-containing material and a nitride-containing material.

The second device isolation structure 61 includes a second gap 57 filling the second trench 54 on the second liner 57 "and the second liner 57" formed on the bottom and sidewalls of the second trench 54, The second device isolation structure 51 may further include a second stress buffer layer 58 "', and the second stress buffer layer 58 " may include a second gap fill layer < 59 "). ≪ / RTI > If the second gap fill layer 59 "includes an oxide, the second device isolation structure 61 may be a structure that is completely filled with an oxide-containing material. The second element isolation structure 61 may be completely filled with the oxide-containing material and the nitride-containing material.

8A to 8C show a manufacturing method according to a modification of the second embodiment.

The width of the second trench 54 is larger than the width of the first trench 53 so that the second stress buffer layer 58A formed in the second trench 54 has a higher height Can be low. Thus, the height of the second gap fill layer 59 "filling the second trenches 54 can be further increased. [0060] Thus, as shown in Fig. 8A, the second device isolation structure 61 has a low height The second device isolation structure 61 may include a second liner layer 57 ", a second stress buffer layer 58A, a second gap layer 58A on the second stress buffer layer 58A, Film layer 59 ".

7D, since the width of the second trench 54 is larger than that of the first trench 53, the second gap fill layer 59 " formed in the second trench 54 is formed to have a thickness The second trench 54 in which the second gap fill layer 59 "is formed can be filled with the additional gap fill layer 59A. 8B, the second element isolation structure 61 is formed on the second gap fill layer 59 ", and the second gap fill layer 59A is formed of the same material as the second gap fill layer 59 ".Gt; 59A < / RTI >

Fig. 8C shows a second device isolation structure 61 to which both the second stress buffer layer 58A of Fig. 8A and the additional gap fill layer 59A of Fig. 8B are applied.

Fig. 9 shows a memory cell as an application example of the second embodiment. The first region R1 may be a memory cell region, and the second region R2 may be a peripheral circuit region. A plan view of the memory cell will be described with reference to FIG.

First, as shown in FIGS. 7A to 7E, the first and second isolation structures 60 and 61 and the first and second active regions 55 and 56 may be formed.

Next, the gate trench 71, the gate insulating layer 72, the buried gate electrode 73, and the gate capping layer 74 are included in the first region Rl by the method shown in Figs. 4A to 4F A buried wordline structure may be formed.

Subsequently, a bit line contact node 75 and a storage node contact node 76 may be formed.

Subsequently, a bit line contact plug 77 connected to the bit line contact node 75 may be formed. A bit line 79 connected to the bit line contact plug 77 may be formed. The bit line contact plug 77 may be connected to the bit line contact node 75 through the hard mask layer 52. The bit line 79 and the bit line contact plug 77 may be formed by a single patterning process. Simultaneously with formation of the bit line 79, a planar gate structure may be formed in the second region R2. That is, the material used as the bit line 79 can be etched to form the planar gate structure in the second region R2. The planar gate structure may include a peripheral gate insulating layer 81, a first gate electrode 82 and a second gate electrode 83. The first gate electrode 82 and the bit line contact plug 77 may be the same material. The second gate electrode 83 and the bit line 79 may be the same material. The peripheral gate insulating layer 81 may be formed before the first gate electrode 82 and the bit line contact plug 77 are formed. The hard mask layer 52 may not remain in the second region R2. In the second region R2, source / drain regions 84 and 85 may be further formed in the second active region 56 below both sides of the planar gate structure. Although not shown, gate spacers may be further formed on both side walls of the planar gate structure in the second region R2.

A storage node contact plug 78 connected to the storage node contact node 76 may be formed. The storage node contact plug 78 may be connected to the doped region 76 through the hard mask layer 52. A memory element 80, which is subsequently connected to the storage node contact plug 78, may be formed. The memory element 80 may include a capacitor.

The semiconductor device according to the above-described embodiments may be applied to a dynamic random access memory (DRAM), and the present invention is not limited thereto. For example, a static random access memory (SRAM), a flash memory, a ferroelectric random access memory (FeRAM) (Magnetic Random Access Memory), and a PRAM (Phase Change Random Access Memory).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

11: substrate 12: hard mask layer
13: trench 14: active area
15: liner layer 16: stress buffer layer
17: gap fill layer 18: element isolation structure

Claims (20)

Etching the substrate to form a first trench defining an active region;
Forming a flowable material such that the first trench is filled by underfilling to a level lower than an upper surface of the substrate;
Forming a gap fill layer filling the first trench on the fluid material;
Planarizing the gap fill layer to form a device isolation structure including the fluid material and the gap fill layer;
Etching the active region and the gap fill layer of the device isolation structure to form a second trench that traverses the active region and the device isolation structure; And
Forming a gate electrode in the second trench;
≪ / RTI >
The method according to claim 1,
In forming the second trench,
And the height of the second trench is equal to or lower than the height of the gap fill layer.
The method according to claim 1,
Wherein the flowable material comprises a flowable silicon oxide.
The method according to claim 1,
Wherein the gap fill layer comprises silicon nitride.
The method according to claim 1,
Before the step of forming the flowable material,
And forming a liner layer lining the first trench.
6. The method of claim 5,
Wherein the liner layer comprises silicon oxide.
6. The method of claim 5,
Wherein the liner layer comprises a silicon layer,
Further comprising performing a thermal process to convert the silicon layer to a silicon oxide layer after forming the flowable material.
The method according to claim 1,
Before the step of forming the gate electrode,
And forming a gate insulating layer on bottoms and sidewalls of the second trench.
9. The method of claim 8,
Wherein forming the gate insulating layer comprises:
Forming a liner silicon layer on the bottom and sidewalls of the second trench;
Performing a thermal process to convert the liner silicon layer to a liner silicon oxide layer
≪ / RTI >
Etching the substrate to form a first trench defining a first active region and a second trench defining a second active region;
Forming a fluidic oxide such that the first and second trenches are filled by underfilling to a level lower than an upper surface of the substrate;
Forming a capillary filling the first and second trenches on the fluid oxide;
Forming a first device isolation structure and a second device isolation structure in the first trench and the second trench, the first device isolation structure and the second device isolation structure including the flowable oxide and the capillary, respectively;
Etching the gap fill layer of the first active region and the first device isolation structure to form a second trench that traverses the first active region and the first device isolation structure; And
Forming a first gate electrode in the second trench;
≪ / RTI >
11. The method of claim 10,
In forming the second trench,
And the height of the second trench is equal to or lower than the height of the gap fill layer.
11. The method of claim 10,
Wherein the flowable oxide comprises a flowable silicon oxide.
11. The method of claim 10,
Wherein the gap fill nitride comprises silicon nitride.
11. The method of claim 10,
Before the step of forming the fluid oxide,
And forming a liner layer lining the first trench and the second trench, respectively.
15. The method of claim 14,
Wherein the liner layer comprises silicon oxide.
15. The method of claim 14,
Wherein the liner layer comprises a silicon layer,
Further comprising performing a thermal process to convert the silicon layer to a silicon oxide layer after the step of forming the flowable oxide.
11. The method of claim 10,
Before the step of forming the first gate electrode,
And forming a first gate insulating layer on the bottom and sidewalls of the second trench.
18. The method of claim 17,
Wherein forming the first gate insulating layer comprises:
Forming a liner silicon layer on the bottom and sidewalls of the second trench;
Performing a thermal process to convert the liner silicon layer to a liner silicon oxide layer
≪ / RTI >
11. The method of claim 10,
After forming the first gate electrode,
And forming a second gate electrode on the second active region.
11. The method of claim 10,
Wherein the first device isolation structure is formed in a memory cell region and the second device isolation structure is formed in a peripheral circuit region for operation of the memory cell region.

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