KR20130005775A - Buried gate in semiconductor device and method for fabricating the same - Google Patents

Buried gate in semiconductor device and method for fabricating the same Download PDF

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Publication number
KR20130005775A
KR20130005775A KR1020110067385A KR20110067385A KR20130005775A KR 20130005775 A KR20130005775 A KR 20130005775A KR 1020110067385 A KR1020110067385 A KR 1020110067385A KR 20110067385 A KR20110067385 A KR 20110067385A KR 20130005775 A KR20130005775 A KR 20130005775A
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KR
South Korea
Prior art keywords
film
buried gate
recess pattern
gate electrode
buffer film
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KR1020110067385A
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Korean (ko)
Inventor
황선환
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에스케이하이닉스 주식회사
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Priority to KR1020110067385A priority Critical patent/KR20130005775A/en
Publication of KR20130005775A publication Critical patent/KR20130005775A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention provides a buried gate of a semiconductor device and a method for manufacturing the same, which prevents refresh degradation of the buried gate. The present invention provides a semiconductor device comprising: a recess pattern formed on a substrate including an isolation layer; A buried gate electrode embedded in a portion of the recess pattern; A buffer film having a compressive stress formed on the buried gate electrode along a step of the entire structure; And a capping film formed on the buffer film and having a tensile stress filling the remaining portion of the recess pattern, and forming a buffer film with a low temperature oxide film after forming the buried gate to prevent oxidation of the buried gate, and a tensile stress of the capping film. It has the effect of improving the refresh characteristics by mitigating.

Description

Buried gate of semiconductor device and manufacturing method therefor {BURIED GATE IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a buried gate of a semiconductor device and a manufacturing method thereof.

As the degree of integration of semiconductor devices increases, the planar area occupied by MOS transistors decreases. As a result, the channel length of the MOS transistor is reduced to generate a short channel effect. In particular, when a short channel effect occurs in the access MOS transistor adopted in the memory cell of the DRAM device, the threshold voltage of the DRAM cell is reduced and the leakage current is increased, thereby lowering the refresh characteristic of the DRAM device.

Accordingly, a recess gate MOS transistor has been introduced as a MOS transistor capable of suppressing a short channel effect by increasing the gate channel length even if the integration degree of the DRAM device is increased. The recess gate MOS transistor includes a recess formed in the active region of the semiconductor substrate, a gate electrode formed in the recess, and source / drain regions formed in the active regions on both sides of the gate electrode so as to be spaced apart by the recess. Recess gate transistors having such a structure can suppress problems due to short channel effects by increasing the channel length even though the degree of integration increases.

However, even if the recess gate MOS transistor is applied to a semiconductor device such as a DRAM device, there is a limit to the high integration of the device. On the source / drain regions of the recess gate MOS transistor, a contact structure for electrical connection with the bit lines and capacitors is formed, which reduces contact resistance and suppresses electrical shorts between neighboring contact structures or between the contact structure and the gate electrode. In order to achieve this, an adequate contact area must be secured. That is, the active regions on both sides of the gate electrode where the source / drain regions are formed should have an area of a certain degree or more for good contact formation. However, although the problems due to the short channel effect can be suppressed by applying the recess gate MOS transistor, there is still a need for an appropriate contact area.

Accordingly, a semiconductor device having a buried word line has been proposed. The buried word line is a technique of forming a trench crossing the channel region and the device isolation layer, forming a word line filling a portion of the trench, and forming an insulating pattern filling the remaining portion of the trench. As a result, the wordline is buried below the surface of the semiconductor substrate, providing a relatively large effective channel length. In addition, the capacitance value of the bit line and the word line may be reduced to reduce the array voltage.

Meanwhile, a nitride film is used to fill the remaining portion after the word line is formed to fill a portion in the trench when the buried word line is formed. However, in the case of a nitride film, there is a problem in that refresh deterioration occurs due to tensile stress.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a buried gate of a semiconductor device and a manufacturing method thereof for preventing the deterioration of the buried gate.

The buried gate of the semiconductor device according to the embodiment of the present invention for achieving the above object is a recess pattern formed on a substrate including an isolation layer; A buried gate electrode embedded in a portion of the recess pattern; A buffer film having a compressive stress formed on the buried gate electrode along a step of the entire structure; And a capping film formed on the buffer film and having a tensile stress filling the remaining portion of the recess pattern.

In particular, the buffer layer may include a low temperature oxide layer, and the capping layer may include a nitride layer.

A semiconductor device manufacturing method according to an embodiment of the present invention for achieving the above object comprises the steps of forming a recess pattern by etching a substrate; Forming a buried gate electrode filling a portion of the recess pattern; Forming a buffer film having a compressive stress along the step of the entire structure on the buried gate electrode; Post-processing the buffer film; And forming a capping film having a tensile stress filling the remaining portion of the recess pattern on the buffer film.

Particularly, the buffer film includes a low temperature oxide film, and is formed at a temperature of 5 ° C. to 400 ° C., and the post-treatment may include plasma oxidation and plasma selective oxidation. ), Thermal Oxidation, Thermal Selective Oxidation, Furnace Heat Treatment and Rapid Thermal Process (RTP) or any one or more heat treatment methods selected from the group consisting of It characterized by proceeding to.

The buried gate of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention described above form a buffer film with a low temperature oxide film after formation of the buried gate to prevent oxidation of the buried gate, and to reduce the tensile stress of the capping film to improve refresh characteristics. It works.

1 is a cross-sectional view illustrating a buried gate of a semiconductor device according to an embodiment of the present invention;
2A to 2I are cross-sectional views illustrating a method of manufacturing a buried gate in a semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

1 is a cross-sectional view illustrating a buried gate of a semiconductor device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a recess pattern 17 is formed on the substrate 10 on which the device isolation layer 16 is formed. Then, a buried gate electrode 18A filling a part of the recess pattern 17 is formed. In this case, the buried gate electrode 18A includes a conductive material, and the conductive material includes a single film of titanium nitride (TiN) or a stacked film of titanium nitride and tungsten (W).

Then, the buffer film 19 is formed along the step of the entire structure including the buried gate electrode 18A. The buffer film 19 includes a low temperature oxide film formed at a temperature of 5 ° C to 400 ° C.

The first and second capping films 20B and 21 are formed on the buffer film 19. The first and second capping films 20B and 21 include a nitride film.

As described above, the present invention forms a buffer film 19 formed of a low temperature oxide film on the buried gate electrode 18A to prevent oxidation of the buried gate electrode 18A, while the first and second capping films formed of a nitride film ( 20B, 21) has the effect of improving the refresh by reducing the tensile stress.

Reference numeral 11 denotes a pad oxide film, 12 a pad nitride film, 13 an etch stop film, 14 a sidewall oxide film, and 15 a liner nitride film.

2A to 2I are cross-sectional views illustrating a method of manufacturing a buried gate in a semiconductor device according to an embodiment of the present invention. 2A to 2I illustrate a method of manufacturing the buried gate illustrated in FIG. 1, and the same reference numerals as those of FIG. 1 will be described.

As shown in FIG. 2A, an isolation region 16 is formed on the substrate 10 to define an active region. The device isolation layer 16 proceeds through a shallow transistor isolation (STI) process.

In the STI process, first, the pad oxide film 11 and the pad nitride film 12 are formed on the substrate 10, and the etch stop layer 13 is formed on the pad nitride film 12. In the embodiment of the present invention, although the pad nitride film 12 is formed, it is also possible to form a polysilicon film instead of the pad nitride film.

Subsequently, after the photoresist pattern for opening the device isolation region is formed on the etch stop layer 13, the etch stop layer 13, the pad nitride layer 12, and the pad oxide layer 11 are patterned. Subsequently, a trench is formed by etching the substrate 10 at a predetermined depth with the patterned etch stop layer 13 and the pad nitride layer 12 as an etch barrier.

Next, a sidewall oxide layer 14 and a liner nitride layer 15 are formed on the sidewalls and the bottom of the trench, and an insulating layer filling the trench is formed on the liner nitride layer 15 to define an active region. An element isolation film 16 is formed. The etch stop film 13 is a film serving as an etch stop target in a process of filling an insulating film in the trench and then planarizing the insulating film to remain only in the trench, and preferably, the etch stop film 13 is formed of a material having a selectivity with respect to the insulating film. The insulating film for forming the device isolation film 16 includes an oxide film, wherein the etch stop film 13 is preferably formed of a nitride film.

As shown in FIG. 2B, the etch stop layer 13, the pad nitride layer 12, and the pad oxide layer 11 are patterned, and the substrate 10 is etched using the etch barrier to form the recess pattern 17. . The process of patterning the etch stop film 13, the pad nitride film 12, and the pad oxide film 11 forms a photoresist pattern (not shown) for opening a line type recess pattern region on the etch stop film 13. The etching stop film 13, the pad nitride film 12 and the pad oxide film 11 are etched using the photoresist pattern as an etch barrier. In addition, the recess pattern 17 is formed in a line type, and is formed in both the active region and the device isolation layer 16.

As shown in FIG. 2C, the conductive material 18 for the buried gate is formed in the recess pattern 17. Before forming the buried gate conductive material 18, a gate insulating film (not shown) is formed along the stepped portion of the recess pattern 17. The gate insulating film 18 is formed of a buried gate.

The buried gate conductive material 18 is formed to a thickness that sufficiently fills the recess pattern 17. After the buried gate conductive material 18 is formed, the planarization process is performed by planarization to a target in which the upper portion of the etch stop layer 13 is opened. The planarization is preferably carried out in a chemical mechanical polishing process. The buried gate conductive material 18 may be formed of a single film or a multilayer film. For example, the buried gate conductive material 18 may be a titanium nitride film (TiN) in the case of a single layer, and the buried gate conductive material 18 may be a stacked structure of the titanium nitride film and the tungsten film (W).

As shown in FIG. 2D, the buried gate conductive material 18 (see FIG. 2C) is etched to a height at least lower than the surface of the substrate 10. Accordingly, the buried gate conductive material 18 (see FIG. 2C) remains only in the recess pattern 17. The conductive material 18 for the buried gate 18 (refer to FIG. 2C) is preferably etched by an etch back process.

Hereinafter, the etched conductive material 18 for the buried gate is referred to as a buried gate electrode 18A. In addition, the structure embedded in the recess pattern 17 is referred to as a buried gate.

As shown in FIG. 2E, the buffer film 19 is formed along the step of the entire structure including the buried gate electrode 18A. The buffer film 19 serves to alleviate the tensile stress of the subsequent capping film and to improve refresh.

The buffer film 19 is formed of an oxide film, and the oxide film includes a silicon oxide film (SiO 2 ). In particular, the buffer film 19 preferably proceeds at a temperature at which the buried gate electrode 18A is not oxidized. In other words, the buffer film 19 is formed of a low temperature oxide film.

The buffer film 19 is preferably formed in a thickness of 10 kPa to 1000 kPa, and is formed by atomic layer deposition in order to form a uniform thickness along the step of the entire structure. The atomic layer deposition is performed at a temperature of 5 ° C to 400 ° C to prevent oxidation of the buried gate electrode 18A. In addition, as the process proceeds to improve the film quality of the buffer film 19, the plasma may be turned on / off.

The atomic layer deposition method for forming the buffer film 19 uses any one selected from the group consisting of a chloride chloride group consisting of SiCl, SiCl 4 and Si 2 Cl 6 as a silicon precursor. In addition, H 2 O or 4H 2 O is used as an oxygen precursor (Oxygen Precursor), and pyridine (C 5 H 5 N) is used as a catalyst.

Subsequently, post treatment is performed on the buffer film 19. The post-treatment is to improve the film quality and the etching rate of the buffer film 19 and may be performed by heat treatment. Post-treatment includes Plasma Oxidation, Plasma Selective Oxidation, Thermal Oxidation, Thermal Selective Oxidation, Furnace Heat Treatment and Rapid Thermal Process (RTP) Any one heat treatment method selected from the group consisting of or two or more heat treatment methods may be continuously performed. At this time, the furnace heat treatment or rapid heat treatment may proceed in an NH 3 or N 2 atmosphere.

As described above, by forming the buffer layer 19 on the buried gate electrode 18A, the tensile stress of the subsequent capping layer may be alleviated and the refresh may be improved.

As shown in FIG. 2F, the capping film 20 is formed on the buffer film 19 to a thickness that sufficiently fills the remaining portion of the recess pattern 17. The capping film 20 is formed of an insulating film, and the insulating film includes a nitride film. At this time, the capping film 20 is preferably formed to a thickness of 500 kPa to 5000 kPa so as to sufficiently fill the recess pattern 17.

On the other hand, it is difficult to secure a gap fill margin due to the buried depth of the capping film 20, and thus voids occur in the capping film 20 that is buried between the pad nitride film 12 and the etch stop film 13. Can be.

These voids cause problems in device reliability and thus need to be removed. To this end, as shown in FIG. 2G, the first capping film 20 (see FIG. 2F) is etched with the target where the voids are exposed. The first capping film 20 (refer to FIG. 2F) is etched by dry etching, and it is preferable to proceed to a target in which the void 100 formed inside the first capping film 20 (refer to FIG. 2F) is opened. . The etched first capping film 20 (see FIG. 2F) is hereinafter referred to as first capping film 20A.

As shown in FIG. 2H, the cleaning process is performed to remove the first capping film 20A (see FIG. 2G) remaining on the sidewall of the etch stop film 13 or the pad nitride film 12. The first capping film 20A (see FIG. 2G) in which the cleaning process is performed is referred to as a first capping film 20B.

As shown in FIG. 2I, a second capping film 21 is formed on the first capping film 20B. The second capping film 21 may be formed of the same material as the first capping film 20B, for example, a nitride film.

The second capping film 21 forms an insulating film on the first capping film 20B to sufficiently fill the remaining portion, and then planarizes the target to which the etch stop film 13 is exposed. The planarization may be performed by a chemical mechanical polishing process. As the planarization is performed to the target on which the surface of the etch stop layer 13 is exposed, the buffer layer 19 on the etch stop layer 13 is also etched. .

As described above, the present invention forms the buffer film 19 using a low temperature oxide film after forming the buried gate electrode 18A to prevent oxidation of the buried gate electrode 18A, and at the same time, the first and second capping films formed of a nitride film ( 20B, 21) has the advantage of improving the refresh by reducing the tensile stress.

Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

10 substrate 11 pad oxide film
12: pad nitride film 13: etching stop film
14 side wall oxide film 15 liner nitride film
16 device isolation layer 17 recess pattern
18A: buried gate electrode 19: buffer film
20: first capping film 21: second capping film

Claims (5)

A recess pattern formed on the substrate including the isolation layer;
A buried gate electrode embedded in a portion of the recess pattern;
A buffer film having a compressive stress formed on the buried gate electrode along a step of the entire structure; And
A capping film formed on the buffer film and having a tensile stress to fill the remaining portion of the recess pattern.
A buried gate of a semiconductor device comprising a.
The method of claim 1,
The buffer film includes a low temperature oxide film, and the capping film includes a nitride film.
Etching the substrate to form a recess pattern;
Forming a buried gate electrode filling a portion of the recess pattern;
Forming a buffer film having a compressive stress along the step of the entire structure on the buried gate electrode;
Post-processing the buffer film;
Forming a capping film having a tensile stress filling the remaining portion of the recess pattern on the buffer film;
≪ / RTI >
The method of claim 3,
The buffer film comprises a low temperature oxide (Low Temperature Oxide), and is formed at a temperature of 5 ℃ ~ 400 ℃ semiconductor device manufacturing method.
The method of claim 3,
The post-processing step,
Group consisting of Plasma Oxidation, Plasma Selective Oxidation, Thermal Oxidation, Terminal Selective Oxidation, Furnace Heat Treatment and Rapid Thermal Process (RTP) A method of manufacturing a semiconductor device which continuously proceeds any one of the heat treatment methods or two or more heat treatment methods selected from among them.
KR1020110067385A 2011-07-07 2011-07-07 Buried gate in semiconductor device and method for fabricating the same KR20130005775A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9853031B1 (en) 2016-08-12 2017-12-26 Samsung Electronics Co., Ltd. Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9853031B1 (en) 2016-08-12 2017-12-26 Samsung Electronics Co., Ltd. Semiconductor device
US10199379B2 (en) 2016-08-12 2019-02-05 Samsung Electronics Co., Ltd. Semiconductor device

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