TWI597822B - Self-aligned buried word line isolation and fabrication method thereof - Google Patents

Description

Self-aligned buried word line isolation structure and method of forming same

The present invention relates to a semiconductor memory device, and more particularly to a self-aligned buried word line isolation structure and method of forming the same.

A dynamic random access memory (DRAM) is mainly composed of a capacitor and a transistor. With the trend toward miniaturization of electronic products, there is also a need for a miniaturization of memory devices. However, the capacitors in the conventional dynamic random access memory occupy most of the available space, so that the volume of the dynamic random access memory can no longer be reduced, and a capacitorless dynamic random access memory is developed.

Therefore, as memory miniaturization progresses, there is still a need for a memory device having a smaller critical dimension and a more simple and low-cost formation method.

An embodiment of the present disclosure discloses a method for forming a self-aligned buried word line isolation structure, including: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a plurality of unit cells are located in the array region, wherein the unit cell Each of the regions includes two word lines; forming a first material layer on the semiconductor substrate, wherein the upper surface of the first material layer has a recess between two adjacent cell regions; forming a second a layer of material on the first layer of material and filled in the recess, wherein a second material layer at the bottom of the recess has a first thickness, and a second material layer at the cell region has a second thickness greater than the first thickness; a first etching step is performed along the recess through the first material layer and a material layer for forming a word line isolation trench in the semiconductor substrate between two adjacent cell regions, wherein the position of the word line isolation trench corresponds to the position of the recess; A second etching step to expand the bottom of the word line isolation trench, wherein the word line isolation trench has an upper portion and an enlarged bottom portion.

Another embodiment of the present disclosure discloses a self-aligned buried word line isolation structure including: a semiconductor substrate including an array region and a plurality of cell regions in the array region, wherein each of the cell regions includes Two word lines; a word line isolation trench between two adjacent cell regions, wherein the word line isolation trench has an upper portion and an enlarged bottom portion; the doped region is located in the semiconductor substrate and is surrounded by the expansion The bottom; and the filling material, filled in the word line isolation trench.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

1a‧‧‧First material

2a‧‧‧ Cover layer

10‧‧‧Array area

20‧‧‧ peripheral circuit area

100‧‧‧Self-aligned buried word line isolation structure

102‧‧‧Semiconductor substrate

104‧‧‧Shallow trench isolation structure

106‧‧‧ Tunneling oxide layer

108‧‧‧ character line

110‧‧‧First material grid layer

110p‧‧‧ protruding parts

112‧‧‧First material layer

114‧‧‧Second material layer

118‧‧‧ openings

120‧‧‧word line trench

130‧‧‧ notch

140‧‧‧ trench

150‧‧‧word line isolation trench

150a‧‧‧ upper

150b‧‧‧ enlarged bottom

160‧‧‧Doped area

170‧‧‧Filling materials

210‧‧‧Doping step

C‧‧‧cell area

s ₁ ‧‧‧first spacing

s ₂ ‧‧‧second spacing

t ₁ ‧‧‧first thickness

t ₂ ‧‧‧second thickness

w ₁ ‧‧‧first width

w ₂ ‧‧‧second width

1 to 7 are schematic cross-sectional views showing a process of the self-aligned buried word line isolation structure 100 of some embodiments.

The above and other objects, features and advantages of the present invention will become more <RTIgt; However, it will be understood by those of ordinary skill in the art that the description thing In fact, in order to make the description clearer, the relative size ratio of various feature structures can be arbitrarily increased or decreased. Throughout the specification and in all figures, the same reference numerals refer to the same features.

The present disclosure provides a self-aligned buried word line isolation structure and a method for forming the same. FIGS. 1 through 7 are schematic cross-sectional views of a self-aligned buried word line isolation structure 100 according to some embodiments of the present disclosure. .

Referring to FIG. 1, a semiconductor substrate 102 is provided that includes an array region 10 having a plurality of cell regions C and peripheral circuit regions 20 adjacent to the array regions 10. In addition, as shown in FIG. 1, shallow trench isolation (STI) 104 is located in the array region 10 and the peripheral circuit region 20, respectively.

The material of the semiconductor substrate 102 may include germanium, gallium arsenide, gallium nitride, germanium germanium, silicon on indulator (SOI), other suitable materials, or a combination thereof. In some embodiments, the semiconductor substrate 102 is a germanium substrate.

The function of the shallow trench isolation structure 104 is to electrically isolate the components that will subsequently be formed in the array region 10. It should be understood by those skilled in the art that the shallow trench isolation structure 104 is a plurality of elongated regions arranged in parallel as viewed from a plan view, and the word lines 108 are also a plurality of elongated regions arranged in parallel. Since the extending direction of the shallow trench isolation structure 104 and the extending direction of the word line 108 are not perpendicular or parallel to each other, they are arranged at a specific angle (for example, between about 10-80 degrees). Therefore, the resulting profile is different as the position of the line is different. Also, in the cross-sectional view, the trench isolation structure 104 and the word line 108 are not regularly arranged in the array region 10, as shown in FIG.

Still referring to FIG. 1, a tunneling oxide layer 106, a first material 1a, and a mask layer 2a are sequentially deposited (from bottom to top) on the surface of the semiconductor substrate 102 and the shallow trench isolation structure 104. . Next, a masking process is performed on the mask layer 2a located in the array region 10 to define a plurality of openings 118. An etching step is performed along the opening 118 and through the first material, the tunnel oxide layer 106, the semiconductor substrate 102, and/or the shallow trench isolation structure 104 to form a plurality of word line trenches 120, as shown in FIG. .

Referring to FIG. 2, the conductive material and the first material 1a are sequentially filled in the word line trenches 120. The conductive material filled in the word line trenches 120 forms word lines 108. Since the word line 108 is buried under the top surface of the semiconductor substrate, it can also be referred to as a "buried word line." Furthermore, the first material 1a filled in the word line trench 120 is connected to the first material 1a overlying the tunnel oxide layer 106, thereby forming the first material gate film layer 110. The first material gate film layer 110 has a fence-shaped profile, and the first material gate film layer 110 has a plurality of protrusions 110p corresponding to the word line 108 in the cell region C. Location, as shown in Figure 2. After the first material gate film layer 110 is formed, the mask layer 2a is removed.

Referring to FIG. 3, after forming the first material gate film layer 110, depositing the same first material 1a as the first material gate film layer 110 on the first material gate film layer 110, so that the first material 1a A suitable thickness is stacked along the fence-like cross-sectional profile of the first material gate film layer 110 to form a first material layer 112 having a plurality of notches 130. In the present embodiment, each of the notches 130 on the upper surface of the first material layer 112 is interposed between two adjacent cell regions C, as shown in FIG.

Referring to FIG. 2, in some embodiments, the protrusions 110p of the first material gate film layer 110 have different pitches. The two protrusions 110p located in the same cell region C have a first pitch s ₁ . The two protrusions 110p located in the adjacent unit cell region C have a second pitch s ₂ . By selecting the first pitch s ₁ and the second pitch s ₂ , the formation position of the notch 130 can be controlled. For example, in the embodiment, the first pitch s _{1 is} smaller than the second pitch s ₂ . When the deposited first material fills the space of the first pitch s ₁ , the space at the second pitch s ₂ has not been completely filled. In this way, the recess 130 can be formed between the adjacent unit cells C. It should be noted that in the present example, the formation position of the notch 130 can be controlled by forming the first material gate film layer 110 and selecting the first pitch s ₁ and the second pitch s ₂ . In other words, according to the present example, after the word line is formed, no additional patterning process is required to define the notch 130 between two adjacent cell regions C. Therefore, the process steps and the use of the mask can be reduced, thereby reducing the cost.

In addition, it should be noted that the step of depositing the first material 1a on the first material gate film layer 110 is a non-conformal deposition step, which may form an overhang at the top of the notch 130 (overhang) ). Thus, the top of the recess 130 has a first aperture w ₁ and the bottom of the recess 130 has a second aperture w ₂ that is greater than or equal to the first aperture w ₁ . As shown in FIG. 3, in the present embodiment, the second aperture w ₂ at the bottom of the recess 130 is greater than the first aperture w _{1 of the} top, this feature will help to form a second material having a different thickness in subsequent steps. Layers, which are discussed in more detail below.

Referring to FIG. 3, after forming the first material layer 112 having the plurality of notches 130, a second material different from the first material 1a is deposited to form the second material layer 114 on the first material layer 112 and fill in Into the notch 130. In the present embodiment, the second material layer 114 at the bottom of the recess 130 has a first thickness t ₁ , and the second material layer 114 located in the cell region has a second thickness t ₂ greater than the first thickness, such as the third The figure shows.

It should be noted that since the second aperture w ₂ at the bottom of the recess 130 is larger than the first aperture w _{1 of the} top, when the second material is deposited into the recess 130, the overhang at the top of the recess 130 will be obscured. The effect, thus reducing the amount of the second material filled into the recess 130. In this way, the first thickness t _{1 of} the second material layer at the bottom of the recess 130 can be made smaller than the second thickness t _{2 of the} unit cell region. In some embodiments, the second thickness t ₂ has a first thickness t ₁ ratio t ₂ / t ₁ is about 3-10. In this embodiment, the thickness of the second material layer at the bottom of the recess is less than the thickness of the cell region, and this feature will help to reduce the critical dimension (CD) of the memory device in a subsequent step. This will be discussed in detail below.

The first material and the second material may be deposited using a suitable process. In the present embodiment, the first material and the second material are deposited by a high density plasma chemical vapor deposition (HDPCVD) process to form the first material layer 112 and the second material layer 114.

Referring to FIG. 4, after forming the second material layer 114, a first etching step is performed along the recess 130 through the first material layer 112 and the second material layer 114 to form two adjacent cells. A trench 140 is formed between the regions.

In the present disclosure, the term "self-aligned" means that the first etching step is performed by using the first material layer 112 and the second material layer 114 as an etching mask, so that the trench can be made without using an additional mask. The position of the slot 140 corresponds to the position of the recess 130 as shown in FIG. As described above, in accordance with the method of the present disclosure, in the process of forming the word line isolation structure, no additional patterning process is required to define the word line isolation structure between two adjacent cell regions. therefore, It can reduce the cost of the process steps and the use of the mask.

In the present disclosure, the first etching step has a high etch selectivity for the first material and the second material. In other words, the first etching step has an etching rate R ₁ for the first material layer 112 that is greater than the etching R ₂ for the second material layer 114. Again, as described above, the first thickness t _{1 of the} second material layer 114 at the bottom of the recess 130 is less than the second thickness t ₂ at the cell region. When the first etching process is performed, the second material layer 114 at the bottom of the recess 130 is relatively small in thickness, so that it is removed by etching faster, exposing the first material layer 112. In contrast, the second material layer 114 located in the cell region has a large thickness, so that it can serve as an etching mask to protect the first material layer 112 located at the opening and the sidewall of the recess 130, thereby avoiding excessive exposure of the first material layer 112. Etching. In some embodiments, the ratio R ₁ /R ₂ of the first etching step to the etching rate of the first material layer 112 relative to the etching rate of the second material layer 114 is about 2-20.

It should be noted that if the first etching step is directly performed to form the trench 140 without forming the second material layer 114, the first etching step will overetch the first material layer 112 and widen the aperture of the trench 140. So that it is larger than the first aperture w _{1 of the} recess 130. As such, when the first etching step proceeds to the semiconductor substrate 102, the surface area of the semiconductor substrate 102 is reduced because the aperture of the trench 140 at the semiconductor substrate 102 is widened. Therefore, in a subsequent step, when a contact electrically connected to an external circuit is formed on the surface of the semiconductor substrate 102, the surface area of the semiconductor substrate 102 that can be electrically connected to the subsequently formed contact is reduced. As a result, the resistance of the contacts will increase, increasing the risk of electrical failure. Moreover, if the aperture of the trench 140 is too wide, it is not conducive to reducing the critical size of the memory device.

The present disclosure discloses that the first thickness t _{1 of} the second material layer 114 at the bottom of the recess 130 is smaller than the second thickness t _{2 of the} cell region, and the first etching step has a high etching for the first material and the second material. Optionally, the first material layer 112 can be protected during etching, thereby avoiding widening the aperture of the trench 140. Therefore, the risk of subsequent electrical failure can be reduced and the critical dimension of the memory device can be reduced.

In order for the first etching step to have a high etch selectivity for the first material and the second material, a suitable first material, second material, and/or etching process may be selected. For example, in the present embodiment, the first material is a nitride, such as tantalum nitride; and the second material is an oxide, such as hafnium oxide, and is dry etched. It should be noted that the first materials, the second materials, and the etching processes listed above are for illustrative purposes only and are not intended to limit the invention. It will be understood by those of ordinary skill in the art that the first material, the second material, and/or the etching process can be selected as desired to provide a first etching step with high etch selectivity for the first material and the second material. Therefore, any combination of the first material, the second material, and/or the etching process is such that the first etching step has a high etching selectivity (R ₁ /R ₂ greater than 2) for the first material and the second material. The scope of protection disclosed herein.

Referring to FIG. 5, the first etching step is continued along the trench 140 through the semiconductor substrate 102 and/or the shallow trench isolation structure 104 to form the upper portion 150a of the word line isolation trench 150 in the semiconductor substrate 102. Next, after the upper portion 150a of the word line isolation trench 150 reaches a predetermined depth, a second etching step is performed at the bottom of the word line isolation trench 150 to expand the bottom of the word line isolation trench 150 to form an enlarged portion. The bottom 150b is shown in Figure 5. In some embodiments, the second etching step includes performing a dry etch.

It should be noted that in the disclosure, the first etching step is non-equal An anisotropic etching step, and the second etching step is an isotropic etching step. By performing the anisotropic etching by the first etching step, the upper portion 150a of the word line isolation trench 150 can have a uniform aperture, which helps to reduce the critical dimension of the memory device. Moreover, by performing an isotropic etching by the second etching step, the bottom of the word line isolation trench 150 can be enlarged to form an enlarged bottom portion 150b, which can increase the surface area of the bottom of the word line isolation trench 150. Therefore, when the doping process is subsequently performed, the enlarged bottom portion 150b can produce a doped region having a higher dopant concentration and a larger volume under the same doping process conditions. In this way, the word line isolation trench 150 can be made to have a better isolation effect.

In some embodiments, the second etch process can use an etch process that is the same as the first etch process, and an etch gas that is the same as the first etch process can be used. In other embodiments, the second etch process may use an etch process that is the same as the first etch process, but uses an etch gas that is different than the first etch process. In this embodiment, the first etching process and the second etching process are the same dry etching process. In this embodiment, the same etching process is selected in the first etching process and the second etching process, and the degree of isotropic of the etching can be controlled only by adjusting other process parameters without replacing the process equipment. For example, adjustable process parameters include, but are not limited to, the following: etch gas flow, etch gas pressure, etch temperature, and/or etch power. In some embodiments, the degree of isotropicity of the etch can be increased by reducing the flow of the etch gas.

It should be noted that the first etching process, the second etching process, and the etching process parameters listed above are for illustrative purposes only and are not intended to limit the invention. It should be understood by those of ordinary skill in the art that the first etching process, the second etching process, and/or the etching process parameters can be selected as needed to make the first etch The engraving step and the second etching process have different degrees of isotropic. Therefore, any combination of the first etching process, the second etching process, and/or the etching process parameter is a protection of the present disclosure as long as it can be an anisotropic etching step and the second etching step is an isotropic etching step. range.

Referring to FIG. 6, after the word line isolation trench 150 (including the upper portion 150a and the enlarged bottom portion 150b) is formed in the semiconductor substrate 102, a doping step 210 is performed to form the doped region 160 in the semiconductor substrate 102 and surround Expanded bottom 105b. In some embodiments, the doping step 210 can be performed using a P-type dopant (eg, boron). In other embodiments, the doping step 210 can be performed using an N-type dopant (eg, phosphorus).

Since the doping step is performed in a direction substantially perpendicular to the surface of the semiconductor substrate 102, the formed doped region 160 surrounds the enlarged bottom portion 105b of the word line isolation trench 150 and is substantially lightly doped or even The sidewall region of the upper portion 150a of the word line isolation trench 150 is undoped as shown in FIG.

It should be noted that the present disclosure extends the bottom of the word line isolation trench by a second etching process to increase the surface area to be doped. Therefore, when the doping process is performed, the enlarged word line isolation trenches at the bottom of the present disclosure can form a larger volume under the same doping process conditions than the un-expanded word line isolation trenches at the bottom. Doped regions and have a higher dopant concentration. In this way, better isolation can be obtained.

Referring to FIG. 7, after the doping step 210 is performed and the doping region 160 is formed, the filling material 170 is filled into the word line isolation trench 150 to complete the word line isolation structure. Suitable fill material 170 can include an insulating material or a conductive material. In some embodiments, the fill material 170 includes nitrides, oxides, High dielectric constant (high-k) dielectric materials or other suitable insulating materials.

Still referring to FIG. 7 , the present disclosure also provides a self-aligned buried word line isolation structure 100 including a semiconductor substrate 102 having an array region 10 and a peripheral circuit region adjacent to the array region 10 . 20. The self-aligned buried word line isolation structure 100 also includes a plurality of cell regions C located in the array region 10, wherein each of the cell regions C includes two word lines 108. The self-aligned buried word line isolation structure 100 also includes a word line isolation trench 150 between two adjacent cell regions C, wherein the word line isolation trench 150 has an upper portion 150a and an enlarged portion. Bottom 150b. The self-aligned buried word line isolation structure 100 also includes a doped region 160 located in the semiconductor substrate 102 and surrounding the enlarged bottom portion 150b, wherein the doped region 160 may include a P-type dopant or an N-type dopant. The self-aligned buried word line isolation structure 100 also includes a fill material 170 that is filled into the word line isolation trenches 150, wherein the fill material 170 can comprise an insulating material or a conductive material.

In this embodiment, since the first material layer 112 and the second material layer 114 serve as etching masks during the first and second etching processes, respectively, the semiconductor substrate 102 located in the peripheral circuit region 20 is protected from being etched by the etching process. Therefore, no additional etching masks need to be formed. So come. An etching mask and patterning process can be omitted, which simplifies the process and reduces costs.

Compared with the prior art, the present disclosure provides a method for forming a self-aligned buried word line isolation structure, which has at least the following advantages:

(1) The formation position of the notch 130 (subsequent groove 140) is controlled by forming the first material gate film layer 110 and selecting the first pitch s ₁ and the second pitch s ₂ . After the word line is formed, no additional patterning process is required to define the notch 130 between two adjacent cell regions C. Therefore, the process steps and the use of the mask can be reduced, thereby reducing the cost.

(2) by making the first thickness t _{1 of} the second material layer 114 at the bottom of the recess 130 smaller than the second thickness t ₂ at the cell region, and making the first etching step high for the first material and the second material The etch selectivity protects the first material layer 112 during etching, thereby avoiding widening the aperture of the trench 140. Therefore, the risk of subsequent electrical failure can be reduced and the critical dimension of the memory device can be reduced.

(3) An isotropic etching is performed by the second etching step to form an enlarged bottom portion 150b. The enlarged bottom portion 150b can produce a doped region having a higher dopant concentration and a larger volume. Therefore, the word line isolation trench 150 can be made to have a better isolation effect.

(4) By using the first material layer 112 and the second material layer 114 as etching masks during the first and second etching processes, respectively, an etching mask and a patterning process can be omitted, thereby simplifying the process and reducing the process. cost.

In summary, the method for forming a self-aligned buried word line isolation structure provided by the present disclosure can effectively improve the critical size of the memory device, and can simplify the process and reduce the manufacturing cost.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

10‧‧‧Array area

20‧‧‧ peripheral circuit area

100‧‧‧Self-aligned buried word line isolation structure

102‧‧‧Semiconductor substrate

104‧‧‧Shallow trench isolation structure

108‧‧‧ character line

112‧‧‧First material layer

150‧‧‧word line isolation trench

150a‧‧‧ upper

150b‧‧‧ enlarged bottom

160‧‧‧Doped area

170‧‧‧Filling materials

C‧‧‧cell area

Claims (7)

A method for forming a self-aligned buried word line isolation structure includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a plurality of cell regions in the array region, wherein the cell regions Each of the plurality of word lines includes a first material layer on the semiconductor substrate, wherein the upper surface of the first material layer has a recess between two adjacent unit cells; Forming a second material layer on the first material layer and filling the recess, wherein the second material layer at the bottom of the recess has a first thickness, and the second material is located in the unit cell regions The layer has a second thickness greater than the first thickness; a first etching step is performed along the recess through the first material layer and the second material layer to form a word line isolation in the semiconductor substrate The trench is interposed between two adjacent ones of the unit cells, wherein the first etching step etches the first material layer more than the etching rate of the second material layer, wherein the word line isolation trench The position of the slot corresponds to the position of the recess; And performing a second etching step, the word line to expand the bottom of the isolation trenches, wherein the word line isolation trenches having an upper and a widened bottom. The method for forming a self-aligned buried word line isolation structure according to claim 1, wherein the forming the first material layer comprises: forming a first material gate film layer on the semiconductor substrate Wherein the first material gate film layer has a plurality of protrusions corresponding to positions of the word lines; Depositing a first material on the first material gate film layer to form the first material layer having the recess. The method for forming a self-aligned buried word line isolation structure according to claim 2, wherein the first material is a nitride and the second material is an oxide. The method for forming a self-aligned buried word line isolation structure according to claim 1, wherein the first etching step is an anisotropic etching step, and the second etching step is an isotropic Sex etching step. The method for forming a self-aligned buried word line isolation structure according to claim 1, further comprising: after performing the second etching step, performing a doping step to form a doped region And surrounding the enlarged bottom portion in the semiconductor substrate; and after performing the doping step, filling a filling material in the word line isolation trench. The method for forming a self-aligned buried word line isolation structure according to claim 1, wherein the top of the notch has a first aperture before the second material layer is formed, and the notch The bottom has a second aperture greater than the first aperture. The method for forming a self-aligned buried word line isolation structure according to claim 1, wherein after the second material layer is filled in the recess, the bottom of the recess is completely affected by the second material. Covered by layers.