TW243542B - - Google Patents

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Publication number
TW243542B
TW243542B TW082100237A TW82100237A TW243542B TW 243542 B TW243542 B TW 243542B TW 082100237 A TW082100237 A TW 082100237A TW 82100237 A TW82100237 A TW 82100237A TW 243542 B TW243542 B TW 243542B
Authority
TW
Taiwan
Application number
TW082100237A
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW243542B publication Critical patent/TW243542B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865Selective removal of parts of the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844Bottomless liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76858After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882Reflowing or applying of pressure to better fill the contact hole
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
TW082100237A 1992-01-23 1993-01-15 TW243542B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920000904A KR960001601B1 (ko) 1992-01-23 1992-01-23 반도체 장치의 접촉구 매몰방법 및 구조

Publications (1)

Publication Number Publication Date
TW243542B true TW243542B (zh) 1995-03-21

Family

ID=19328196

Family Applications (1)

Application Number Title Priority Date Filing Date
TW082100237A TW243542B (zh) 1992-01-23 1993-01-15

Country Status (6)

Country Link
US (3) US5534463A (zh)
EP (1) EP0552968B1 (zh)
JP (1) JP2545184B2 (zh)
KR (1) KR960001601B1 (zh)
DE (1) DE69322180T2 (zh)
TW (1) TW243542B (zh)

Families Citing this family (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960001601B1 (ko) * 1992-01-23 1996-02-02 삼성전자주식회사 반도체 장치의 접촉구 매몰방법 및 구조
GB2307345A (en) * 1993-03-02 1997-05-21 Samsung Electronics Co Ltd Semiconductor device contact structure
DE19515564B4 (de) * 1994-04-28 2008-07-03 Denso Corp., Kariya Elektrode für ein Halbleiterbauelement und Verfahren zur Herstellung derselben
JP3104534B2 (ja) * 1994-06-27 2000-10-30 ヤマハ株式会社 半導体装置とその製法
DE69529775T2 (de) * 1994-08-05 2003-10-16 Ibm Verfahren zur Herstellung einer Damaszenstruktur mit einer WGe Polierstoppschicht
JP3599199B2 (ja) * 1994-08-31 2004-12-08 富士通株式会社 多層配線を有する半導体装置の製造方法
KR0171069B1 (ko) * 1994-10-27 1999-03-30 문정환 반도체 장치의 접촉부 형성방법
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
US5738917A (en) * 1995-02-24 1998-04-14 Advanced Micro Devices, Inc. Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer
US5527736A (en) * 1995-04-03 1996-06-18 Taiwan Semiconductor Manufacturing Co. Dimple-free tungsten etching back process
KR0179827B1 (ko) * 1995-05-27 1999-04-15 문정환 반도체 소자의 배선 형성방법
US5770519A (en) * 1995-06-05 1998-06-23 Advanced Micro Devices, Inc. Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device
US6239029B1 (en) 1995-07-17 2001-05-29 Micron Technology, Inc. Sacrificial germanium layer for formation of a contact
US5644166A (en) 1995-07-17 1997-07-01 Micron Technology, Inc. Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts
KR0161422B1 (ko) * 1995-07-31 1999-02-01 김광호 접촉창을 용이하게 매몰한 반도체 장치 및 그 제조 방법
US5962923A (en) * 1995-08-07 1999-10-05 Applied Materials, Inc. Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches
US5641992A (en) * 1995-08-10 1997-06-24 Siemens Components, Inc. Metal interconnect structure for an integrated circuit with improved electromigration reliability
US6225218B1 (en) 1995-12-20 2001-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
US6225222B1 (en) * 1995-12-29 2001-05-01 United Microelectronics Corporation Diffusion barrier enhancement for sub-micron aluminum-silicon contacts
US6420786B1 (en) 1996-02-02 2002-07-16 Micron Technology, Inc. Conductive spacer in a via
US5700718A (en) * 1996-02-05 1997-12-23 Micron Technology, Inc. Method for increased metal interconnect reliability in situ formation of titanium aluminide
JP2891161B2 (ja) * 1996-02-15 1999-05-17 日本電気株式会社 配線形成方法
US5918149A (en) * 1996-02-16 1999-06-29 Advanced Micro Devices, Inc. Deposition of a conductor in a via hole or trench
FR2747511B1 (fr) 1996-04-10 1998-09-04 Sgs Thomson Microelectronics Interconnexions multicouches a faible capacite parasite laterale
US5789317A (en) 1996-04-12 1998-08-04 Micron Technology, Inc. Low temperature reflow method for filling high aspect ratio contacts
US5756396A (en) * 1996-05-06 1998-05-26 Taiwan Semiconductor Manufacturing Company Ltd Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect
US5641710A (en) * 1996-06-10 1997-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Post tungsten etch back anneal, to improve aluminum step coverage
KR100223332B1 (ko) * 1996-06-17 1999-10-15 김영환 반도체 소자의 금속배선 및 그 형성방법
US6331482B1 (en) * 1996-06-26 2001-12-18 Micron Technology, Inc. Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization
KR100203905B1 (ko) * 1996-06-27 1999-06-15 김영환 금속배선 제조방법
KR100193897B1 (ko) * 1996-06-28 1999-06-15 김영환 반도체 소자의 플러그 형성 방법
US5990507A (en) * 1996-07-09 1999-11-23 Kabushiki Kaisha Toshiba Semiconductor device having ferroelectric capacitor structures
JPH1027797A (ja) * 1996-07-10 1998-01-27 Oki Electric Ind Co Ltd Al/Ti積層配線およびその形成方法
US6005277A (en) * 1996-07-15 1999-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. ARC layer enhancement for reducing metal loss during via etch
US5926736A (en) * 1996-10-30 1999-07-20 Stmicroelectronics, Inc. Low temperature aluminum reflow for multilevel metallization
JP3725266B2 (ja) 1996-11-07 2005-12-07 株式会社半導体エネルギー研究所 配線形成方法
US5963828A (en) * 1996-12-23 1999-10-05 Lsi Logic Corporation Method for tungsten nucleation from WF6 using titanium as a reducing agent
US6071810A (en) * 1996-12-24 2000-06-06 Kabushiki Kaisha Toshiba Method of filling contact holes and wiring grooves of a semiconductor device
KR100431708B1 (ko) * 1996-12-27 2004-09-01 주식회사 하이닉스반도체 반도체장치제조방법
KR100295568B1 (ko) * 1997-02-03 2001-09-07 니시무로 타이죠 반도체 장치 및 그의 제조방법
US6143645A (en) * 1997-02-03 2000-11-07 Texas Instruments Incorporated Reduced temperature contact/via filling
US20040222525A1 (en) * 1997-03-14 2004-11-11 Rhodes Howard E. Advanced VLSI metallization
US5913146A (en) * 1997-03-18 1999-06-15 Lucent Technologies Inc. Semiconductor device having aluminum contacts or vias and method of manufacture therefor
KR100265993B1 (ko) * 1997-04-02 2000-10-02 김영환 반도체장치의 금속배선층 형성방법
US5998296A (en) * 1997-04-16 1999-12-07 Texas Instruments Incorporated Method of forming contacts and vias in semiconductor
US6395629B1 (en) * 1997-04-16 2002-05-28 Stmicroelectronics, Inc. Interconnect method and structure for semiconductor devices
US6171957B1 (en) * 1997-07-16 2001-01-09 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of semiconductor device having high pressure reflow process
JPH1174480A (ja) * 1997-08-29 1999-03-16 Oki Electric Ind Co Ltd 半導体メモリ及びその製造方法
US6091148A (en) * 1997-09-10 2000-07-18 Micron Technology Inc Electrical connection for a semiconductor structure
US5989984A (en) * 1997-10-07 1999-11-23 Lucent Technologies, Inc. Method of using getter layer to improve metal to metal contact resistance at low radio frequency power
US7253109B2 (en) 1997-11-26 2007-08-07 Applied Materials, Inc. Method of depositing a tantalum nitride/tantalum diffusion barrier layer system
KR20010032498A (ko) 1997-11-26 2001-04-25 조셉 제이. 스위니 손상없는 스컵쳐 코팅 증착
US6365514B1 (en) * 1997-12-23 2002-04-02 Intel Corporation Two chamber metal reflow process
US5994221A (en) * 1998-01-30 1999-11-30 Lucent Technologies Inc. Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects
US6376369B1 (en) 1998-02-12 2002-04-23 Micron Technology, Inc. Robust pressure aluminum fill process
KR100292940B1 (ko) * 1998-03-30 2001-07-12 윤종용 디램 셀 캐패시터의 제조 방법
KR100303059B1 (ko) * 1998-03-30 2001-11-30 윤종용 디램셀커패시터의제조방법
US6140236A (en) * 1998-04-21 2000-10-31 Kabushiki Kaisha Toshiba High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring
JP2956693B1 (ja) * 1998-05-27 1999-10-04 日本電気株式会社 金属窒化膜形成方法
JP4307592B2 (ja) * 1998-07-07 2009-08-05 Okiセミコンダクタ株式会社 半導体素子における配線形成方法
US6140217A (en) 1998-07-16 2000-10-31 International Business Machines Corporation Technique for extending the limits of photolithography
US6124205A (en) 1998-09-03 2000-09-26 Micron Technology, Inc. Contact/via force fill process
US6949464B1 (en) 1998-09-03 2005-09-27 Micron Technology, Inc. Contact/via force fill techniques
JP2000223527A (ja) * 1999-01-28 2000-08-11 Mitsubishi Electric Corp 半導体装置
US6319825B1 (en) * 1999-05-12 2001-11-20 Dongbu Electronics Co., Ltd. Metallization process of semiconductor device
JP2001060590A (ja) 1999-08-20 2001-03-06 Denso Corp 半導体装置の電気配線及びその製造方法
US7071557B2 (en) 1999-09-01 2006-07-04 Micron Technology, Inc. Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same
JP4190118B2 (ja) * 1999-12-17 2008-12-03 三菱電機株式会社 半導体装置、液晶表示装置および半導体装置の製造方法
FR2805084B1 (fr) 2000-02-14 2003-09-26 St Microelectronics Sa Procede de fabrication de pistes metalliques pour des circuits integres
US6335261B1 (en) 2000-05-31 2002-01-01 International Business Machines Corporation Directional CVD process with optimized etchback
KR100382730B1 (ko) * 2000-12-14 2003-05-09 삼성전자주식회사 반도체 소자의 금속 컨택 구조체 및 그 형성방법
KR100399417B1 (ko) * 2001-01-08 2003-09-26 삼성전자주식회사 반도체 집적 회로의 제조 방법
US6476498B1 (en) * 2001-07-13 2002-11-05 Advanced Micro Devices, Inc. Elimination of flux divergence in integrated circuit interconnects
US7067440B1 (en) 2001-08-24 2006-06-27 Novellus Systems, Inc. Gap fill for high aspect ratio structures
JP2003115535A (ja) * 2001-10-04 2003-04-18 Hitachi Ltd 半導体集積回路装置
US6746950B2 (en) 2001-11-14 2004-06-08 Vitesse Semiconductor Corporation Low temperature aluminum planarization process
US6794290B1 (en) 2001-12-03 2004-09-21 Novellus Systems, Inc. Method of chemical modification of structure topography
US6943105B2 (en) * 2002-01-18 2005-09-13 International Business Machines Corporation Soft metal conductor and method of making
JP3643116B2 (ja) * 2002-06-28 2005-04-27 住友精密工業株式会社 可動電気回路用導電膜および振動式ジャイロ
US7122485B1 (en) 2002-12-09 2006-10-17 Novellus Systems, Inc. Deposition profile modification through process chemistry
US7211502B2 (en) * 2003-03-26 2007-05-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20100072622A1 (en) * 2003-06-16 2010-03-25 United Microelectronics Corporation Method for forming Barrier Layer and the Related Damascene Structure
JP2005026641A (ja) * 2003-07-04 2005-01-27 Nec Electronics Corp 半導体装置およびその製造方法
US7078312B1 (en) 2003-09-02 2006-07-18 Novellus Systems, Inc. Method for controlling etch process repeatability
US20050112957A1 (en) * 2003-11-26 2005-05-26 International Business Machines Corporation Partial inter-locking metal contact structure for semiconductor devices and method of manufacture
US7163896B1 (en) 2003-12-10 2007-01-16 Novellus Systems, Inc. Biased H2 etch process in deposition-etch-deposition gap fill
US7476621B1 (en) 2003-12-10 2009-01-13 Novellus Systems, Inc. Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill
US7344996B1 (en) 2005-06-22 2008-03-18 Novellus Systems, Inc. Helium-based etch process in deposition-etch-deposition gap fill
US7217658B1 (en) 2004-09-07 2007-05-15 Novellus Systems, Inc. Process modulation to prevent structure erosion during gap fill
US7176039B1 (en) 2004-09-21 2007-02-13 Novellus Systems, Inc. Dynamic modification of gap fill process characteristics
US7381451B1 (en) 2004-11-17 2008-06-03 Novellus Systems, Inc. Strain engineering—HDP thin film with tensile stress for FEOL and other applications
US7211525B1 (en) 2005-03-16 2007-05-01 Novellus Systems, Inc. Hydrogen treatment enhanced gap fill
JP4694281B2 (ja) 2005-06-23 2011-06-08 レンゴー株式会社 版締め装置
US20070243708A1 (en) * 2006-04-12 2007-10-18 Jens Hahn Manufacturing method for an integrated semiconductor contact structure having an improved aluminum fill
US7482245B1 (en) 2006-06-20 2009-01-27 Novellus Systems, Inc. Stress profile modulation in STI gap fill
US8030215B1 (en) * 2008-02-19 2011-10-04 Marvell International Ltd. Method for creating ultra-high-density holes and metallization
US8133797B2 (en) * 2008-05-16 2012-03-13 Novellus Systems, Inc. Protective layer to enable damage free gap fill
KR20100053063A (ko) * 2008-11-12 2010-05-20 주식회사 동부하이텍 이미지센서의 제조방법
US8089144B2 (en) 2008-12-17 2012-01-03 Denso Corporation Semiconductor device and method for manufacturing the same
KR101461633B1 (ko) * 2008-12-26 2014-11-13 삼성전자주식회사 이미지 센서 및 그의 제조방법
US20190140167A1 (en) * 2017-11-07 2019-05-09 Everspin Technologies, Inc. Angled surface removal process and structure relating thereto
US10964590B2 (en) * 2017-11-15 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Contact metallization process
CN113316840A (zh) * 2019-03-28 2021-08-27 东京毅力科创株式会社 半导体装置的制造方法

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893255A (ja) * 1981-11-30 1983-06-02 Toshiba Corp 半導体装置の製造方法
US4507853A (en) * 1982-08-23 1985-04-02 Texas Instruments Incorporated Metallization process for integrated circuits
JPS59171374A (ja) * 1983-03-18 1984-09-27 Hitachi Denshi Ltd テレビ放送システム
US4720908A (en) * 1984-07-11 1988-01-26 Texas Instruments Incorporated Process for making contacts and interconnects for holes having vertical sidewalls
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
US4589196A (en) * 1984-10-11 1986-05-20 Texas Instruments Incorporated Contacts for VLSI devices using direct-reacted silicide
JPS61183942A (ja) * 1985-02-08 1986-08-16 Fujitsu Ltd 半導体装置の製造方法
US4630357A (en) * 1985-08-02 1986-12-23 Ncr Corporation Method for forming improved contacts between interconnect layers of an integrated circuit
JPS62109341A (ja) * 1985-11-07 1987-05-20 Mitsubishi Electric Corp 半導体装置の製造方法
JPS62111421A (ja) * 1985-11-09 1987-05-22 Mitsubishi Electric Corp 金属シリサイド膜組成比制御方法
JPS62132348A (ja) * 1985-12-04 1987-06-15 Sony Corp 半導体装置の製造方法
JPS62211915A (ja) * 1986-03-12 1987-09-17 Nec Corp 導電薄膜の堆積法
JPS62274640A (ja) * 1986-05-22 1987-11-28 Fuji Xerox Co Ltd 半導体装置およびその製造方法
EP0252742B1 (en) * 1986-07-11 1991-10-02 Mobil Oil Corporation Process for conversion of lower aliphatic oxygenates to olefins and aromatics with gallium containing zsm-5 catalyst
JPS6373660A (ja) * 1986-09-17 1988-04-04 Fujitsu Ltd 半導体装置
JPS6399546A (ja) * 1986-10-16 1988-04-30 Hitachi Ltd 半導体装置の製造方法
JPS63162854A (ja) * 1986-12-25 1988-07-06 Fujitsu Ltd 金属膜形成方法
US4753709A (en) * 1987-02-05 1988-06-28 Texas Instuments Incorporated Method for etching contact vias in a semiconductor device
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
JPH0622235B2 (ja) * 1987-05-21 1994-03-23 日本電気株式会社 半導体装置の製造方法
US4910580A (en) * 1987-08-27 1990-03-20 Siemens Aktiengesellschaft Method for manufacturing a low-impedance, planar metallization composed of aluminum or of an aluminum alloy
JPH0719841B2 (ja) * 1987-10-02 1995-03-06 株式会社東芝 半導体装置
US4963511A (en) * 1987-11-30 1990-10-16 Texas Instruments Incorporated Method of reducing tungsten selectivity to a contact sidewall
US4872050A (en) * 1988-03-15 1989-10-03 Mitsubishi Denki Kabushiki Kaisha Interconnection structure in semiconductor device and manufacturing method of the same
JPH01246831A (ja) * 1988-03-29 1989-10-02 Seiko Epson Corp 多層電極配線法
JP2751223B2 (ja) * 1988-07-14 1998-05-18 セイコーエプソン株式会社 半導体装置およびその製造方法
JP3028519B2 (ja) * 1988-10-25 2000-04-04 日本電気株式会社 半導体集積回路の製造方法
JP2701239B2 (ja) * 1989-01-11 1998-01-21 ローム 株式会社 半導体装置の製造方法
US4938079A (en) * 1989-03-06 1990-07-03 Ivac Corporation Thermal transit time flow measurement system
JPH0727879B2 (ja) * 1989-03-14 1995-03-29 株式会社東芝 半導体装置の製造方法
JP2537413B2 (ja) * 1989-03-14 1996-09-25 三菱電機株式会社 半導体装置およびその製造方法
JPH036827A (ja) * 1989-06-05 1991-01-14 Sharp Corp 半導体装置の製造方法
US4970176A (en) * 1989-09-29 1990-11-13 Motorola, Inc. Multiple step metallization process
DE69031903T2 (de) * 1989-11-30 1998-04-16 Sgs Thomson Microelectronics Verfahren zum Herstellen von Zwischenschicht-Kontakten
JPH03257926A (ja) * 1990-03-08 1991-11-18 Matsushita Electron Corp 半導体装置の製造方法
KR960001601B1 (ko) * 1992-01-23 1996-02-02 삼성전자주식회사 반도체 장치의 접촉구 매몰방법 및 구조
US5136362A (en) * 1990-11-27 1992-08-04 Grief Malcolm K Electrical contact with diffusion barrier
DE4200809C2 (de) * 1991-03-20 1996-12-12 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement
JP2811131B2 (ja) * 1991-04-26 1998-10-15 三菱電機株式会社 半導体装置の配線接続構造およびその製造方法
TW520072U (en) * 1991-07-08 2003-02-01 Samsung Electronics Co Ltd A semiconductor device having a multi-layer metal contact
JPH05160067A (ja) * 1991-07-23 1993-06-25 Seiko Epson Corp 半導体装置およびその製造方法
US5254873A (en) * 1991-12-09 1993-10-19 Motorola, Inc. Trench structure having a germanium silicate region
KR930020669A (ko) * 1992-03-04 1993-10-20 김광호 고집적 반도체장치 및 그 제조방법
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
US5213989A (en) * 1992-06-24 1993-05-25 Motorola, Inc. Method for forming a grown bipolar electrode contact using a sidewall seed
US5262352A (en) * 1992-08-31 1993-11-16 Motorola, Inc. Method for forming an interconnection structure for conductive layers
JPH0915277A (ja) * 1995-04-24 1997-01-17 Matsushita Electric Ind Co Ltd インピーダンス演算方法及びインピーダンス演算装置

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EP0552968A2 (en) 1993-07-28
KR930017100A (ko) 1993-08-30
JPH0684911A (ja) 1994-03-25
US5534463A (en) 1996-07-09
DE69322180D1 (de) 1999-01-07
DE69322180T2 (de) 1999-06-24
US5589713A (en) 1996-12-31
KR960001601B1 (ko) 1996-02-02
EP0552968B1 (en) 1998-11-25
JP2545184B2 (ja) 1996-10-16
US5869902A (en) 1999-02-09
EP0552968A3 (en) 1993-09-29

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