KR930020669A - 고집적 반도체장치 및 그 제조방법 - Google Patents

고집적 반도체장치 및 그 제조방법 Download PDF

Info

Publication number
KR930020669A
KR930020669A KR1019920003559A KR920003559A KR930020669A KR 930020669 A KR930020669 A KR 930020669A KR 1019920003559 A KR1019920003559 A KR 1019920003559A KR 920003559 A KR920003559 A KR 920003559A KR 930020669 A KR930020669 A KR 930020669A
Authority
KR
South Korea
Prior art keywords
conductive layer
semiconductor device
forming
insulating film
interlayer insulating
Prior art date
Application number
KR1019920003559A
Other languages
English (en)
Inventor
신윤승
장성남
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920003559A priority Critical patent/KR930020669A/ko
Priority to JP4116332A priority patent/JPH0645329A/ja
Publication of KR930020669A publication Critical patent/KR930020669A/ko
Priority to US08/188,113 priority patent/US5414302A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 고집적 반도체메모리장치 및 그 제조방법에 관한 것으로, 특히 셀프얼라인 콘택구조를 가진 고집적 반도체메모리장치 및 그 제조방법에 관한 것이다.
본 발명에 의하면, 하부도전층과 상부도전층의 전기적접속을 위한 접속구조를 포함하는 반도체장치에 있어서, 상기 하부도전층과 상부도전층 사이에 잡속구조 형성을 위한 비아를 포함하는 층간절연막이 형성되어 있고, 상기 접속구조는 상기 비아의 내면에 하부도전층과 전기적으로 접촉하고 상기 비아주위의 층간절연막상의 소정영역상에 형성된 제1도전층, 상기 제1도전층상에 형성된 상기 비아에 매립된 평탄화물질, 상기 편탄화물질과 노출된 제1도전층상에 형성된 제2도전층으로 구성된 콘택패드를 포함함을 특징으로 하는 반도체장치가 제공되며, 이들 형성하기 위한 제조방법으로서 반도체기판상에 접속구조형성을 위한 비아를 포함하는 층간절연막을 형성하고, 상기 비아의 내면 및 상기 비아주위의 층간절연막의 소정부분상에 제1도전층을 형성하고, 상기 비아를 층간평탄화물질로 매립하고 상기 평탄화물질 및 상기 노출된 제1도전층 상에 제2도전층을 형성함을 특징으로 하는 반도체장치의 제조방법이 제공된다. 따라서 본 발명에 의하면, 콘택패드 상부면이 평탄화되어 있으므로 후속공정에 의한 상부도전층과의 전기적 접속이 용이해지며, 셀프얼라인 콘택을 오픈한 후 콘택패드를 형성하기 위한 제2도전층을 얇게 침적하고 패터닝한 후 에칭한 다음 BPSG로 된 절연막에 의해 제2도전칭이 움푹 패인 골 부분을 평탄화 시키고 나서 제3도전층을 제2도전칭과 연결되도록 형성함으로써 제2도전층의 움푹 패인 골 부분에 스트링거등의 잔유물이 남지 않게 됨에 따라 디바이스 제조에 적용했을때 신뢰성을 향상된다.

Description

고집적 반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 고집적 반도체메모리장치를 나타낸 단면도이다.
제3a도 내지 제3f도는 본 발명의 고집적 반도체 장치의 제조방법을 나타낸 공정순서도이다.

Claims (18)

  1. 하부도전층과 상부도전층의 전기적 접속을 위한 접속구조를 포함하는 반도체장치에 있어서, 상기 하부도전층과 상부도전층상이에 접속구조 형성을 위한 비아를 포함하는 층간절연막이 형성되어 있고, 상기 접속구조는 상기 비아의 내면에 하부도전층과 전기적으로 접속하고 상기 비아주위의 층간절연막상의 소정영역상에 형성된 제1도전층, 상기 제1도전층상에 형성된 상기 비아에 매립된 평탄화물질, 상기 평탄화물질과 노출된 제1도전층상에 형성된 제2도전층으로 구성된 콘택패드를 포함함을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 비아의 하부주위에는 게이트측벽스페이서가 형성되어 있고, 상기 비아의 상부내면은 층간절연막의 측벽임을 특징으로 하는 반도체장치.
  3. 제1항에 있어서, 상기 제1도전층은 폴리실리콘을 얇게 증착하여 형성함을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 상기 평탄화물질은 BPSG임을 특징으로 하는 반도체장치.
  5. 제1항에 있어서, 상기 제2도전층은 폴리실리콘으로 형성함을 특징으로 하는 반도체장치.
  6. 제1항에 있어서, 상기 제2도전층은 폴리실리콘과 고융점금속 화합물로 이루어짐을 특징으로 하는 반도체장치.
  7. 제6항에 있어서, 상기 고융점금속화합물은 WSi₂임을 특징으로 하는 반도체장치.
  8. 제1항에 있어서, 사익 접속구조는 셀프얼라인 접속구조임을 특징으로 하는 반도체장치.
  9. 제1항에 있어서, SRAM임을 특징으로 하는 반도체장치.
  10. 반도체기판상에 접속구조형성을 위한 비아를 포함하는 층간절연막을 형성하고, 상기 비아의 내면 및 상기 비아주위의 층간절연막의 소정부분상에 제1도전층을 형성하고, 상기 비아를 층간평탄화물질로 매립하고 상기 평탄화물질 및 상기 노출된 제1도전층상에 제2도전층을 형성함을 특징으로 하는 반도체장치의 제조방법.
  11. 제10항에 있어서, 상기 접속구조 형상을 위한 비아를 포함하는 층간절연막을 형성하는 공정은 MOS 트랜지스터가 형성되어 있는 반도체기판상에 층간절연막을 형성하고 사진공정에 의해 상기 층간절연막에 개구를 형성하는 공정임을 특징으로 하는 반도체장치.
  12. 제10항에 있어서, 상기 제1도전층을 형성하는 공정은 상기 층간절연막이 형성된 반도체기판상에 제1도전층을 얇게 침적한 후, 사진공정에 의해 콘택패드패턴으로 패터닝하는 공정임을 특징으로 하는 반도체장치.
  13. 제10항에 있어서, 상기 층간평탄화물질을 매립하는 공정은 상기 제1도전층이 형성된 반도체기판 전면에 층간평탄화물질을 침적하고 리플로우한 후 상기 제1도전층의 상부가 노출될 때까지 에치백하는 공정임을 특징으로 하는 반도체장치.
  14. 제10항에 있어서, 상기 제2도전층을 형성하는 공정은 상기 노출된 제1도전층 및 층간평탄화물질상에 제2도전층을 침적한 다음 사진공중에 의해 콘택패드패턴으로 패터닝하는 공정임을 특징으로 하는 반도체장치.
  15. 제10항에 있어서, 상기 제1도전층은 폴리실리콘으로 형성함을 특징으로 하는 반도체장치.
  16. 제10항에 있어서, 상기 층간평탄화물질은 BPSG임을 특징으로 하는 반도체장치.
  17. 제10항에 있어서, 상기 제2도전층은 폴리실리콘과 고융점금속으로 이루어짐을 특징으로 하는 반도체장치.
  18. 제10항에 있어서, 상기 제1도전층 및 제2도전층의 사진공정에 의한 콘택패드패턴으로의 패턴닝시 동일한 마스크를 사용함을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920003559A 1992-03-04 1992-03-04 고집적 반도체장치 및 그 제조방법 KR930020669A (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920003559A KR930020669A (ko) 1992-03-04 1992-03-04 고집적 반도체장치 및 그 제조방법
JP4116332A JPH0645329A (ja) 1992-03-04 1992-05-08 高集積半導体装置およびその製造方法
US08/188,113 US5414302A (en) 1992-03-04 1994-01-28 Semiconductor device with a multilayered contact structure having a boro-phosphate silicate glass planarizing layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920003559A KR930020669A (ko) 1992-03-04 1992-03-04 고집적 반도체장치 및 그 제조방법

Publications (1)

Publication Number Publication Date
KR930020669A true KR930020669A (ko) 1993-10-20

Family

ID=19329945

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920003559A KR930020669A (ko) 1992-03-04 1992-03-04 고집적 반도체장치 및 그 제조방법

Country Status (3)

Country Link
US (1) US5414302A (ko)
JP (1) JPH0645329A (ko)
KR (1) KR930020669A (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100265848B1 (ko) * 1997-06-30 2000-10-02 김영환 반도체장치의전하저장전극형성방법
CN108573972A (zh) * 2017-03-09 2018-09-25 三星电子株式会社 三维半导体器件及其形成方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388075B1 (en) * 1989-03-16 1996-11-06 STMicroelectronics, Inc. Contacts for semiconductor devices
KR960001601B1 (ko) * 1992-01-23 1996-02-02 삼성전자주식회사 반도체 장치의 접촉구 매몰방법 및 구조
US5563089A (en) * 1994-07-20 1996-10-08 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
JP3256048B2 (ja) * 1993-09-20 2002-02-12 富士通株式会社 半導体装置及びその製造方法
JP2947054B2 (ja) * 1994-03-04 1999-09-13 ヤマハ株式会社 配線形成法
US5956615A (en) * 1994-05-31 1999-09-21 Stmicroelectronics, Inc. Method of forming a metal contact to landing pad structure in an integrated circuit
US5945738A (en) * 1994-05-31 1999-08-31 Stmicroelectronics, Inc. Dual landing pad structure in an integrated circuit
US5702979A (en) * 1994-05-31 1997-12-30 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5795208A (en) * 1994-10-11 1998-08-18 Yamaha Corporation Manufacture of electron emitter by replica technique
KR0161731B1 (ko) * 1994-10-28 1999-02-01 김주용 반도체소자의 미세콘택 형성방법
JP4156044B2 (ja) * 1994-12-22 2008-09-24 エスティーマイクロエレクトロニクス，インコーポレイテッド 集積回路におけるランディングパッド構成体の製造方法
US5705427A (en) * 1994-12-22 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5534451A (en) * 1995-04-27 1996-07-09 Taiwan Semiconductor Manufacturing Company Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance
US5744866A (en) * 1997-03-11 1998-04-28 Nec Corporation Low resistance ground wiring in a semiconductor device
KR100198634B1 (ko) * 1996-09-07 1999-06-15 구본준 반도체 소자의 배선구조 및 제조방법
US5827762A (en) * 1997-05-02 1998-10-27 National Semiconductor Corporation Method for forming buried interconnect structue having stability at high temperatures
JPH11260937A (ja) 1998-03-13 1999-09-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100426811B1 (ko) * 2001-07-12 2004-04-08 삼성전자주식회사 셀프얼라인 콘택을 갖는 반도체 소자 및 그의 제조방법
US6590295B1 (en) * 2002-06-11 2003-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic device with a spacer redistribution layer via and method of making the same
JP4755400B2 (ja) * 2003-08-29 2011-08-24 株式会社リコー 無端移動部材駆動装置と画像形成装置と感光体駆動装置と無端移動部材の劣化警告方法
KR100761354B1 (ko) * 2006-10-02 2007-09-27 주식회사 하이닉스반도체 다면채널을 갖는 반도체소자의 듀얼폴리게이트 및 그의형성 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199369A (ja) * 1984-10-22 1986-05-17 Fuji Photo Film Co Ltd 固体撮像素子
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
JPH06105772B2 (ja) * 1987-07-28 1994-12-21 株式会社東芝 半導体装置の製造方法
JPH0227717A (ja) * 1988-07-15 1990-01-30 Toshiba Corp 半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100265848B1 (ko) * 1997-06-30 2000-10-02 김영환 반도체장치의전하저장전극형성방법
CN108573972A (zh) * 2017-03-09 2018-09-25 三星电子株式会社 三维半导体器件及其形成方法
CN108573972B (zh) * 2017-03-09 2024-04-09 三星电子株式会社 三维半导体器件及其形成方法

Also Published As

Publication number Publication date
US5414302A (en) 1995-05-09
JPH0645329A (ja) 1994-02-18

Similar Documents

Publication Publication Date Title
KR930020669A (ko) 고집적 반도체장치 및 그 제조방법
US5091768A (en) Semiconductor device having a funnel shaped inter-level connection
JPH04174541A (ja) 半導体集積回路及びその製造方法
KR890017734A (ko) 금속판 캐패시터 및 이의 제조방법
US6184127B1 (en) Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure
US6008114A (en) Method of forming dual damascene structure
JP3123092B2 (ja) 半導体装置の製造方法
KR950012918B1 (ko) 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법
KR960026644A (ko) 반도체 장치의 배선구조 및 그의 제조방법
JP3321864B2 (ja) 半導体装置とその製法
US5589418A (en) Method of forming a polysilicon buried contact
KR970013369A (ko) 반도체집적회로장치의 제조방법 및 반도체집적회로장치
KR950015589A (ko) 반도체 장치의 금속배선시 콘택홀 형성방법
JP2867555B2 (ja) 半導体装置の製造方法
KR950011982B1 (ko) 전도물질 패드를 갖는 반도체 접속장치 및 그 제조방법
KR100214556B1 (ko) 다층구조 모스 트랜지스터 제조방법
KR100230735B1 (ko) 반도체 소자의 제조방법
JPH11111921A (ja) 半導体装置
KR100315457B1 (ko) 반도체 소자의 제조 방법
KR100252883B1 (ko) 반도체소자의 콘택홀 매립방법
JPH02126684A (ja) 半導体装置の製造方法
KR940016877A (ko) 고집적 반도체 접속장치 제조방법
JPS59125661A (ja) 好ましい電極構造を有する半導体装置およびその製造方法
KR20060000597A (ko) 반도체 소자의 콘택 형성 방법
JP2000058640A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A201 Request for examination
WITB Written withdrawal of application