TW202318808A - Pll電路及發送系統 - Google Patents
Pll電路及發送系統 Download PDFInfo
- Publication number
- TW202318808A TW202318808A TW111131890A TW111131890A TW202318808A TW 202318808 A TW202318808 A TW 202318808A TW 111131890 A TW111131890 A TW 111131890A TW 111131890 A TW111131890 A TW 111131890A TW 202318808 A TW202318808 A TW 202318808A
- Authority
- TW
- Taiwan
- Prior art keywords
- clock signal
- signal
- aforementioned
- reference clock
- switching
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
- H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail by switching the reference signal of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/195—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021137169 | 2021-08-25 | ||
| JP2021-137169 | 2021-08-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW202318808A true TW202318808A (zh) | 2023-05-01 |
Family
ID=85322853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW111131890A TW202318808A (zh) | 2021-08-25 | 2022-08-24 | Pll電路及發送系統 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US12401367B2 (https=) |
| EP (1) | EP4395178A4 (https=) |
| JP (1) | JP7818608B2 (https=) |
| CN (1) | CN117837087A (https=) |
| TW (1) | TW202318808A (https=) |
| WO (1) | WO2023027078A1 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI869261B (zh) * | 2024-04-10 | 2025-01-01 | 新唐科技股份有限公司 | 降低電源訊號線雜訊對解碼影響的方法以及使用其之解碼電路 |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7818608B2 (ja) * | 2021-08-25 | 2026-02-20 | ヌヴォトンテクノロジージャパン株式会社 | Pll回路および送信システム |
| US12542547B2 (en) * | 2024-02-26 | 2026-02-03 | International Business Machines Corporation | Reducing the time to switch between the redundant clock signals applied to a phase lock loop |
| EP4629512A1 (en) * | 2024-04-02 | 2025-10-08 | Nxp B.V. | Phase-locked loop reference clock switching with controlled output transient frequency drift |
| CN118590041A (zh) * | 2024-06-20 | 2024-09-03 | 中国电子科技集团公司第十研究所 | 一种数字集成电路时钟复位系统 |
Family Cites Families (78)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SU1293841A1 (ru) * | 1984-10-09 | 1987-02-28 | Предприятие П/Я В-8574 | Синтезатор частот |
| DE3685616T2 (de) * | 1985-07-09 | 1993-02-04 | Nippon Electric Co | Phasenverriegelte taktregenerierschaltung fuer digitale uebertragungssysteme. |
| US4864253A (en) * | 1987-12-22 | 1989-09-05 | Siemens Aktiengesellschaft | Phase locked loop wherein phase comparing and filtering are performed by microprocessor |
| GB2223136B (en) * | 1988-03-28 | 1992-10-14 | Plessey Co Plc | Broad band vco control system for clock recovery |
| JP2589370B2 (ja) * | 1989-04-13 | 1997-03-12 | シャープ株式会社 | 光ディスク装置 |
| JPH0327620A (ja) * | 1989-06-23 | 1991-02-06 | Fujitsu Ltd | 基準信号の切替装置 |
| JPH06152581A (ja) * | 1992-11-10 | 1994-05-31 | Fujitsu Ltd | クロック供給装置 |
| JP3313175B2 (ja) * | 1993-02-19 | 2002-08-12 | 富士通株式会社 | ディスク装置のサーボ位置検出装置及びその方法 |
| US6269061B1 (en) * | 1993-10-07 | 2001-07-31 | Sony Corporation | Servo control system for disk player |
| CN1031846C (zh) * | 1993-11-20 | 1996-05-22 | 南京理工大学 | 基色灰度分级顺序寻址动态图像显示屏 |
| JPH0818447A (ja) * | 1994-06-28 | 1996-01-19 | Mitsubishi Electric Corp | Pll回路装置 |
| GB2293062B (en) * | 1994-09-09 | 1996-12-04 | Toshiba Kk | Master-slave multiplex communication system and PLL circuit applied to the system |
| JP2606670B2 (ja) * | 1994-09-29 | 1997-05-07 | 日本電気株式会社 | 光ディスク再生装置 |
| JP3260048B2 (ja) * | 1994-12-13 | 2002-02-25 | 株式会社東芝 | クロック信号発生回路及び半導体装置 |
| JPH08228149A (ja) * | 1995-02-22 | 1996-09-03 | Toshiba Corp | 位相同期ループ回路 |
| JPH0983396A (ja) * | 1995-09-07 | 1997-03-28 | Sony Corp | 受信機 |
| US6141769A (en) * | 1996-05-16 | 2000-10-31 | Resilience Corporation | Triple modular redundant computer system and associated method |
| JPH1013383A (ja) * | 1996-06-26 | 1998-01-16 | Matsushita Electric Ind Co Ltd | 光伝送システム |
| JPH1022822A (ja) * | 1996-07-05 | 1998-01-23 | Sony Corp | ディジタルpll回路 |
| JP3591754B2 (ja) * | 1997-03-19 | 2004-11-24 | パイオニア株式会社 | Pll回路 |
| US6341149B1 (en) * | 1997-06-27 | 2002-01-22 | International Business Machines Corporation | Clock control device for a non-disruptive backup clock switching |
| TW419901B (en) * | 1997-06-27 | 2001-01-21 | Hitachi Ltd | Phase-locked ring circuit, data processing device and data process system |
| US5907263A (en) * | 1997-11-14 | 1999-05-25 | Cirrus Logic, Inc. | Bias current calibration of voltage controlled oscillator |
| US6182236B1 (en) * | 1998-08-26 | 2001-01-30 | Compaq Computer Corporation | Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew |
| JP3085293B2 (ja) * | 1998-11-18 | 2000-09-04 | 日本電気株式会社 | データ伝送装置 |
| FR2793091B1 (fr) * | 1999-04-30 | 2001-06-08 | France Telecom | Dispositif d'asservissement de frequence |
| US6208183B1 (en) * | 1999-04-30 | 2001-03-27 | Conexant Systems, Inc. | Gated delay-locked loop for clock generation applications |
| JP2001094420A (ja) * | 1999-09-24 | 2001-04-06 | Fujitsu Ltd | 位相ロック・ループ回路 |
| US6259328B1 (en) * | 1999-12-17 | 2001-07-10 | Network Equipment Technologies, Inc. | Method and system for managing reference signals for network clock synchronization |
| US6362670B1 (en) * | 2000-08-04 | 2002-03-26 | Marconi Communications, Inc. | Controlled slew reference switch for a phase locked loop |
| US6307411B1 (en) * | 2000-10-13 | 2001-10-23 | Brookhaven Science Associates | Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems |
| JP3557612B2 (ja) * | 2000-12-05 | 2004-08-25 | 日本電気株式会社 | 低レーテンシ高速伝送システム |
| JP3655878B2 (ja) | 2002-02-18 | 2005-06-02 | 埼玉日本電気株式会社 | Pll回路 |
| JP2004015659A (ja) * | 2002-06-10 | 2004-01-15 | Mitsubishi Electric Corp | Pll制御装置 |
| JP2004037939A (ja) * | 2002-07-04 | 2004-02-05 | Pioneer Electronic Corp | 表示パネル駆動装置、表示制御装置、駆動装置およびデータ転送方式 |
| EP1376526A3 (en) * | 2002-06-26 | 2004-12-08 | Pioneer Corporation | Display panel drive device, data transfer system and data reception device |
| JP2004364366A (ja) * | 2003-06-02 | 2004-12-24 | Seiko Epson Corp | Pwm制御システム |
| GB0323936D0 (en) * | 2003-10-11 | 2003-11-12 | Zarlink Semiconductor Inc | Digital phase locked loop with selectable normal or fast-locking capability |
| JP2005252587A (ja) * | 2004-03-03 | 2005-09-15 | Seiko Epson Corp | クロック整形器およびクロック整形器を用いた電子機器 |
| JP2005277880A (ja) * | 2004-03-25 | 2005-10-06 | Seiko Epson Corp | クロック整形器およびこれを用いた電子機器 |
| JP4651348B2 (ja) * | 2004-09-30 | 2011-03-16 | 株式会社タムラ製作所 | デジタル音声調整装置 |
| JP2007049217A (ja) * | 2005-08-05 | 2007-02-22 | Matsushita Electric Ind Co Ltd | ネットワークシステム |
| JP2007266923A (ja) * | 2006-03-28 | 2007-10-11 | Fujitsu Ltd | クロック供給装置 |
| US7902886B2 (en) * | 2007-10-30 | 2011-03-08 | Diablo Technologies Inc. | Multiple reference phase locked loop |
| US7737739B1 (en) * | 2007-12-12 | 2010-06-15 | Integrated Device Technology, Inc. | Phase step clock generator |
| US8077822B2 (en) * | 2008-04-29 | 2011-12-13 | Qualcomm Incorporated | System and method of controlling power consumption in a digital phase locked loop (DPLL) |
| JP2011170644A (ja) * | 2010-02-19 | 2011-09-01 | Sony Corp | 通信装置、通信システムおよび通信方法 |
| JP5560833B2 (ja) * | 2010-03-29 | 2014-07-30 | 富士通株式会社 | 光インターフェイス装置および入力周波数偏差の異常監視方法 |
| US8222933B2 (en) * | 2010-05-07 | 2012-07-17 | Texas Instruments Incorporated | Low power digital phase lock loop circuit |
| US8395428B2 (en) * | 2010-09-30 | 2013-03-12 | St-Ericsson Sa | Reference clock sampling digital PLL |
| JP5711949B2 (ja) * | 2010-12-03 | 2015-05-07 | ローム株式会社 | シリアルデータの受信回路、受信方法およびそれらを用いたシリアルデータの伝送システム、伝送方法 |
| US20120166859A1 (en) * | 2010-12-22 | 2012-06-28 | Fernald Kenneth W | Method and apparatus for generating a system clock signal |
| WO2012150621A1 (ja) * | 2011-05-02 | 2012-11-08 | パナソニック株式会社 | 周波数シンセサイザ |
| US8842490B2 (en) * | 2012-06-29 | 2014-09-23 | Intel Corporation | Apparatus and method for selectively using a memory command clock as a reference clock |
| US9343126B2 (en) * | 2012-09-12 | 2016-05-17 | Intel Corporation | Frequency selection granularity for integrated circuits |
| JP2014158195A (ja) * | 2013-02-18 | 2014-08-28 | Renesas Electronics Corp | 無線通信システムおよび無線通信用半導体装置 |
| US9142272B2 (en) * | 2013-03-15 | 2015-09-22 | International Business Machines Corporation | Dual asynchronous and synchronous memory system |
| CN203387495U (zh) * | 2013-08-14 | 2014-01-08 | 江西航天海虹测控技术有限责任公司 | Pll电路参考时钟切换电路系统 |
| US9395745B2 (en) * | 2014-02-10 | 2016-07-19 | Analog Devices, Inc. | Redundant clock switchover |
| US9531390B1 (en) * | 2015-12-15 | 2016-12-27 | Altera Corporation | Techniques for generating clock signals using oscillators |
| US10523219B2 (en) * | 2016-03-04 | 2019-12-31 | Sony Corporation | Phase locked loop and control method therefor |
| JP2018011277A (ja) * | 2016-07-15 | 2018-01-18 | 富士通株式会社 | 伝送装置及びクロック制御方法 |
| CN109565277B (zh) * | 2016-08-30 | 2024-03-22 | 株式会社半导体能源研究所 | 接收差分信号的接收器、包括接收器的ic以及显示装置 |
| KR102757627B1 (ko) * | 2016-09-23 | 2025-01-23 | 삼성전자주식회사 | 케스-케이드 연결 구조로 레퍼런스 클록을 전달하는 스토리지 장치들을 포함하는 전자 장치 |
| CN110024288B (zh) * | 2016-11-28 | 2023-06-06 | 新唐科技日本株式会社 | 脉冲频率控制电路、微控制器、dcdc转换器及脉冲频率控制方法 |
| US10234895B2 (en) * | 2017-05-11 | 2019-03-19 | Microsemi Semiconductor Ulc | Clock synthesizer with hitless reference switching and frequency stabilization |
| US10516402B2 (en) * | 2018-03-09 | 2019-12-24 | Texas Instruments Incorporated | Corrupted clock detection circuit for a phase-locked loop |
| US10491222B2 (en) * | 2018-03-13 | 2019-11-26 | Texas Instruments Incorporated | Switch between input reference clocks of different frequencies in a phase locked loop (PLL) without phase impact |
| JP2019204998A (ja) * | 2018-05-21 | 2019-11-28 | 株式会社デンソー | Pll回路 |
| US11152947B2 (en) * | 2019-02-20 | 2021-10-19 | Renesas Electronics America Inc. | Feedback control for accurate signal generation |
| US10790838B1 (en) * | 2019-05-14 | 2020-09-29 | Intel Corporation | Method and apparatus to perform dynamic frequency scaling while a phase-locked loop operates in a closed loop |
| US10727845B1 (en) * | 2019-06-25 | 2020-07-28 | Silicon Laboratories Inc. | Use of a virtual clock in a PLL to maintain a closed loop system |
| JP7113788B2 (ja) * | 2019-07-01 | 2022-08-05 | 三菱電機株式会社 | 位相同期回路 |
| WO2021112000A1 (ja) * | 2019-12-05 | 2021-06-10 | ローム株式会社 | Pll回路およびその制御方法 |
| US11233518B2 (en) * | 2019-12-13 | 2022-01-25 | Samsung Electronics Co., Ltd. | Clock recovery circuit, clock data recovery circuit, and apparatus including the same |
| US11031945B1 (en) * | 2020-09-11 | 2021-06-08 | Apple Inc. | Time-to-digital converter circuit linearity test mechanism |
| JP7818608B2 (ja) * | 2021-08-25 | 2026-02-20 | ヌヴォトンテクノロジージャパン株式会社 | Pll回路および送信システム |
| CN118801874A (zh) * | 2024-07-25 | 2024-10-18 | 思瑞浦微电子科技(上海)有限责任公司 | 双模式时钟系统及模式切换方法 |
-
2022
- 2022-08-23 JP JP2023543935A patent/JP7818608B2/ja active Active
- 2022-08-23 CN CN202280057066.7A patent/CN117837087A/zh active Pending
- 2022-08-23 WO PCT/JP2022/031746 patent/WO2023027078A1/ja not_active Ceased
- 2022-08-23 EP EP22861366.7A patent/EP4395178A4/en active Pending
- 2022-08-24 TW TW111131890A patent/TW202318808A/zh unknown
-
2024
- 2024-02-14 US US18/441,724 patent/US12401367B2/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI869261B (zh) * | 2024-04-10 | 2025-01-01 | 新唐科技股份有限公司 | 降低電源訊號線雜訊對解碼影響的方法以及使用其之解碼電路 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023027078A1 (ja) | 2023-03-02 |
| EP4395178A4 (en) | 2024-12-25 |
| JP7818608B2 (ja) | 2026-02-20 |
| US20240187006A1 (en) | 2024-06-06 |
| CN117837087A (zh) | 2024-04-05 |
| JPWO2023027078A1 (https=) | 2023-03-02 |
| US12401367B2 (en) | 2025-08-26 |
| EP4395178A1 (en) | 2024-07-03 |
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