JP7818608B2 - Ｐｌｌ回路および送信システム - Google Patents

Ｐｌｌ回路および送信システム

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Publication number
JP7818608B2
JP7818608B2 JP2023543935A JP2023543935A JP7818608B2 JP 7818608 B2 JP7818608 B2 JP 7818608B2 JP 2023543935 A JP2023543935 A JP 2023543935A JP 2023543935 A JP2023543935 A JP 2023543935A JP 7818608 B2 JP7818608 B2 JP 7818608B2
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JP
Japan
Prior art keywords
clock signal
reference clock
signal
circuit
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2023543935A
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English (en)
Japanese (ja)
Other versions
JPWO2023027078A1 (https=
JPWO2023027078A5 (https=
Inventor
真由子 藤田
亮規 新名
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nuvoton Technology Corp Japan
Original Assignee
Nuvoton Technology Corp Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Publication of JPWO2023027078A1 publication Critical patent/JPWO2023027078A1/ja
Publication of JPWO2023027078A5 publication Critical patent/JPWO2023027078A5/ja
Application granted granted Critical
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/195—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2023543935A 2021-08-25 2022-08-23 Ｐｌｌ回路および送信システム Active JP7818608B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021137169 2021-08-25
JP2021137169 2021-08-25
PCT/JP2022/031746 WO2023027078A1 (ja) 2021-08-25 2022-08-23 Ｐｌｌ回路および送信システム

Publications (3)

Publication Number Publication Date
JPWO2023027078A1 JPWO2023027078A1 (https=) 2023-03-02
JPWO2023027078A5 JPWO2023027078A5 (https=) 2024-05-21
JP7818608B2 true JP7818608B2 (ja) 2026-02-20

Family

ID=85322853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023543935A Active JP7818608B2 (ja) 2021-08-25 2022-08-23 Ｐｌｌ回路および送信システム

Country Status (6)

Country Link
US (1) US12401367B2 (https=)
EP (1) EP4395178A4 (https=)
JP (1) JP7818608B2 (https=)
CN (1) CN117837087A (https=)
TW (1) TW202318808A (https=)
WO (1) WO2023027078A1 (https=)

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JP7818608B2 (ja) * 2021-08-25 2026-02-20 ヌヴォトンテクノロジージャパン株式会社 Ｐｌｌ回路および送信システム
US12542547B2 (en) * 2024-02-26 2026-02-03 International Business Machines Corporation Reducing the time to switch between the redundant clock signals applied to a phase lock loop
EP4629512A1 (en) * 2024-04-02 2025-10-08 Nxp B.V. Phase-locked loop reference clock switching with controlled output transient frequency drift
TWI869261B (zh) * 2024-04-10 2025-01-01 新唐科技股份有限公司 降低電源訊號線雜訊對解碼影響的方法以及使用其之解碼電路
CN118590041A (zh) * 2024-06-20 2024-09-03 中国电子科技集团公司第十研究所 一种数字集成电路时钟复位系统

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Also Published As

Publication number Publication date
WO2023027078A1 (ja) 2023-03-02
EP4395178A4 (en) 2024-12-25
US20240187006A1 (en) 2024-06-06
CN117837087A (zh) 2024-04-05
TW202318808A (zh) 2023-05-01
JPWO2023027078A1 (https=) 2023-03-02
US12401367B2 (en) 2025-08-26
EP4395178A1 (en) 2024-07-03

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