TW201719755A - 特徵尺寸縮減技術（二） - Google Patents

特徵尺寸縮減技術（二） Download PDF

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TW201719755A
TW201719755A TW105130848A TW105130848A TW201719755A TW 201719755 A TW201719755 A TW 201719755A TW 105130848 A TW105130848 A TW 105130848A TW 105130848 A TW105130848 A TW 105130848A TW 201719755 A TW201719755 A TW 201719755A
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艾略特Ｎ 譚
麥可Ｋ 哈波
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英特爾公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask

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Abstract

用於半導體裝置製造的方法被提供。特徵利用間隔物而生成。方法包括在基板表面上生成包含至少二第一特徵的一圖案，在該至少二第一特徵上沈積第一共形層，在該第一共形層上沈積第二共形層，部分地移除該第二共形層以部分地曝光該第一共形層，及自該等第一特徵與該第二共形層中間部分地移除該第一共形層，從而生成至少二第二特徵。可選擇地，在該第二共形薄膜被沈積之前，第一共形薄膜被部分地回蝕。

Description

特徵尺寸縮減技術(二)
發明領域
本發明之實施例大體有關於半導體加工及製造、積體電路，及用以在積體電路中生成裝置的間隔物。
發明背景
為推展更小的積體電路(IC)對用以構建IC裝置的技術及材料寄予極大的性能要求。一般而言，一積體電路晶片也被稱作微晶片、矽晶片，或一晶片。IC晶片存在於各種常見裝置，諸如計算機、汽車、電視、CD播放器，及蜂巢式電話中的微處理器中。複數IC晶片典型地建立在一矽晶圓(直徑為，例如300mm的一薄矽碟)上，且在加工後，晶圓被切成小方塊以產生個別晶片。特徵尺寸在大約65nm左右的一1cm2 IC晶片可包含數億組件。現有技術推展小於45nm的特徵尺寸。
發明概要
依據本發明之一實施例，係特地提出一種積體電路結構，其包含：一基板；以及複數個特徵在該基板中，該複 數個特徵具有一間距，其中該間距是被使用來製造該積體電路結構之一最小微影術間距的三分之一，其中該複數個特徵之該間距係在5奈米及30奈米之間。
105、205、305、405‧‧‧基板
110‧‧‧第一特徵
115‧‧‧第一共形間隔物薄膜/共形間隔物薄膜/非晶碳
120‧‧‧第二共形間隔物薄膜/第二間隔物薄膜
124、325、425、426‧‧‧特徵
210、310、311、410、411‧‧‧第一特徵/特徵
215‧‧‧第一共形間隔物薄膜
220‧‧‧第二共形間隔物薄膜/第二共形薄膜/特徵/第二間隔物薄膜
315、415‧‧‧第一共形薄膜
320‧‧‧第二共形薄膜/第二間隔物薄膜
420‧‧‧第二共形薄膜/第二間隔物薄膜
第1A-E圖繪示一可用於積體電路裝置製造，使用雙間隔物來生成特徵的製程。
第2A-F圖繪示一可用於積體電路裝置製造，使用雙間隔物來生成特徵的另外一製程。
第3A-C圖提供一可用於積體電路裝置製造，使用雙間隔物來生成可變線路間距特徵的又一製程。
第4A-C圖繪示一可用於積體電路裝置製造，使用雙間隔物來生成可變線路間距特徵的另外一製程。
較佳實施例之詳細說明
有各種不同製程用以製造構成一積體電路晶片的裝置，諸如，鋪設材料的沈積製程，及移除選定區域中之材料的微影術及蝕刻製程。半導體晶片之持續小型化需要以45nm尺度及低於45nm尺度界定特徵。用以生成特徵的一常見製程為光蝕刻(微影術)。微影術典型地涉及沈積一層光阻劑在晶圓表面欲被圖案化的材料上，以電磁輻射(典型地為深紫外線)使光阻劑圖案化，及移除圖案化(或未圖案化，視光阻劑類型而定)區域中的光阻劑。在已曝光之光阻劑之下的層接著在一典型的製程中被蝕刻。以電磁輻射來使光阻劑圖案化例如可藉透過一遮罩來曝光光阻劑來完 成。於是，遮罩圖案被轉移至光阻劑。諸如浸沒及EUV(極紫外線)微影術之技術允許製造更小的特徵。然而，光學微影術上存在由光學系統之成像波長及數值孔徑所決定的解析度限制。
其上建立有構成IC電路晶片之裝置的基板例如是矽晶圓或絕緣體上覆矽基板。矽晶圓是典型地用在半導體加工業中的基板，惟本發明之實施例並不依賴於所用基板類型。該基板也可包含例如，鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、碲化鎵，及或單獨或與矽或二氧化矽或其他絕緣材料組合的其他III-V族材料。構成晶片的IC裝置建立在基板表面上。裝置選擇性地分佈在基板表面上及或彼此上下堆疊。
本發明之實施例提供在一基板，諸如矽晶圓上圖案化特徵使其具有一緊密圖案密度之方法。間隔物用以生成具有小於可藉由微影術所獲得者之間距的特徵，同時還使生成特徵所需的製程數目最小化。一般而言，一特徵之間距是重複特徵單元之間的距離，且在量測中包括一特徵尺寸(例如特徵寬度)。
第1A-E圖繪示用以使用雙間隔物來生成特徵的一製程。一般而言，一間隔物是在一裝置製程期間生成的一特徵，該間隔物可在製程期間全部或部分移除。在第1A圖中，一基板105具有第一特徵110。第一特徵110透過一沈積、微影圖案化，及蝕刻製程製造在基板105上，例如，藉由沈積一層材料使特徵由該材料被製成在一基板 表面上，以一光阻劑塗覆該材料，微影圖案化該光阻劑，依據圖案選擇性地移除光阻劑，且蝕刻光阻劑已被移除之區域中的材料，以及移除剩餘的光阻劑。特徵110包含，例如氮化矽(SiN)。使用具有一3x間距的特徵110(如同第1圖中一般)產生具有一1x間距之特徵的一裝置。在第1圖中，特徵110之寬度為0.5x。在第1圖中，初始的邊緣到邊緣特徵到特徵110距離為2.5x。在本發明之實施例中，1x是欲達成的最終間距，且3x是藉由微影術而圖案化的起始間距。在實施例中，x是5nm與30nm之間的一數字。特徵110之高度(h)典型地在10nm到100nm的範圍內。因此，依據本發明之實施例，一種技術，諸如提供具有一60nm間距之特徵的EUV微影術，可用以製造具有一20nm間距之特徵，且一種技術，諸如提供一80nm間距之特徵的浸沒微影術，可用以製造具有一27nm間距之特徵。在此實施例中，特徵110之寬度(在第1A圖中為0.5x)，和欲生成之特徵與特徵110間的距離(在第1A圖中為2.5x)之比為1：5。然而，為了簡化，在第1A-E圖中所示之實施例中，該等特徵被繪示為一光柵，該等特徵之幾何形狀、佈局及數目並不限於此實施例中所示之幾何形狀、佈局及數目。允許半導體裝置製作的(複數)特徵之其他幾何形狀、佈局及數目是可能的。
在第1B圖中，第一共形間隔物薄膜115已沈積在特徵110及基板105之表面上。在此實施例中，共形間隔物薄膜115具有0.5x的厚度。第一共形間隔物薄膜115 包含例如非晶碳，且可使用例如化學氣相沈積來沈積。在第1C圖中，第二共形間隔物薄膜120已沈積並覆蓋第一共形間隔物薄膜115。在此實施例中，第二共形間隔物薄膜120具有0.5x的厚度。第二共形間隔物薄膜120包含例如氮化矽，且可使用例如化學氣相沈積或原子層沈積來沈積。在第1D圖中，該第二共形間隔物薄膜被部分回蝕，移去第一共形間隔物薄膜115之覆蓋物。蝕刻例如使用反應性離子電漿來完成。
在第1E圖中，第一共形間隔物薄膜115被選擇性地蝕刻掉，生成特徵124，特徵124部分包含第二共形間隔物薄膜120。蝕刻例如使用一乾式蝕刻以一反應性離子電漿來完成，且就非晶碳115而言，利用一氧電漿。所生成的特徵110及124具有一1x間距，0.5x之寬度，及0.5x的一邊緣到邊緣特徵距離。依據本發明之實施例，一組具有一30nm間距之特徵可使用具有一90nm間距的一起始光柵而生成，且一組具有一20nm間距的特徵可使用具有一60nm間距的一起始光柵來生成。本發明之實施例有利地允許特徵尺寸縮減同時還使用一相對較少數目的製程步驟。
第2A-F圖繪示用以使用半導體加工技術及間隔物來生成特徵的另一製程。在第2A圖中，一基板205具有第一特徵210。第一特徵210透過一沈積、微影圖案化，及蝕刻製程，例如藉由沈積特徵從中被製造的一層材料在一基板表面上，以一光阻劑塗覆該材料，微影圖案化該光阻劑，依據圖案選擇性地移除光阻劑，且蝕刻光阻劑 已被移除之區域中的材料，以及移除剩餘的光阻劑，且第一特徵210例如包含氮化矽。使用具有一3x間距的特徵210造成具有一1x間距之特徵的一裝置。特徵210之寬度為0.5x。在第2圖中，邊緣到邊緣特徵距離為2.5x。在本發明之實施例中，x是5nm與30nm之間的一數字。特徵210之高度(h)典型地在10nm到100nm的範圍內。在此實施例中，特徵210之寬度(在第2A圖中為0.5x)和欲生成之特徵與特徵間距離(在第2A圖中為2.5x)之比為1：5。然而，為了簡化，在第2A-E圖中所示之實施例中，該等特徵被繪示為一光柵，該等特徵之幾何形狀、佈局及數目並不限於此實施例中所示之幾何形狀、佈局及數目。允許半導體裝置製成的(複數)特徵之其他尺寸、幾何形狀、佈局、相對方位，及數目是可能的。
在第2B圖中，第一共形間隔物薄膜215覆蓋特徵210及基板205之表面。在此實施例中，第一共形間隔物薄膜215具有0.5x的厚度。第一共形間隔物薄膜215由例如氧化矽所構成，且例如可使用化學氣相沈積或原子層沈積來沈積。在第2C圖中，第一共形間隔物薄膜215已被部分回蝕，部份地曝光基板且部分地曝光特徵210。自第2B圖之裝置生成第2C圖之裝置的蝕刻例如藉由反應性離子電漿來完成。
在第2D圖中，第二共形間隔物薄膜220已被沈積並覆蓋第一共形間隔物薄膜215。在此實施例中，第二共形薄膜220具有0.5x的厚度。第二共形薄膜220是由例 如非晶碳所構成且可使用例如化學氣相沈積或原子層沈積來沈積。在第2E圖中，第二共形薄膜220被部分回蝕，部分地移去第一共形間隔物薄膜115之覆蓋物，且部分地移去基板205表面之覆蓋物。部分蝕刻例如是使用反應性離子電漿而完成。
在第2F圖中，第一共形間隔物薄膜215被移除，顯露出特徵210及220。第一氧化矽共形間隔物薄膜215例如透過濕式蝕刻使用含水HF被移除。所生成的特徵210及220具有一1x間距，0.5x之寬度，及0.5x的一邊緣到邊緣特徵距離。
第3A-C圖繪示用於半導體裝置特徵製造，其中所生成之特徵間距改變的一製程。第3A-C圖中所示之實施例例如與第1A-E及2A-F圖之方法一起使用。亦可組合第3A-C圖與第4A-C圖之元件。在第3A圖中，基板305具有第一特徵310及311。在第3A-C圖之實施例中，特徵尺寸藉由改變第一特徵310及311之尺寸而改變，且可看出，第一特徵310具有0.5x之寬度，且第一特徵311具有1.5x之寬度。具有其他寬度的第一特徵也是可能的，且特定值之選擇視例如所製造之裝置類型而定。同樣地，第一特徵310與311之間的邊緣到邊緣距離被改變且距離2.5x及3x被繪示於第3A圖中。其他邊緣到邊緣特徵距離也是可能的，且特定值之選擇視例如所製造之裝置類型而定。在第3B圖中，繪示第一共形薄膜315已被回蝕(依據第2A-F圖之實施例)的一實施例，但是如先前所提到者，也可不回蝕 第一共形薄膜315(依據第1A-E圖之實施例)。第二共形薄膜320已被沈積並覆蓋特徵310及311，及剩餘之第一共形薄膜315。在第二共形薄膜320已被部分回蝕且第一共形薄膜自第一特徵310與311之間被蝕刻之後，獲得第3C圖之裝置。從第3C圖中可見，特徵310、311及325具有1.5x及0.5x的尺寸。特徵310、311與325之間的邊緣到邊緣距離在0.5x與1x之間變化。使用特徵310、311，及325作為一遮罩，由特徵310、311，及325所生成的圖案可選擇性地被蝕刻到基板305中。在基板被蝕刻之後，特徵310、311及325被選擇性地移除。
第4A-C圖繪示用於半導體裝置特徵製造，其中所生成之特徵之間距改變的製程。第4A-C圖中所示之實施例例如與第1A-E及2A-F圖之方法一起使用。亦可組合第4A-C圖與第3A-C圖之元件。在第4A圖中，基板405具有第一特徵410及411。在第3A-C圖之實施例中，特徵尺寸藉由改變第一特徵410及411之尺寸而改變，且可看出，第一特徵410具有0.5x之寬度，且第一特徵411具有1x之寬度。具有其他寬度的第一特徵410及411也是可能的且特定值之選擇視例如所製造之裝置類型而定。同樣地，第一特徵410與411之間的邊緣到邊緣距離被改變且距離2x及3x被繪示於第4A圖中。其他邊緣到邊緣特徵距離也是可能的且特定值之選擇視例如所製造之裝置類型而定。在第4B圖中，繪示第一共形薄膜415已被回蝕(依據第2A-F圖之實施例)的一實施例，但是如先前所提到者，也可不回蝕第一共 形薄膜415(依據第1A-E圖之實施例)。第二共形薄膜420已被沈積並覆蓋特徵410及411，及剩餘之第一共形薄膜415，並填充二第一特徵410與411之間之間隙。在第二共形薄膜420已被部分回蝕而曝光第一共形薄膜415，且第一共形薄膜自第一特徵410與411之間被蝕刻之後，獲得第4C圖之裝置。從第4C圖中可見，特徵410及425具有0.5x的尺寸且特徵411及426具有1x的尺寸。特徵410、411、425與426之間的邊緣到邊緣距離在0.5x與1x之間變化。使用特徵410、411、425，及426作為一遮罩，由特徵410、411、425及426所生成的圖案可選擇性地被蝕刻到基板305中。在基板被蝕刻之後，特徵410、411、425及426被選擇性地移除。
可選擇地，依據本發明之實施例，藉由所揭露之方法所生成之特徵可用作一遮罩，以將特徵轉移到下面的基板中。在一實施例中，其上配置有特徵的基板表面是矽，且使用，例如，乾式蝕刻，將該等特徵轉移到矽基板之表面中。該等特徵接著使用例如濕式蝕刻被選擇性地移除。
進一步可選擇地，一硬遮罩用以協助將藉由所揭露方法生成之特徵轉移至下面的基板中。在一硬遮罩被使用的實施例中，一硬遮罩在第一特徵(即110、210、310、311、410及411)被製作在基板上前被提供給基板，使得該硬遮罩位在基板與第一特徵與共形間隔物薄膜之間。在這些實施例中，所生成之圖案被轉移至硬遮罩(即硬 遮罩在曝光區域中被蝕刻)，該等特徵被移除，且曝光基板被蝕刻，生成特徵於基板中。
當然，可以使用其他材料作為第一特徵及第一與第二共形間隔物。一般而言，材料被選擇成使得一蝕刻化學作用能夠區分主幹(即第一特徵110、210、310、311、410，及411)與第二間隔物薄膜(即120、220、320，及420)，使得第一間隔物薄膜可被選擇性地蝕刻掉，留下第一及第二(間隔物)特徵。表格1提供可用在相關於例如第1-4圖所描述之本發明之實施例中的另外示範性材料。在表格1中，SiN是氮化矽，a-C是非晶碳，PLY-Si是多晶矽，a-Si是非晶矽，SiO是二氧化矽，TiN是氮化鈦，且CHM是一碳硬遮罩。
依據表1，一選項，諸如選項3，包括使用多晶矽做第一特徵，二氧化矽做第一間隔物，及非晶矽做第二特徵。一可選擇的硬遮罩由氮化矽組成。
熟習相關技藝人士了解，在整體揭露以及所示與所述的各種組件的組合與替代品中，修改及變更是可能的。此說明書中提及「一個實施例」或「一實施例」意指結合該實施例所描述的一特定特徵、結構、材料或特性 被包括在本發明之至少一實施例中，但並不一定表示它們存在於每一實施例中。此外，特定特徵、結構、材料，或特性可以在一或更多個實施例中以任何適合的方式被組合。各種附加層及/或結構可被納入其他實施例且/或所述特徵可在其他實施例中被省略。
105‧‧‧基板
110‧‧‧第一特徵
124‧‧‧特徵

Claims (19)

  1. 一種積體電路結構，其包含：一基板；以及複數個特徵在該基板中，該複數個特徵具有一間距，其中該間距是被使用來製造該積體電路結構之一最小微影術間距的三分之一，其中該複數個特徵之該間距係在5奈米及30奈米之間。
  2. 如請求項1之積體電路結構，其中該複數個特徵之各者具有一寬度，該寬度大約該複數個特徵之該間距的一半。
  3. 如請求項1之積體電路結構，其中該複數個特徵之各者係藉由一間隔來將一鄰近的特徵隔開，該間隔大約該複數個特徵之該間距的一半。
  4. 如請求項1之積體電路結構，其中該複數個特徵之該間距係大約20奈米，且該最小微影術間距係大約60奈米。
  5. 如請求項4之積體電路結構，其中該最小微影術間距係一最小EUV微影術間距。
  6. 如請求項1之積體電路結構，其中該複數個特徵之該間距係大約27奈米，且該最小微影術間距係大約80奈米。
  7. 如請求項6之積體電路結構，其中該最小微影術間距係一最小浸沒微影術間距。
  8. 一種積體電路結構，其包含： 一包含矽之基板；以及複數個矽特徵在該基板中，該複數個矽特徵具有一間距，其中該間距是被使用來製造該積體電路結構之一最小微影術間距的三分之一間距，其中該複數個矽特徵之該間距係在5奈米及30奈米之間。
  9. 如請求項8之積體電路結構，其中該複數個矽特徵之各者具有一寬度，該寬度大約該複數個矽特徵之該間距的一半。
  10. 如請求項8之積體電路結構，其中該複數個矽特徵之各者係藉由一間隔來將一鄰近的矽特徵隔開，該間隔大約該複數個矽特徵之該間距的一半。
  11. 如請求項8之積體電路結構，其中該複數個矽特徵之該間距係大約20奈米，且該最小微影術間距係大約60奈米。
  12. 如請求項11之積體電路結構，其中該最小微影術間距係一最小EUV微影術間距。
  13. 如請求項8之積體電路結構，其中該複數個矽特徵之該間距係大約27奈米，且該最小微影術間距係大約80奈米。
  14. 如請求項13之積體電路結構，其中該最小微影術間距係一最小浸沒微影術間距。
  15. 一種積體電路結構，其包含：一包含矽之基板；以及複數個矽特徵在該基板中，該複數個矽特徵具有一間 距，其中該間距是被使用來製造該積體電路結構之一最小微影術間距的三分之一間距，其中該複數個矽特徵之各者具有一寬度，該寬度大約該複數個矽特徵之該間距的一半，其中該複數個矽特徵之各者係藉由一間隔來將一鄰近的矽特徵隔開，該間隔大約該複數個矽特徵之該間距的一半，以及其中該複數個矽特徵之該間距係在5奈米及30奈米之間。
  16. 如請求項15之積體電路結構，其中該複數個矽特徵之該間距係大約20奈米，且該最小微影術間距係大約60奈米。
  17. 如請求項16之積體電路結構，其中該最小微影術間距係一最小EUV微影術間距。
  18. 如請求項15之積體電路結構，其中該複數個矽特徵之該間距係大約27奈米，且該最小微影術間距係大約80奈米。
  19. 如請求項18之積體電路結構，其中該最小微影術間距係一最小浸沒微影術間距。
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