CN104733291B - 用于集成电路图案化的方法 - Google Patents
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Abstract
一种形成目标图案的方法包括利用第一掩模在衬底上方形成多条线并且在衬底上方、多条线上方和多条线的侧壁上形成第一间隔件层。多条线被去除，从而在衬底上方提供图案化的第一间隔件层。该方法还包括在衬底上方、图案化的第一间隔件层上方和图案化的第一间隔件层的侧壁上形成第二间隔件层，并利用第二掩模在第二间隔件层上方形成图案化的材料层。借此，图案化的材料层和第二间隔件层共同地限定多个沟槽。本发明涉及用于集成电路图案化的方法。
Description
技术领域
本发明涉及用于集成电路图案化的方法。
背景技术
半导体集成电路(IC)工业经历了指数式发展。IC材料和设计中的技术进步已产生了数代IC，其中，每代IC都比前一IC具有更小且更复杂的电路。在IC演变过程中，功能密度(即，每芯片面积上互连器件的数量)通常都已增加，而几何尺寸(即，可使用制造工艺可以创建的最小组件(或线))却已减小。这种按比例缩小工艺通常通过增加成产效率和降低相关成本而提供益处。这些按比例缩小也增加了处理和制造IC的复杂性，并且为了实现这些进步，需要IC处理和制造中的类似发展。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种形成用于集成电路的目标图案的方法，所述方法包括：利用第一掩模在衬底上方形成多条线；在所述衬底上方、所述多条线上方和所述多条线的侧壁上形成第一间隔件层；去除所述第一间隔件层的至少一部分以暴露所述多条线；去除所述多条线从而在所述衬底上方提供图案化的第一间隔件层；在所述衬底上方、所述图案化的第一间隔件层上方和所述图案化的第一间隔件层的侧壁上形成第二间隔件层；以及利用第二掩模在所述第二间隔件层上方形成图案化的材料层，从而所述图案化的材料层和所述第二间隔件层共同地限定多个沟槽。
在上述方法中，还包括：将所述多个沟槽转印至所述衬底。
在上述方法中，还包括：穿过所述多个沟槽的开口蚀刻所述第二间隔件层以暴露所述衬底；穿过所述多个沟槽的开口蚀刻所述衬底；以及在蚀刻后，去除所述第一间隔件层、所述第二间隔件层和所述图案化的材料层。
在上述方法中，形成所述多条线包括：在所述衬底上方形成光刻胶层；以及利用所述第一掩模图案化所述光刻胶层。
在上述方法中，形成所述多条线包括：在所述衬底上方形成硬掩模层；在所述硬掩模层上方形成光刻胶层；利用所述第一掩模图案化所述光刻胶层；将所述图案化的光刻胶层用作蚀刻掩模蚀刻所述硬掩模层；以及之后去除所述图案化的光刻胶层。
在上述方法中，形成所述第一间隔件层和所述第二间隔件层包括沉积。
在上述方法中，形成所述图案化的材料层包括：在所述第二间隔件层上方形成第一材料层；在所述第一材料层和所述第二间隔件层上方形成第二材料层；利用所述第二掩模图案化所述第二材料层；将所述图案化的第二材料层用作蚀刻掩模蚀刻所述第一材料层；以及之后去除所述图案化的第二材料层。
在上述方法中，还包括：回蚀刻所述第一材料层从而在形成所述第二材料层之前暴露所述第二间隔件层。
在上述方法中，图案化所述第二材料层使用光刻工艺，包括：在所述第二材料层上方形成光刻胶层；利用所述第二掩模图案化所述光刻胶层；将所述图案化的光刻胶层用作蚀刻掩模蚀刻所述第二材料层；以及之后去除所述图案化的光刻胶层。
在上述方法中，蚀刻所述第一材料层包括选择性地调整为使用所述图案化的第二材料层作为蚀刻掩模来去除所述第一材料层而保留所述第二间隔件层的工艺。
在上述方法中，去除所述第一间隔件层的至少一部分包括各向异性蚀刻工艺。
在上述方法中，去除所述多条线包括等离子体蚀刻工艺。
在上述方法中，所述多个沟槽的至少一个的尺寸由所述第一掩模的图案间隔和位于所述多条线的侧壁上方的所述第一间隔件层和所述第二间隔件层的厚度至少部分地限定。
根据本发明的另一方面，还提供了一种方法，包括：在衬底上方形成线，所述衬底具有多个硬掩模层；在所述衬底上方、所述线上方和所述线的侧壁上将第一材料沉积至第一厚度；去除所述线从而在所述衬底上方提供图案化的第一材料；在所述衬底上方、所述图案化的第一材料上方和所述图案化的第一材料的侧壁上将第二材料沉积至第二厚度；在所述第二材料上方沉积第三材料；以及图案化所述第二材料和所述第三材料以形成沟槽。
在上述方法中，还包括，在沉积所述第一材料之前：将所述线转印至所述硬掩模层中的一个。
在上述方法中，还包括，在所述去除所述线之前，去除所述第一材料的至少一部分以暴露所述线。
在上述方法中，还包括，穿过所述沟槽的开口蚀刻所述衬底。
根据本发明的又一方面，还提供了一种形成用于集成电路的目标图案的方法，所述方法包括：将所述目标图案分解到至少第一掩模和第二掩模，所述第一掩模具有第一掩模图案，所述第二掩模具有第二掩模图案，其中，所述第一掩模图案的至少一部分与所述第二掩模图案的至少一部分重叠；利用所述第一掩模图案化衬底从而形成多个第一部件；在所述衬底上方、所述多个第一部件上方和所述多个第一部件的侧壁上形成第一间隔件层；部分地去除所述第一间隔件层以暴露所述衬底和所述多个第一部件；去除所述多个第一部件；在所述衬底上方、所述第一间隔件层上方和所述第一间隔件层的侧壁上形成第二间隔件层；在所述第二间隔件层上方形成第一材料层；以及利用所述第二掩模图案化所述第一材料层，其中，所述第二间隔件层和所述图案化的第一材料层共同地限定多个第二部件。
在上述方法中，还包括：在图案化所述第一材料层之前回蚀刻所述第一材料层以暴露所述第二间隔件层。
在上述方法中，还包括：将所述多个第二部件转印至所述衬底；以及之后去除所述图案化的第一材料层及所述第一间隔件层和所述第二间隔件层。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1是在衬底上形成目标图案或器件以实施本发明的一个或多个实施例的方法的流程图。
图2根据本发明的各个方面示出了示例性衬底和将形成在其上的目标图案。
图3a至图14b是根据实施例的按照图1的方法形成图2的目标图案的俯视图和截面图。
图15示出了具有可根据本发明的各个方面进行调整的多种尺寸的最终图案。
图16a至图17b是根据实施例的按照图1的方法形成用于图2的目标图案的芯轴线的俯视图和截面图。
图18a至图18b是根据实施例的按照图1的方法形成用于图2的目标图案的沟槽的俯视图和截面图。
具体实施方式
为了实现本发明的不同特征，以下描述提供了许多不同的实施例或实例。以下描述组件和布置的特定实例以简化本公开。当然，这些仅仅是实例并不打算限定。另外，本公开可能在各个实施例中重复参考标号和/或字符。这种重复只是为了简化和清楚的目的且其本身并不指定所讨论的各个实施例和/或结构之间的关系。另外，在以下描述中于第二工艺之前执行第一工艺可包括在第一工艺之后立即执行第二工艺的实施例，并还可包括于第一和第二工艺之间执行另外的工艺的实施例。可出于简化和清楚的目的而以不同比例任意绘制各个部件。另外，在以下描述中第一部件形成在第二部件上方或第二部件上可包括第一和第二部件以直接接触的方式形成的实施例，并且还可以包括形成在第一和第二部件之间形成额外部件以使第一和第二部件不直接接触的实施例。
而且，为便于说明，诸如“在···之下”、“下面”、“下部”、“在···之上”、“上部”等空间关系术语可在此用以描述如图中所示的一个元件或部件与另一个元件或部件的关系。除了图中所示的方位之外，空间相对术语旨在包括处于使用或操作状态的器件的不同方位。例如，如果附图中的器件被翻转，则描述为在其他元件或部件“下面”或“之下”的元件将然后被定向为在其他元件或部件“之上”。因此，示例性术语“下面”可包含“在···之上”和“下面”的方位。装置可以以其他方式定向(旋转90度或者在其他方位上)，并且在此使用的空间相对描述符可类似进行相应的解释。
本发明通常涉及采用间隔件技术通过193nm浸没式光刻或其他合适的光刻技术提高先进工艺节点(诸如14纳米(nm)、10nm等)中的集成电路图案密度。在一种间隔件技术中，光刻胶材料被在衬底上图案化并随后被修整。随后，修整后的光刻胶图案被转印至下方的芯轴层从而形成芯轴线且此后去除修整后的光刻胶图案。在芯轴线的侧壁上形成间隔件。后续的间隔件蚀刻和芯轴去除工艺导致将间隔件留在衬底上作为最终图案。尽管最终图案的间距被减小归因于光刻胶修整工艺，但通过相同的光刻胶修整工艺不期望地增大了最终图案的线端至端(EtE)距离。这可通过光刻胶材料在横向和垂直方向上的几乎相等的蚀刻率进行解释。即便在不使用光刻胶修整工艺的情况下，本发明使用双间隔件工艺来增大最终图案密度。本发明的优势在于：通过调整间隔件的厚度可灵活地调整最终图案的间距、线至线距离及EtE距离。
现参照图1，根据本发明的各个方面示出了用于形成目标图案或器件的方法100的流程图。在方法100之前、期间和之后，可提供额外的操作，且所述的一些操作可被替换、消除或移动以用于该方法的另外的实施例。下面将对方法100进一步描述。方法100为实例且并不意在限制本公开超出权利要求中所明确列举的。
图2示出了示例性目标图案200。目标图案200包括布置成两行的密集部件180a至180b、182a至182b和184a至184b及隔离部件186。出于示例目的，“b”部件(180b、182b和184b)具有分别与“a”部件(180a、182a和184a)相同的尺寸和间隔，并且所有“a”和“b”部件沿Y方向具有相同尺寸L。“b”部件和“a”部件之间沿Y方向的端至端(EtE)距离为目标图案200的临界尺寸。部件180a、182a和184a沿X方向分别具有宽度W1、W2和W3。此外，部件180a、182a和184a沿X方向由间隔S1和S2间隔开。目标图案200可被用以形成集成电路(IC)的多个部件。在实施例中，目标图案200被用以在多层互连结构中形成金属线。在另一实施例中，目标图案200被用以在半导体衬底中形成多个沟槽以用于浅沟槽隔离(STI)部件。随着集成电路的密度增加，一些部件对于掩模(或光掩模)的分辨率而言，太过靠近。为克服这个问题，目标图案的部件可被分配给两个或更多掩模。在本实施例中，将部件180a至180b及184a至184b分配给第一掩模且将部件182a至182b及186b分配给第二掩模。正如下面将要讨论的，第二掩模包括采用间隔件自对准技术以不严格的精度与部件180a至180b及184a至184b重叠的图案。这点将在后面部分中详细说明。
在后续讨论中，方法100(图1)结合图3a至图17b描述以示出如何根据本发明的各个方面使用第一掩模和第二掩模形成目标图案200。在图3a至图18b的每一个中，以后缀“a”指定的附图(例如，图3a)包括虚线，虚线限定了以后缀“b”、“c”等指定的附图(例如，图3b)的截面图。
方法100(图1)在操作102中接收衬底202。参照图3a和图3b，在本实施例中，衬底202包括材料层214和216。材料层216可使用非晶硅(a-硅)、氧化硅、氮化硅(SiN)或其他合适的材料或组分。材料层214可使用无氮抗反射涂层(NFARC)、旋涂玻璃(SOG)、氮化钛或其他合适的材料或组分。材料层214和216可通过多种工艺形成。例如，材料层214可通过诸如沉积的工序在另一衬底上方形成。在实施例中，材料层216可包括通过热氧化形成的氧化硅。在实施例中，材料层216可包括通过化学汽相沉积(CVD)形成的SiN。例如，材料层216可采用化学物质通过CVD形成，这些化学物质包括六氯二硅烷(HCD或Si2Cl6)、二氯甲硅烷(DCS或Si2H2Cl6)、双(叔丁基氨基)硅烷(BTBAS或C8H22N2Si)和乙硅烷(DS或Si2H6)。材料层214和216可通过类似或不同的步骤形成。上述材料层214和216的示例性组分并不限于本发明的发明范围。
方法100(图1)进行至操作104，通过合适的工艺利用第一掩模在衬底202上方形成芯轴线，合适的工艺诸如包括光刻工艺的工艺。参照图4a和图4b，芯轴线218a至218d在衬底202上方形成。芯轴线218a、218c、218b和218d以间距Pm分别限定在对应于部件180a至180b及184a至184b(图2)的第一掩模中。芯轴线218a至218c(218b至218d)沿X方向具有第一尺寸W1m(W3m)并沿Y方向具有第二尺寸Lm。尺寸W1m、W3m和Lm分别大于对应的尺寸W1、W3和L(图2)。这点在后面结合图15将变得更为清楚。
在实施例中，在光刻工艺中在负光刻胶或正光刻胶(或photoresist)材料中形成芯轴线218a至218d。示例性光刻工艺包括在材料层216上方涂覆负光刻胶层218、软烘该光刻胶层218、以及采用第一掩模将光刻胶层218曝光于深紫外(DUV)光。该工艺进一步包括曝光后烘焙(PEB)、显影及硬烘焙，从而去除光刻胶层218的未曝光部分并使光刻胶层218的曝光部分留在衬底202上作为芯轴线218a至218d。在另一实施例中，芯轴线218a至218d可以类似的光刻工艺由正光刻胶材料层的未曝光部分形成。
在另一实施例中，芯轴线218a至218d可采用之后进行蚀刻工艺的光刻工艺在硬掩模层中形成。参照图16a至17b，硬掩模层218(2)和217及光刻胶层219在材料层216上方形成。采用第一掩模通过诸如上面所讨论的光刻工艺的光刻工艺(图16a和图16b)图案化光刻胶层219。通过图案化的光刻胶层219的开口蚀刻硬掩模层217并且之后采用诸如湿剥离或等离子灰化的合适工艺去除图案化的光刻胶层219。硬掩模层218(2)随后采用图案化的硬掩模层217作为蚀刻掩模进行蚀刻并且硬掩模层217此后被去除，从而将芯轴线218a至218d留在硬掩模层218(2)中(图17a和图17b)。在一个实例中，蚀刻硬掩模层217包括应用干(或等离子体)蚀刻来去除位于图案化的光刻胶层219的开口内的硬掩模层217。例如，干蚀刻工艺可使用含氧气体、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含硼气体(例如，HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体以及/或者他们的组合。该硬掩模层218(2)可采用类似的或不同的蚀刻工艺进行蚀刻。
方法100(图1)进行至操作106，在衬底202上方及芯轴线218a至218d上方和周围形成第一间隔件层220。参照图5a和图5b，在衬底202上方形成第一间隔件层220，更具体地在材料层216上方形成第一间隔件层220。还在芯轴线218a至218d上方及芯轴线218a至218d的侧壁上形成第一间隔件层220。第一间隔件层220具有第一厚度T1。第一间隔件层220包括不同于材料层216和芯轴线218a至218d的一种或多种材料或组分。在实施例中，第一间隔件层220可包括介电材料，诸如氮化钛、氮化硅、氧化硅或氧化钛。第一间隔件层220可通过诸如沉积工艺的合适工艺形成。例如，沉积工艺包括化学汽相沉积(CVD)工艺或物理汽相沉积(PVD)工艺。
方法100(图1)进行至操作108，蚀刻第一间隔件层220以暴露芯轴线218a至218b及材料层216。参照图6a和图6b，通过该蚀刻工艺暴露芯轴线218a和218b的顶面且还部分地去除布置在材料层216上方的第一间隔件材料，从而分别在芯轴线218a至218d的侧壁上提供第一间隔部件220a至220d。在实施例中，蚀刻第一间隔件层220的工艺包括诸如等离子体蚀刻的各向异性蚀刻。
方法100(图1)进行至操作110，去除芯轴线218a至218d。参照图7a和图7b，去除芯轴线218a至218d，将第一间隔部件220a至220d留在衬底202上方。使用调整为选择性地去除芯轴线218a至218d而同时保留第一间隔部件220a至220d的工艺去除芯轴线218a至218d。
方法100(图1)进行至操作112，在衬底202上方及第一间隔部件220a至220d上方和周围形成第二间隔件层222。参照图8a和图8b，在衬底202上方形成第二间隔件层222，更具体地，在材料层216上方形成第二间隔件层222。也在第一间隔部件220a至220d上方及第一间隔部件220a至220d的侧壁上形成第二间隔件层222。第二间隔件层222具有第二厚度T2。第二间隔件层222包括不同于材料层216的一种或多种材料或组分。第二间隔件层222可使用与第一间隔件层220相同或不同的材料或组分。然而，两个间隔件层220和222中使用的材料可具有类似的蚀刻选择性以便当在后续步骤中蚀刻两个间隔件层时防止不期望的微沟槽形成。在实施例中，第二间隔件层222可包括介电材料，诸如氮化钛、氮化硅、氧化硅或氧化钛。第二间隔件层222可通过诸如沉积工艺的合适工艺形成。例如，该沉积工艺包括化学汽相(CVD)沉积或物理汽相沉积(PVD)工艺。
方法100(图1)进行至操作114，在第二间隔件层222上方形成另一材料层。参照图9a和图9b，材料层222在衬底202上方和第二间隔件层222上方形成。在实施例中，首先将材料层224沉积在第二间隔件层222上方并随后部分地去除材料层224，从而暴露出位于第一间隔部件220a至220d的顶面上方的第二间隔件层222。可通过诸如化学机械抛光(CMP)或回蚀刻的工序实施材料层224的部分去除。在实施例中，材料层224采用底部抗反射涂层(BARC)或旋涂玻璃(SOG)。
方法100(图1)进行至操作116，利用第二掩模在材料层224和第二间隔件层222上形成沟槽。该操作包括诸如沉积工艺、光刻工艺和蚀刻工艺的多种工艺。结合图10a至图11b和图18a至图18b对此示出。
参照图10a和图10b，将材料层226沉积在第二间隔件层222和材料层224上方。可随后对材料层226执行抛光工艺。硬掩模层228沉积在材料层226上方。在实施例中，材料层226可为底部抗反射涂(BARC)层，而硬掩模层228可由硅制成。在另一实施例中，代替使用两个材料层226和228，可使用一个材料层。光刻胶层230在硬掩模层228上形成并采用光刻工艺利用作为沟槽的第二掩模进行图案化。在本实施例中，第二掩模包括作为沟槽的三个图案230a、230b和230g。图案230a与第一间隔部件220a和220b重叠，从而限定用于部件180a、182a和184a(图2)的沟槽。图案230b与第一间隔部件220a和220d重叠，从而限定用于部件180b、182b和184b(图2)的沟槽。这些沟槽限定归因于芯轴线218a至218d(图4)的尺寸和间距、第一厚度T1(图5b)及第二厚度T2(图8b)。这点将结合图15进行详细的讨论。在本实施例中，布置在第一间隔部件220a和220b上方的第二间隔件层222的外表面之间的间隔被调整为等于部件182的宽度W2。在如图18a和图18b中所示的另一实施例中，当布置在第一间隔件部件220a和220b上方的第二间隔件层222的外表面之间的间隔大于宽度W2时，第二掩模包括六个图案230a至230f。在这方面，图10a可被视作图18a的特殊情况，其中，图18a的图案230a至230c合并成图10a的图案230a且图18a的图案230d至230f合并成图10a的图案230b。
参照图10c，通过蚀刻穿过图案化的光刻胶层230的开口而对硬掩模层228进行图案化。在一个实例中，该蚀刻工艺包括应用干(或等离子体)蚀刻来去除位于图案化的光刻胶层230的开口内的硬掩模层228。例如，干蚀刻工艺可使用含氧气体、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体以及/或者他们的组合。在实施例中，在已经对硬掩模层228进行图案化后，采用诸如湿剥离或等离子体灰化的合适工艺去除或部分地去除图案化的光刻胶层230。
参照图10d，在已图案化硬掩模层228后，将图案化的硬掩模层228用作蚀刻掩模，采用合适的工艺来蚀刻材料层226和224，合适的工艺诸如为调整为选择性去除材料层226和224而同时保留第二间隔件层222的蚀刻工艺。在实施例中，在硬掩模层228图案化步骤之后的光刻胶层230的任何保留部分都通过这种蚀刻工艺去除。在实施例中，在材料层226和224图案化步骤之后的硬掩模层228的任何保留部分同样通过这种蚀刻工艺去除。此后采用合适的工艺去除材料层228和226，合适的工艺诸如调整为选择性去除材料层228和226而同时保留材料层224和第二间隔件层222的蚀刻工艺。
参照图11a和图11b，通过上述蚀刻工艺在材料层224和第二间隔件层222内形成沟槽232a至232g。
方法100(图1)进行至操作118，蚀刻第二间隔件层122以暴露材料层216。参照图12a和图12b，布置在材料层216上方的第二间隔件材料的位于沟槽232a至232g的底部处的部分被去除。第一间隔部件220a至220d还可通过蚀刻工艺暴露并可被部分地去除。材料层224可通过蚀刻工艺被部分地去除。在实施例中，蚀刻第二间隔件层的工艺包括诸如等离子体蚀刻的各向异性蚀刻。由于操作118，第一间隔件层220和第二间隔件层222及材料层224图案化为具有多个开口并且该多个开口对应于目标图案200(图2)的部件180a至180b、182a至182b、184a至184b及186。
方法100(图1)进行至操作120，采用诸如各向异性蚀刻工艺的合适工艺将图案从间隔件层220和222及材料层224转印至材料层216(图13a和图13b)。间隔件层220和222及材料层224此后被去除(图14a和图14b)。参照图14a和图14b，图案在材料层216中形成，从而与目标图案200(图2)匹配。
方法100(图1)进行至操作122以通过图案化后材料层216形成最终图案或器件。在实施例中，目标图案形成为多层互连结构中的金属线。例如，金属线可在层间介电(ILD)层中形成。在这种实例中，操作122使用图案化的材料层216在ILD层中形成多个沟槽；通过诸如金属的导电材料填充沟槽；以及使用诸如化学机械抛光的工艺来抛光导电材料以暴露图案化的ILD层，从而在ILD层中形成金属线。
在另一实施例中，操作122使用图案化的材料层216在半导体衬底上形成鳍式场效应晶体管(FinFET)结构。在该实施例中，操作122在半导体衬底中形成多个沟槽。在沟槽中形成进一步浅沟槽隔离(STI)部件的工序包括：通过介电材料沉积以填充沟槽并抛光(诸如CMP)以去除过多的介电材料及平坦化半导体沉底的顶面。此后，对介电材料应用选择性蚀刻工艺以使STI部件凹进，从而形成鳍状有源区域。
图15示出了目标图案200(图2)的各个尺寸、芯轴线218a至218d(图4a)的各个尺寸、第一间隔件层220(图5b)的厚度T1及第二间隔件层222(图8b)的厚度T2之间的关系。参照图15，其可被视作顺时针旋转90度的图13a的一部分，各个上述尺寸具有下述：
Lm＝L+2×T2 (1)
W1m＝W1+2×T2 (2)
W3m＝W3+2×T2 (3)
Pm＝W1+W2+2×T1+4×T2 (4)
S1≥T1+2×T2 (5)
S2≥T1+2×T2 (6)
EtE＝EtEm+2×T2 (7)
本发明提供了优于传统间隔件技术的多种优势，其中，图案在将间隔件形成于图案上方之前进行修正。一个优势在于较小EtE可通过调整厚度T2实现。作为实例，在采用传统间隔件技术的工艺P中，芯轴线218a至218d的宽度在修正工艺中减小T，以便宽度满足最终图案间距。芯轴线218a至218d的长度通过相同修正工艺同样减小大约T。因此，芯轴线218a至218d之间的端至端间距被从EtEm增加至(EtEm+2×T)，其与通过工艺P的最终图案的端至端距离约相同。相反，在本实施例中，厚度T2可被调整至小于T，其间接地减小最终图案的端至端距离(参见上述公式(7))。除减小的EtE距离外，目标图案200的部件180a至180b、182a至182b和184a至184b的宽度和长度以及它们之间的间距可通过调整厚度T1和T2而制得更小。这通常提供了增加图案密度的优势。本发明的另一优势是节省成本，因为(1)本实施例避免芯轴线修整工艺以及(2)光刻胶层218(图4b)可制得更薄。
前面概述了若干实施例的特征，以便本领域的普通技术人员可更好地理解本发明的方面。本领域普通技术人员应当理解，它们可容易地使用本发明作为基础来设计或修改用于实现实现本文所介绍的实施例的相同目的和/或相同优势的其他工艺和结构。本领域普通技术人员还应当理解，这种等同结构并不背离本发明的精神和范围，并且他们可在不背离本发明的精神和范围的情况下，对本发明作出各种改变、替换和修改。
在一个示例性方面中，本发明针对一种形成用于集成电路(IC)的目标图案的方法。该方法包括利用第一掩模在衬底上方形成多条线；在衬底上方、多条线上方及多条线的侧壁上形成第一间隔件层；去除第一间隔件层的至少一部分以暴露多条线；去除多条线从而在衬底上方提供图案化的第一间隔件层；在衬底上方、图案化的第一间隔件层上方及图案化的第一间隔件层的侧壁上形成第二间隔件层；以及利用第二掩模在第二间隔件层上方形成图案化的材料层从而该图案化的材料层和第二间隔件层共同限定多个沟槽。
在另一示例性方法中，本发明针对一种在具有多个硬掩模层的衬底上方形成图案的方法。该方法包括在衬底上方形成线；在衬底上方、线上方及线的侧壁上将第一材料沉积到第一厚度；去除线从而在衬底上方提供图案化的第一材料；在衬底上方、图案化的第一材料上方及图案化的第一材料的侧壁上将第二材料沉积到第二厚度；在第二材料上方沉积第三材料；以及图案化该第二和第三材料以形成沟槽。
在又一示例性方法中，本发明针对一种形成用于集成电路的目标图案的方法。该方法包括将目标图案分解到至少第一掩模和第二掩模，第一掩模具有第一掩模图案，第二掩模具有第二掩模图案，其中，第一掩模图案的一部分与第二掩模图案的至少一部分重叠。该方法进一步包括利用第一掩模图案化衬底，从而形成多个第一部件；在衬底上方、多个第一部件上方及多个第一部件的侧壁上形成第一间隔件层；部分地去除第一间隔件层来暴露衬底和多个第一部件，且此后去除多个第一部件。该方法还包括在衬底上方、第一间隔件层上方及第一间隔件层的侧壁上形成第二间隔件层；在第二间隔件层上方形成第一材料层；以及利用第二掩模图案化第一材料层，其中，第一间隔件层和图案化的第一材料层共同限定多个第二部件。
Claims (18)
1.一种形成用于集成电路的目标图案的方法，所述方法包括：
利用第一掩模在衬底上方形成多条线；
在所述衬底上方、所述多条线上方和所述多条线的侧壁上形成第一间隔件层；
去除所述第一间隔件层的至少一部分以暴露所述多条线；
去除所述多条线从而在所述衬底上方提供图案化的第一间隔件层；
在所述衬底上方、所述图案化的第一间隔件层上方和所述图案化的第一间隔件层的侧壁上形成第二间隔件层；以及
利用第二掩模在所述第二间隔件层上方形成图案化的材料层，从而所述图案化的材料层和所述第二间隔件层共同地限定多个沟槽，
将所述多个沟槽转印至所述衬底，
其中，在限定所述多个沟槽之后，所述第二间隔件层保留形成在所述图案化的第一间隔件层的上方以及形成在所述图案化的第一间隔件层的所述侧壁上。
2.根据权利要求1所述的方法，其中，将所述多个沟槽转印至所述衬底包括：
穿过所述多个沟槽的开口蚀刻所述第二间隔件层以暴露所述衬底；
穿过所述多个沟槽的开口蚀刻所述衬底；以及
在蚀刻后，去除所述第一间隔件层、所述第二间隔件层和所述图案化的材料层。
3.根据权利要求1所述的方法，其中，形成所述多条线包括：
在所述衬底上方形成光刻胶层；以及
利用所述第一掩模图案化所述光刻胶层。
4.根据权利要求1所述的方法，其中，形成所述多条线包括：
在所述衬底上方形成硬掩模层；
在所述硬掩模层上方形成光刻胶层；
利用所述第一掩模图案化所述光刻胶层；
将所述图案化的光刻胶层用作蚀刻掩模蚀刻所述硬掩模层；以及
之后去除所述图案化的光刻胶层。
5.根据权利要求1所述的方法，其中，形成所述第一间隔件层和所述第二间隔件层包括沉积。
6.根据权利要求1所述的方法，其中，形成所述图案化的材料层包括：
在所述第二间隔件层上方形成第一材料层；
在所述第一材料层和所述第二间隔件层上方形成第二材料层；
利用所述第二掩模图案化所述第二材料层；
将所述图案化的第二材料层用作蚀刻掩模蚀刻所述第一材料层；以及
之后去除所述图案化的第二材料层。
7.根据权利要求6所述的方法，还包括：
回蚀刻所述第一材料层从而在形成所述第二材料层之前暴露所述第二间隔件层。
8.根据权利要求6所述的方法，其中，图案化所述第二材料层使用光刻工艺，包括：
在所述第二材料层上方形成光刻胶层；
利用所述第二掩模图案化所述光刻胶层；
将所述图案化的光刻胶层用作蚀刻掩模蚀刻所述第二材料层；以及
之后去除所述图案化的光刻胶层。
9.根据权利要求6所述的方法，其中，蚀刻所述第一材料层包括选择性地调整为使用所述图案化的第二材料层作为蚀刻掩模来去除所述第一材料层而保留所述第二间隔件层的工艺。
10.根据权利要求1所述的方法，其中，去除所述第一间隔件层的至少一部分包括各向异性蚀刻工艺。
11.根据权利要求1所述的方法，其中，去除所述多条线包括等离子体蚀刻工艺。
12.根据权利要求1所述的方法，其中，所述多个沟槽的至少一个的尺寸由所述第一掩模的图案间隔和位于所述多条线的侧壁上方的所述第一间隔件层和所述第二间隔件层的厚度至少部分地限定。
13.一种形成用于集成电路的目标图案的方法，包括：
在衬底上方形成线，所述衬底具有多个硬掩模层；
在所述衬底上方、所述线上方和所述线的侧壁上将第一材料沉积至第一厚度；
去除所述线从而在所述衬底上方提供图案化的第一材料；
在所述衬底上方、所述图案化的第一材料上方和所述图案化的第一材料的侧壁上将第二材料沉积至第二厚度；
在所述第二材料上方沉积第三材料；以及
图案化所述第二材料和所述第三材料以形成沟槽，其中，所述第二材料保留在所述图案化的第一材料上方以及保留在所述图案化的第一材料的所述侧壁上；
穿过所述沟槽的开口蚀刻所述衬底。
14.根据权利要求13所述的方法，还包括，在沉积所述第一材料之前：
将所述线转印至所述硬掩模层中的一个。
15.根据权利要求13所述的方法，还包括，在所述去除所述线之前，去除所述第一材料的至少一部分以暴露所述线。
16.一种形成用于集成电路的目标图案的方法，所述方法包括：
将所述目标图案分解到至少第一掩模和第二掩模，所述第一掩模具有第一掩模图案，所述第二掩模具有第二掩模图案，其中，所述第一掩模图案的至少一部分与所述第二掩模图案的至少一部分重叠；
利用所述第一掩模图案化衬底从而形成多个第一部件；
在所述衬底上方、所述多个第一部件上方和所述多个第一部件的侧壁上形成第一间隔件层；
部分地去除所述第一间隔件层以暴露所述衬底和所述多个第一部件；
去除所述多个第一部件；
在所述衬底上方、所述第一间隔件层上方和所述第一间隔件层的侧壁上形成第二间隔件层；
在所述第二间隔件层上方形成第一材料层；以及
利用所述第二掩模图案化所述第一材料层，其中，所述第二间隔件层和所述图案化的第一材料层共同地限定多个第二部件。
17.根据权利要求16所述的方法，还包括：
在图案化所述第一材料层之前回蚀刻所述第一材料层以暴露所述第二间隔件层。
18.根据权利要求16所述的方法，还包括：
将所述多个第二部件转印至所述衬底；以及
之后去除所述图案化的第一材料层及所述第一间隔件层和所述第二间隔件层。
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| CN103137459A (zh) * | 2011-11-28 | 2013-06-05 | 格罗方德半导体公司 | 利用多侧壁图像转移技术在结构中图案化特征的方法 |
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| CN102239540A (zh) * | 2008-12-04 | 2011-11-09 | 美光科技公司 | 制造衬底的方法 |
| CN103137459A (zh) * | 2011-11-28 | 2013-06-05 | 格罗方德半导体公司 | 利用多侧壁图像转移技术在结构中图案化特征的方法 |
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| KR20150072362A (ko) | 2015-06-29 |
| US20150179435A1 (en) | 2015-06-25 |
| KR101670556B1 (ko) | 2016-10-28 |
| US9576814B2 (en) | 2017-02-21 |
| CN104733291A (zh) | 2015-06-24 |
| US10049919B2 (en) | 2018-08-14 |
| US20170162435A1 (en) | 2017-06-08 |
| US9136106B2 (en) | 2015-09-15 |
| US20160005617A1 (en) | 2016-01-07 |
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