KR101670556B1 - 집적 회로 패터닝 방법 - Google Patents

집적 회로 패터닝 방법 Download PDF

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KR101670556B1
KR101670556B1 KR1020140182998A KR20140182998A KR101670556B1 KR 101670556 B1 KR101670556 B1 KR 101670556B1 KR 1020140182998 A KR1020140182998 A KR 1020140182998A KR 20140182998 A KR20140182998 A KR 20140182998A KR 101670556 B1 KR101670556 B1 KR 101670556B1
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forming
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KR20150072362A (ko
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치에 한 우
충 주 리
쳉 슝 차이
밍 펭 시에
류 군 유
티엔 이 바오
샤우 린 슈
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Abstract

본 발명은 제1 마스크를 이용하여 복수의 라인을 기판 위에 형성하는 단계와, 기판 위에, 복수의 라인 위에 그리고 복수의 라인의 측벽 상에 제1 스페이서 층을 형성하는 단계를 포함하는 목표 패턴 형성 방법에 관한 것이다. 복수의 라인이 제거됨으로써, 패터닝된 제1 스페이서 층이 기판 위에 제공된다. 또한, 본 발명의 목표 패턴 형성 방법은 기판 위에, 패터닝된 제1 스페이서 층 위에 그리고 패터닝된 제1 스페이서 층의 측벽 상에 제2 스페이서 층을 형성하는 단계와, 제2 마스크를 이용하여 패터닝된 재료 층을 제2 스페이서 층 위에 형성하는 단계를 포함한다. 패터닝된 재료 층과 제2 스페이서 층은 총괄하여 복수의 트렌치를 형성한다.

Description

집적 회로 패터닝 방법{METHOD FOR INTEGRATED CIRCUIT PATTERNING}
본 발명은 집적 회로 패터닝 방법에 관한 것이다.
반도체 집적 회로(IC) 산업은 급격히 성장하고 있다. IC 재료 및 설계에 있어서의 기술적인 진보는 IC의 세대를 초래하였는데, 각각의 세대는 기존 세대보다 더 소형이고 더 복잡하다. IC 진화의 과정에서, 기능적 밀도(즉, 칩 영역 당 상호연결 디바이스의 개수)는 대체로 증가되면서 기하학적 크기[즉, 제조 공정을 이용하여 생성될 수 있는 최소 구성요소(또는 라인)]는 감소하고 있다. 이런 축소 공정은 통상 제조 효율의 상승 및 관련 비용의 감소에 의해 이익을 제공한다. 또한, 이런 축소 공정은 IC 처리 및 제조의 복잡성도 증가시키고 있는데, 실현되어야 하는 이런 진보를 위해서는 IC 처리 및 제조에 있어서의 유사한 발전도 요구된다.
본 발명의 목적은 개선된 집적 회로 패터닝 방법을 제공하는 것이다.
상술된 본 발명의 목적은 청구항에 개시된 본원 발명에 의해 달성된다.
본 발명에 따르면, 엔드 투 엔드 거리의 감소로 인해 패턴 밀도를 증가시킬 수 있다. 또한, 맨드릴 라인 트리밍 공정의 제거와 레지스트 층의 두께의 감소로 인해 비용을 절감할 수 있다.
도 1은 본 발명의 하나 이상의 실시예를 수행하기 위해 목표 패턴 또는 디바이스를 기판 상에 형성하는 방법의 흐름도.
도 2는 본 발명의 다양한 양태에 따른 예시적인 기판과, 기판 상부에 형성된 목표 패턴을 도시하는 도면.
도 3a 내지 도 14b는 본 발명의 실시예에 따라 도 1의 방법에 따른 도 2의 목표 패턴의 형성에 대한 상면도 및 단면도.
도 15는 본 발명의 다양한 양태에 따라 조정될 수 있는 다양한 치수를 갖는 최종 패턴을 도시하는 도면.
도 16a 내지 도 17b는 본 발명의 실시예에 따라 도 1의 방법에 따른 도 2의 목표 패턴을 위한 맨드릴 라인의 형성에 대한 상면도 및 단면도.
도 18a 및 도 18b는 본 발명의 실시예에 따라 도 1의 방법에 따른 도 2의 목표 패턴을 위한 트랜치의 형성에 대한 상면도 및 단면도.
본 발명의 양태들은 첨부된 도면을 참조하는 이하의 상세한 설명으로부터 가장 잘 이해될 것이다. 산업상의 표준 관행에 따라 다양한 도면들은 일정한 비율로 도시된 것은 아니다. 실제로, 다양한 구성요소들의 치수는 설명의 명료함을 위해 임의로 증감될 수도 있다.
이하의 상세한 설명은 본 발명의 다양한 구성요소를 실시하기 위한 다양한 실시예 또는 예를 제공한다. 구성요소 및 장치의 특정한 예들이 본 발명의 단순화를 위해 이하에 제공된다. 물론, 그런 예들은 예일 뿐 제한적인 것이 아니다. 또한, 본 발명은 다양한 예들에서 도면부호 및/또는 용어를 반복할 수도 있다. 그런 반복은 단순화와 명료함을 위한 것일 뿐, 개시된 다양한 실시예 및/또는 구성 사이의 관계를 자체로 나타내는 것이 아니다. 또한, 이하의 상세한 설명에서 제2 공정 이전의 제1 공정의 수행은 제2 공정이 제1 공정 직후에 수행되는 실시예, 또는 추가의 공정이 제1 공정과 제2 공정 사이에 수행되는 실시예도 포함할 수 있다. 다양한 구성요소들은 단순화와 명료함을 위해 다른 스케일로 임의로 도시될 수도 있다. 또한, 이하의 상세한 설명에서 제2 구성요소 위의 또는 상의 제1 구성요소의 형성은 제1 구성요소와 제2 구성요소가 직접 접촉되게 형성되는 실시예, 또는 제1 구성요소와 제2 구성요소가 직접 접촉되지 않도록 추가의 구성요소가 제1 구성요소와 제2 구성요소 사이에 형성되는 실시예도 포함할 수 있다.
또한, "아래" "하부" "위" "상부" 등과 같은 공간적으로 상대적인 용어들은 도면에 도시된 바와 같이 하나의 요소 또는 구성요소의 다른 요소(들) 또는 구성요소(들)에 대한 관계를 나타내기 위해 본 명세서에 사용될 수 있다. 공간적으로 상대적인 용어들은 도면에 도시된 배향 이외에도 사용시 장치의 다른 배향 또는 작업을 포함하는 것이다. 예컨대, 도면에 도시된 장치가 뒤집힌 경우, 다른 요소 "아래"에 있는 것으로 도시된 요소는 다른 요소 또는 구성요소 "위에" 배향될 수 있다. 따라서, 예시적인 용어 "아래"는 위 그리고 아래의 배향 양자 모두를 포함할 수 있다. 장치는 달리(90도로 회전되거나 다른 배향으로) 배향될 수도 있기 때문에, 본 명세서에 사용된 공간적으로 상대적인 기술 용어들은 유사하게 해석될 수도 있다.
본 발명은 전체적으로 193㎚ 침지 리소그래피 또는 다른 적절한 리소그래피 기술을 이용하여 14 나노미터(㎚), 10㎚ 등과 같이 후기 공정 노드에서 집적 회로 패턴 밀도를 향상시키기 위해 스페이서 기술을 이용하는 것에 관한 것이다. 하나의 스페이서 기술에서, 포토레지스트 재료가 기판 상에 패너팅된 후에 트리밍된다. 후속하여, 트리밍된 포토레지스트 패턴은 하부의 맨드릴 층(mandrel layer)으로 전사됨으로써 맨드릴 라인을 형성하고, 후속하여 트리밍된 포토레지스트 패턴이 제거된다. 스페이서가 맨드릴 라인의 측벽에 형성된다. 후속하는 스페이서 에칭 및 맨드릴 제거 공정으로 인해, 최종 패턴으로서 스페이서가 기판 상에 남겨진다. 최종 패턴의 피치는 포토레지스트 트리밍 공정으로 인해 감소되지만, 최종 패턴의 라인 엔드 투 엔드(end-to-end; EtE) 거리는 동일한 포토레지스트 트리밍 공정에 의해 바람직하지 않게 증가된다. 이는 측방향과 수직 방향에서의 포토레지스트 재료의 거의 동일한 에칭률에 의해 설명될 수 있다. 본 발명은 포토레지스트 트리밍 공정이 없는 경우에도 최종 패턴 밀도를 증가시키기 위해 이중 스페이서 공정을 이용한다. 본 발명의 이점은 최종 패턴의 피치, 라인 투 라인 간격 및 EtE 거리가 스페이서의 두께를 조절함으로써 유연하게 조정될 수 있다는 점이다.
도 1을 이제 참조하면, 본 발명의 다양한 양태에 따라 목표 패턴 또는 디바이스를 형성하기 위한 방법(100)의 흐름도가 도시되어 있다. 추가적인 작업이 방법(100) 이전에, 동안에 그리고 이후에 제공될 수 있으며, 개시된 몇몇 작업은 방법의 추가적인 실시를 위해 대체되거나, 제거되거나 이동될 수 있다. 방법(100)은 이하에서 추가로 기술될 것이다. 방법(100)은 예일 뿐, 첨부된 특허청구범위에 명시된 본 발명의 범주를 벗어나게 본 발명을 한정하는 것이 아니다.
도 2는 예시적인 목표 패턴(200)을 도시한다. 목표 패턴(200)은 2열로 배열된 조밀한 특징부(180a, 180b, 182a, 182b, 184a, 184b)와, 격리된 특징부(186)를 포함한다. 예시를 위해, "b" 특징부(180b, 182b, 184b)는 "a" 특징부(180a, 182a, 184a)와 각각 동일한 치수와 간격을 가지며, "a" 특징부와 "b" 특징부 양자 모두는 Y 방향으로 동일한 치수 L을 갖는다. "b" 특징부와 "a" 특징부 사이의 Y 방향으로서의 엔드 투 엔드 거리는 목표 패턴(200)의 임계 치수이다. 특징부(180a, 182a, 184a)는 X 방향으로 폭 W1, W2 및 W3을 각각 갖는다. 특징부(180a, 182a, 184a)는 간격 S1 및 S2에 의해 X 방향으로 이격되어 있다. 목표 패턴(200)은 집적 회로(IC)의 당양한 구성요소를 형성하는데 이용될 수 있다. 일 실시예에서, 목표 패턴(200)은 다층 상호연결 구조체에서 금속 라인을 형성하는데 이용된다. 다른 실시예에서, 목표 패턴(200)은 얕은 트렌치 격리(STI) 특징부를 위한 반도체 기판에서 복수의 트렌치를 형성하는데 이용된다. 집적 회로의 밀도가 증가됨에 따라, 몇몇 특징부들은 마스크(또는 포토 마스크)의 해상도에 비해 서로 너무 근접해있을 수도 있다. 이런 문제점을 극복하기 위해, 특징부(180a, 180b, 184a, 184b)에는 제1 마스크가 할당되고, 특징부(182a, 182b, 186)에는 제2 마스크가 할당된다. 이하에서 기술되는 바와 같이, 제2 마스크는 스페이서 자체 정렬 기술을 이용하여 어느 정도의 정확성으로 특징부(180a, 180b, 184a, 184b)에 중첩되는 패턴을 포함한다. 이런 점이 이하에서 상세히 기술될 것이다.
이하의 설명에서, 본 발명의 방법(100)(도 1 참조)은 목표 패턴(200)이 본 발명의 다양한 양태에 따른 제1 마스크 및 제2 마스크를 이용하여 형성되는 방법을 도시하는 도 3a 내지 도 17b를 참조하여 기술될 것이다. 각각의 도 3a 내지 도 18b에서, 접미사 "a"(예컨대, 도 3a 참조)가 표시된 도면은 접미사 "b" "c" 등(예컨대, 도 3b 참조)이 표시된 도면의 단면도를 나타내는 점선을 포함한다.
본 발명의 방법(100)(도 1 참조)은 작업 102에서 기판(202)을 수용한다. 도 3a 및 도 3b를 참조하면, 본 실시예에서 기판(202)은 재료 층(214, 216)을 포함한다. 재료 층(216)은 비정질 실리콘(a-Si), 실리콘 산화물, 실리콘 질화물(SiN), 또는 다른 적절한 재료 또는 조성물을 사용할 수 있다. 재료 층(214)은 무질소 반사방지 코팅(NFARC), 스핀 온 유리(SOG), 티타늄 질화물, 또는 다른 적절한 재료 또는 조성물을 사용할 수 있다. 재료 층(214, 216)은 다양한 공정에 의해 형성될 수 있다. 예컨대, 재료 층(214)은 퇴적과 같은 방법에 의해 다른 기판 위에 형성될 수 있다. 일 실시예에서, 재료 층(214)은 열산화에 의해 형성된 실리콘 산화물을 포함할 수 있다. 일 실시예에서, 재료 층(216)은 화학 증착(CVD)에 의해 형성된 SiN을 포함할 수 있다. 예컨대, 재료 층(216)은 헥사클로로디실란(HCD 또는 Si2Cl6), 디클로로실란(DCS 또는 SiH2Cl2), 비스(삼차부틸아미노) 실란(BTBAS 또는 C8H22N2Si), 및 디실란(DS 또는 Si2H6)을 포함하는 케미컬을 사용하는 CVD에 의해 형성될 수도 있다. 재료 층(214, 216)은 유사한 또는 상이한 방법에 의해 형성될 수도 있다. 상술된 재료 층(214, 216)의 예시적인 조성은 신규한 본 발명의 범주를 제한하는 것이 아니다.
본 발명의 방법(100)(도 1 참조)은 포토리소그래피 공정을 포함하는 공정과 같은 적절한 공정을 통해 제1 마스크를 이용하여 기판(202) 위에 맨드릴(mandrel) 라인을 형성함으로써 작업 104로 진행된다. 도 4a 및 도 4b를 참조하면, 맨드릴 라인(218a 내지 218d)은 기판(202) 위에 형성된다. 맨드릴 라인(218a 내지 218d) 각각은 특징부(180a, 180b, 184a, 184b)(도 2 참조)에 대응하는 제1 마스크에 피치 Pm를 갖고 형성된다. 맨드릴 라인(218a 내지 218c)(218b 내지 218d)은 X 방향으로의 제1 치수 W1m(W3m) 및 Y 방향으로의 제2 치수 Lm을갖는다. 치수 W1m, W3m 및 Lm은 각각 대응하는 치수 W1, W2 및 L(도 2 참조)보다 크다. 이런 점은 도 15를 참조하여 추후에 기술되는 부분에서 더 명확해질 것이다.
일 실시예에서, 맨드릴 라인(218a 내지 218d)은 포토리소그래피 공정에서 네가티브 또는 파지티브 레지스트(또는 포토레지스트) 재료에 형성된다. 예시적인 포토리소그래피 공정은 네가티브 레지스트 층(218)을 재료 층(216) 위에 코팅하는 단계와, 레지스트 층(218)을 소프트 베이킹하는 단계와, 제1 마스크를 이용하여 디프 자외선(DUV) 광에 레지스트 층(218)을 노출시키는 단계를 포함한다. 또한, 포토리소그래피 공정은 노출후 베이킹(PEB) 단계와, 현상 단계와, 하드 베이킹하여 레지스트 층(218)의 비노출 부분을 제거하고 레지스트 층(218)의 노출 부분을 맨드릴 라인(218a 내지 218d)으로서 기판(202) 상에 남겨두는 단계를 포함한다. 다른 실시예에서, 맨드릴 라인(218a 내지 218d)은 유사한 포토리소그래피 공정에서 파지티브 레지스트 재료 층의 비노출 부분에 의해 형성될 수도 있다.
다른 실시예에서, 맨드릴 라인(218a 내지 218d)은 에칭 공정이 뒤따라는 포토리소그래피 공정을 이용하여 하드 마스크 층에 형성될 수 있다. 도 16a 내지 도 17b를 참조하면, 하드 마스크 층[218(2), 217] 및 레지스트 층(219)이 재료 층(216) 위에 형성된다. 레지스트 층(219)은 상술된 포토리소그래피 공정과 같은 포토리소그래피 공정을 통해 제1 마스크를 이용하여 패터닝된다(도 16a 및 도 16b 참조). 하드 마스크 층(217)은 패터닝된 레지스트 층(219)의 개구를 통해 에칭되고, 후속하여 패터닝된 레지스트 층(219)이 습식 스트리핑(wet stripping) 또는 플라즈마 애싱(plasma ashing)과 같은 적절한 공정을 이용하여 제거된다. 후속하여, 하드 마스크 층[218(2)]이 패터닝된 하드 마스크 층(217)을 에칭 마스크로서 이용하여 에칭된 다음, 하드 마스크 층(217)이 제거되어 하드 마스크 층[218(2)]에 맨드릴 라인(218a 내지 218d)이 남겨진다. 일례에서, 하드 마스크 층(217)을 에칭하는 단계는 패터닝된 레지스트 층(219)의 개구 내의 하드 마스크 층(217)을 제거하기 위해 건식(또는 플라즈마) 에칭을 적용하는 단계를 포함한다. 예컨대, 건식 에칭 공정은 산소 함유 가스, 플루오르 함유 가스(예컨대, CF4, SF6, CH2F2, CHF3 및/또는 C2F6), 염소 함유 가스(예컨대, Cl2, CHCl3, CCl4 및/또는 BCl3), 브롬 함유 가스(예컨대, HBr 및/또는 CHBR3), 요오드 함유 가스, 다른 적절한 가스 및/또는 플라즈마, 및/또는 이들의 조합물을 이용할 수도 있다. 하드 마스크 층[218(2)]은 유사한 또는 다른 에칭 공정을 이용하여 에칭될 수도 있다.
본 발명의 방법(100)(도 1 참조)은 기판(202) 위에 그리고 맨드릴 라인(218a 내지 218d) 위로 걸쳐 제1 스페이서 층(220)을 형성함으로써 작업 106으로 진행된다. 도 5a 및 도 5b를 참조하면, 제1 스페이서 층(220)은 기판(202) 위에, 보다 구체적으로는 재료 층(216) 위에 형성된다. 또한, 제1 스페이서 층(220)은 맨드릴 라인(218a 내지 218d) 위에 그리고 맨드릴 라인(218a 내지 218d)의 측벽 상에 형성된다. 제1 스페이서 층(220)은 제1 두께 T1을 갖는다. 제1 스페이서 층(220)은 재료 층(216)과 맨드릴 라인(218a 내지 218d)과 상이한 하나 이상의 재료 또는 조성물을 포함한다. 일 실시예에서, 제1 스페이서 층(220)은 티타늄 질화물, 실리콘 질화물, 실리콘 산화물 또는 티타늄 산화물과 같은 유전체 재료를 포함할 수도 있다. 제1 스페이서 층(220)은 퇴적 공정과 같은 적절한 공정에 의해 형성될 수 있다. 예컨대, 퇴적 공정은 화학 증착(CVD) 공정 또는 물리 증착(PVD) 공정을 포함한다.
본 발명의 방법(100)(도 1 참조)은 맨드릴 라인(218a, 218b)과 재료 층(216)을 노출시키기 위해 제1 스페이서 층(220)을 에칭함으로써 작업 108로 진행된다. 도 6a 및 도 6b를 참조하면, 맨드릴 라인(218a, 218b)의 상부면이 이 에칭 공정에 의해 노출되고 그리고 재료 층(216) 위에 배치된 제1 스페이서 재료가 또한 부분적으로 제거되어, 맨드릴 라인(218a 내지 218d)의 측벽 상에 제1 스페이서 특징부(220a 내지 220d)를 각각 제공한다. 일 실시예에서, 제1 스페이서 층(220)의 에칭 공정은 플라즈마 에칭과 같은 이방성 에칭을 포함한다.
본 발명의 방법(100)(도 1 참조)은 맨드릴 라인(218a 내지 218d)을 제거함으로써 작업 110으로 진행된다. 도 7a 내지 도 7b를 참조하면, 맨드릴 라인(218a 내지 218d)이 제거되어, 제1 스페이서 특징부(220a 내지 220d)가 기판(202) 위에 남겨진다. 맨드릴 라인(218a 내지 218d)은 맨드릴 라인(218a 내지 218d)을 선택적으로 제거하도록 조정되는 공정을 이용하여 제거되지만, 제1 스페이서 특징부(220a 내지 220d)는 남겨진다.
본 발명의 방법(100)(도 1 참조)은 기판(202) 위에 그리고 제1 스페이서 특징부(220a 내지 220d) 위로 걸쳐 제2 스페이서 층(222)을 형성함으로써 작업 112로 진행된다. 도 8a 및 도 8b를 참조하면, 제2 스페이서 층(222)은 기판(202) 위에, 보다 구체적으로는 재료 층(216) 위에 형성된다. 또한, 제2 스페이서 층(222)은 제1 스페이서 특징부(220a 내지 220d) 위에 그리고 제1 스페이서 특징부(220a 내지 220d)의 측벽 상에 형성된다. 제2 스페이서 층(222)은 제2 두께 T2를 갖는다. 제2 스페이서 층(222)은 재료 층(216)과 상이한 하나 이상의 재료 또는 조성물을 포함한다. 제2 스페이서 층(222)은 제1 스페이서 층(220)과 동일한 또는 상이한 재료나 조성물을 사용할 수도 있다. 그러나, 2개의 스페이서 층(220, 222)에 사용된 재료는 2개의 스페이서 층이 후속 단계에서 에칭될 때 바람직하지 않은 마이크로 트렌치의 형성을 방지하기 위해 유사한 에칭 선택도를 가질 수 있다. 일 실시예에서, 제2 스페이서 층(222)은 티타늄 질화물, 실리콘 질화물, 실리콘 산화물 또는 티타늄 산화물과 같은 유전체 재료를 포함할 수도 있다. 제2 스페이서 층(222)은 퇴적 공정과 같은 적절한 공정에 의해 형성될 수 있다. 예컨대, 퇴적 공정은 화학 증착(CVD) 공정 또는 물리 증착(PVD) 공정을 포함한다.
본 발명의 방법(100)(도 1 참조)은 제2 스페이서 층(222) 위에 다른 재료 층을 형성함으로써 작업 114로 진행된다. 도 9a 및 도 9b를 참조하면, 재료 층(224)은 기판(202) 위에 그리고 제2 스페이서 층(222) 위에 형성된다. 일 실시예에서, 재료 층(224)은 처음에 제2 스페이서 층(222) 위에 퇴적된 다음, 제1 스페이서 특징부(220a 내지 220d)의 상부면 위의 제2 스페이서 층(222)이 노출되도록 부분적으로 제거된다. 재료 층(224)의 부분적인 제거는 화학 기계적 연마(CMP) 또는 에칭 백(etch back)과 같은 방법에 의해 수행될 수도 있다. 일 실시예에서, 재료 층(224)은 하부 반사 방지 코팅(BARC) 또는 스핀 온 유리(SOG)를 사용한다.
본 발명의 방법(100)(도 1 참조)은 제2 마스크를 이용하여 재료 층(224) 및 제2 스페이서 층(222) 상에 트렌치를 형성함으로써 작업 116으로 진행된다. 이 작업은 퇴적 공정, 리소그래피 공정 및 에칭 공정과 같은 다양한 공정을 포함한다. 이 작업은 도 10a 내지 도 11b, 및 도 18a와 도 18b를 참조하여 기술될 것이다.
도 10a 및 도 10b를 참조하면, 재료 층(226)이 제2 스페이서 층(222)과 재료 층(224) 위에 퇴적된다. 연마 공정이 재료 층(226)에 후속적으로 수행될 수도 있다. 하드 마스크 층(228)이 재료 층(226) 위에 퇴적된다. 일 실시예에서, 재료 층(226)은 하부 반사 방지 코팅(BARC) 층일 수 있지만, 하드 마스크 층(228)은 실리콘으로 제조될 수 있다. 다른 실시예에선, 2개의 재료 층(226, 228)을 사용하는 대신 하나의 재료 층이 사용될 수 있다. 레지스트 층(230)이 하드 마스크 층(228) 상에 형성되고, 리소그래피 공정을 이용하여 트렌치로서의 제2 마스크를 사용하여 패터닝된다. 본 실시예에서, 제2 마스크는 트렌치로서의 3개의 패턴(230a, 230b, 230g)을 포함한다. 패턴(230a)은 제1 스페이서 특징부(220a, 220b)와 중첩됨으로써, 특징부(180a, 182a, 184a)(도 2 참조)를 위한 트렌치를 형성한다. 패턴(230b)은 제1 스페이서 특징부(220c, 220d)와 중첩됨으로써, 특징부(180b, 182b, 184b)(도 2 참조)를 위한 트렌치를 형성한다. 이런 트렌치의 형성은 맨드릴 라인(218a 내지 218d)(도 4a 참조)의 치수와 피치, 제1 두께 T1(도 5b 참조), 및 제2 두께 T2(도 8b 참조)에 기인한다. 이런 점은 도 15를 참조하여 상세히 기술될 것이다. 본 실시예에서, 제1 스페이서 특징부(220a, 220b) 위에 배치된 제2 스페이서 층(222)의 외부면들 사이의 간격은 특징부(182)의 폭 W2와 동일하게 되도록 조정된다. 도 18a 및 도 18b에 도시된 다른 실시예에서, 제1 스페이서 특징부(220a, 220b) 위에 배치된 제2 스페이서 층(222)의 외부면들 사이의 간격이 W2보다 큰 경우, 제2 마스크는 6개의 패턴(230a 내지 230f)을 포함한다. 이와 관련하여, 도 10a는, 도 18a의 패턴(230a 내지 230c)이 도 10a의 패턴(230a)으로 통합되고 도 18a의 패턴(230d 내지 230f)이 도 10a의 패턴(230b)로 통합된, 도 18a의 특별한 경우의 도면일 수 있다.
도 10c를 참조하면, 하드 마스크 층(228)은 패터닝된 레지스트 층(230)의 개구를 통한 에칭에 의해 패터닝된다. 일례에서, 에칭 공정은 패터닝된 레지스트 층(230)의 개구 내의 하드 마스크 층(228)을 제거하기 위해 건식(또는 플라즈마) 에칭을 적용하는 단계를 포함한다. 예컨대, 건식 에칭 공정은 산소 함유 가스, 플루오르 함유 가스(예컨대, CF4, SF6, CH2F2, CHF3 및/또는 C2F6), 염소 함유 가스(예컨대, Cl2, CHCl3, CCl4 및/또는 BCl3), 브롬 함유 가스(예컨대, HBr 및/또는 CHBR3), 요오드 함유 가스, 다른 적절한 가스 및/또는 플라즈마, 및/또는 이들의 조합물을 이용할 수도 있다. 일 실시예에서, 하드 마스크 층(228)이 패터닝된 후에, 패터닝된 레지스트 층(230)이 습식 스트리핑 또는 플라즈마 애싱과 같은 적절한 공정을 이용하여 제거되거나 부분적으로 제거된다.
도 10d를 참조하면, 하드 마스크 층(228)이 패터닝된 후에, 재료 층(226, 224)은 재료 층(226, 224)을 선택적으로 제거하도록 조정되는 에칭 공정과 같은 적절한 공정을 이용하여 에칭 마스크로서의 패터닝된 하드 마스크 층(228)을 사용하여 에칭되지만, 제2 스페이서 층(222)은 남겨진다. 일 실시예에서, 하드 마스크 층(228)의 패터닝 단계 이후의 레지스트 층(230)의 임의의 잔류 부분도 또한 그런 에칭 공정에 의해 제거된다. 일 실시예에서, 재료 층(226, 224)의 패터닝 단계 이후의 하드 마스크 층(228)의 임의의 잔류 부분도 또한 그런 에칭 공정에 의해 제거된다. 후속하여, 재료 층(228, 226)이 재료 층(228, 226)을 선택적으로 제거하도록 조정되는 에칭 공정과 같은 적절한 공정을 이용하여 제거되지만, 재료 층(224)과 제2 스페이서 층(222)은 남겨진다.
도 11a 및 도 11b를 참조하면, 트렌치(232a 내지 232g)가 상술된 에칭 공정에 의해 재료 층(224)과 제2 스페이서 층(222)에 형성된다.
본 발명의 방법(100)(도 1 참조)은 재료 층(216)을 노출시키기 위해 제2 스페이서 층(222)을 에칭함으로써 작업 118로 진행된다. 도 12a 및 도 12b를 참조하면, 재료 층(216) 위에 배치된 제2 스페이서 층이 트렌치(232a 내지 232g)의 바닥부에서 제거된다. 또한, 제1 스페이서 특징부(220a 내지 220d)도 에칭 공정에 의해 노출되고 부분적으로 제거될 수 있다. 재료 층(224)은 에칭 공정에 의해 부분적으로 제거될 수 있다. 일 실시예에서, 제2 스페이서 층의 에칭 공정은 플라즈마 에칭과 같은 이방성 에칭을 포함한다. 작업 118의 결과로서, 제1 및 제2 스페이서 층(220, 222)과 재료 층(224)이 목표 패턴(200)(도 2 참조)의 특징부(180a, 180b, 182a, 182b, 184a, 184b, 186)에 대응하는 복수의 개구로 패터닝된다.
본 발명의 방법(100)(도 1 참조)은 이방성 에칭과 같은 적절한 공정을 이용하여 스페이서 층(220, 222)과 재료 층(224)으로부터의 패턴을 재료 층(216)(도 13a 및 도 13b)으로 전사함으로써 작업 120으로 진행된다. 후속하여, 스페이서 층(220, 222)과 재료 층(224)이 제거된다(도 14a 및 도 14b 참조). 도 14a 및 도 14b를 참조하면, 목표 패턴(200)(도 2 참조)과 일치하는 패턴이 재료 층(216)에 형성된다.
본 발명의 방법(100)(도 1 참조)은 패터닝된 재료 층(216)을 이용하여 최종 패턴 또는 디바이스를 형성하기 위해 작업 122로 진행된다. 일 실시예에서, 목표 패턴은 다층 상호연결 구조의 금속 라인으로서 형성될 것이다. 예컨대, 금속 라인은 내부층 유전체(ILD) 층에 형성될 수도 있다. 이런 경우, 작업 122에서, 패터닝된 재료 층(216)을 이용하여 ILD 층에 복수의 트렌치를 형성하고, 금속과 같은 전도성 재료로 트렌치를 충전하고, 패터닝된 ILD 층을 노출시키기 위해 화학 기계적 연마와 같은 공정을 이용하여 전도성 재료를 연마함으로써, ILD 층에 금속 라인을 형성한다.
다른 실시예에서, 작업 122에서, 패터닝된 재료 층(216)을 이용하여 반도체 기판 상에 핀 구조 전계 효과 트랜지스터(FinFET) 구조를 형성한다. 이 실시예에서는, 작업 122에서 반도체 기판에 복수의 트렌치를 형성한다. 또한, 유전체 재료로 트렌치를 충전하기 위한 퇴적 단계와, 초과 유전체 재료를 제거하고 반도체 기판의 상부면을 평탄화하기 위한 (CMP와 같은)연마 단계를 포함하는 방법에 의해 얕은 트렌치 격리(STI) 특징부가 트렌치에 형성된다. 후속하여, STI 특징부를 리세싱하여(recess) 핀형(fin-like) 활성 구역을 형성하기 위해 선택적 에칭 공정이 유전체 재료에 적용된다.
도 15는 목표 패턴(200)(도 2 참조)의 다양한 치수, 맨드릴 라인(218a 내지 218d)(도 4a 참조)의 다양한 치수, 제1 스페이서 층(220)(도 5b 참조)의 두께 T1, 및 제2 스페이서 층(222)(도 8b 참조)의 두께 T2 사이의 관계를 도시한다. 도 13a의 시계방향으로 90도 회전된 부분도일 수 있는 도 15를 참조하면, 상술된 다양한 치수들은 다음과 같다.
Lm = L + 2 × T2 (1)
W1m = W1 + 2 × T2 (2)
W3m = W3 + 2 × T2 (3)
Pm = W1 + W2 + 2 × T1 + 4 × T2 (4)
S1 ≥ T1 + 2 × T2 (5)
S2 ≥ T1 + 2 × T2 (6)
EtE = EtEm + 2 × T2 (7)
본 발명은 스페이서가 패턴 위에 형성되기 전에 패턴이 트리밍되는 종래의 스페이서 기술에 비해 다양한 이점을 제공한다. 하나의 이점은 더 작은 EtE가 두께 T2의 조정에 의해 달성될 수 있다는 것이다. 예로서, 종래의 스페이서 기술을 이용하는 공정 P에 있어서, 맨드릴 라인(218a 내지 218d)의 폭은 폭이 최종 패턴 피치를 충족시키도록 트리밍 공정에서 T만큼 감소된다. 또한, 맨드릴 라인(218a 내지 218d)의 길이도 동일한 트리밍 공정에 의해 대략 T만큼 감소된다. 따라서, 맨드릴 라인(218a 내지 218d) 사이의 엔드 투 엔드 거리는 EtEm에서 공정 P에 의해 최종 패턴의 엔드 투 엔드 거리와 거의 동일해지는 (EtEm + 2 × T)로 증가된다. 대조적으로, 본 실시예에서, 두께 T2는 T보다 작아지도록 조정될 수 있는데, 이는 최종 패턴의 엔드 투 엔드 거리를 간접적으로 감소시킨다[상술된 등식(7) 참조]. 감소된 EtE 거리 이외에도, 목표 패턴(200)의 특징부(180a, 180b, 182a, 182b, 184a, 184b)의 폭과 길이, 및 특징부(180a, 180b, 182a, 182b, 184a, 184b) 사이의 간격이 두께 T1 및 T2의 조정에 의해 더 작아질 수 있다. 이는 일반적으로 패턴 밀도를 증가시키는 이점이 있다. 본 발명의 다른 이점은 (1) 본 발명의 실시예는 맨드릴 라인 트리밍 공정이 제거되고 (2) 레지스트 층(218)(도 4b 참조)이 더 얇아질 수 있기 때문에 비용이 절감된다.
당업자들이 본 발명의 양태를 더 잘 이해할 수 있도록 몇몇 실시예에 대한 상술된 구성요소가 개시되어 있다. 당업자들은 본 명세서에 개시된 실시예의 동일한 목적 및/또는 이점을 달성하기 위해 다른 공정 및 구조를 설계하거나 변경하기 위한 기초로서 본 명세서의 내용을 용이하게 이용할 수 있을 것이다. 또한, 당업자들은 그런 등가 구성들은 본 발명의 기술 사상 및 범주를 벗어나지 않음을 알 것이며, 본 발명의 기술 사상 및 범주 내에서 다양한 변형예, 대체예 및 변경예를 실시할 수 있을 것이다.
본 발명의 예시적인 일 양태는 집적 회로(IC)를 위한 목표 패턴을 형성하는 방법에 관한 것이다. 본 발명의 방법은 제1 마스크를 이용하여 복수의 라인을 기판 위에 형성하는 단계와; 기판 위에, 복수의 라인 위에 그리고 복수의 라인의 측벽 상에 제1 스페이서 층을 형성하는 단계와; 복수의 라인을 노출시키기 위해 제1 스페이서 층의 적어도 일부를 제거하는 단계와; 복수의 라인을 제거함으로써 패터닝된 제1 스페이서 층을 기판 위에 제공하는 단계와; 기판 위에, 패터닝된 제1 스페이서 층 위에 그리고 패터닝된 제1 스페이서 층의 측벽 상에 제2 스페이서 층을 형성하는 단계와; 제2 마스크를 이용하여 패터닝된 재료 층을 제2 스페이서 층 위에 형성하는 단계를 포함하며, 패터닝된 재료 층과 제2 스페이서 층은 총괄하여 복수의 트렌치를 형성한다.
본 발명의 예시적인 다른 양태는 복수의 하드 마스크 층을 갖는 기판 위에 패턴을 형성하는 방법에 관한 것이다. 본 발명의 방법은 라인을 기판 위에 형성하는 단계와; 기판 위에, 라인들 위에 그리고 라인들의 측벽 상에 제1 재료를 제1 두께로 퇴적하는 단계와; 라인들을 제거함으로써 패터닝된 제1 재료를 기판 위에 제공하는 단계와; 기판 위에, 패터닝된 제1 재료 위에 그리고 패터닝된 제1 재료의 측벽 상에 제2 재료를 제2 두께로 퇴적하는 단계와; 제3 재료를 제2 재료 위에 퇴적하는 단계와; 트렌치를 형성하기 위해 제2 재료와 제3 재료를 패터닝하는 단계를 포함한다.
본 발명의 예시적인 또 다른 양태는 집적 회로를 위한 목표 패턴을 형성하는 방법에 관한 것이다. 본 발명의 방법은 목표 패턴을 적어도 제1 마스크 패턴을 갖는 제1 마스크 및 제2 마스크 패턴을 갖는 제2 마스크로 분해하는 단계를 포함하며, 제1 마스크 패턴의 적어도 일부는 제2 마스크 패턴의 적어도 일부와 중첩된다. 또한, 본 발명의 방법은 제1 마스크를 이용하여 기판을 패터닝함으로써 제1의 복수의 특징부를 형성하는 단계와; 기판 위에, 제1의 복수의 특징부 위에 그리고 제1의 복수의 특징부의 측벽 상에 제1 스페이서 층을 형성하는 단계와; 기판과 제1의 복수의 특징부를 노출시키기 위해 제1 스페이서 층을 부분적으로 제거하는 단계와; 제1의 복수의 특징부를 후속적으로 제거하는 단계를 포함한다. 또한, 본 발명의 방법은 기판 위에, 제1 스페이서 층 위에 그리고 제1 스페이서 층의 측벽 상에 제2 스페이서 층을 형성하는 단계와; 제1 재료 층을 제2 스페이서 층 위에 형성하는 단계와; 제2 마스크를 이용하여 제1 재료 층을 패터닝하는 단계를 포함하며, 제2 스페이서 층과 패터닝된 제1 재료 층은 총괄하여 제2의 복수의 특징부를 형성한다.
200 : 목표 패턴
180a, 180b, 182a, 182b, 184a, 184b : 특징부
202 : 기판
214, 216 : 재료 층
220 : 제1 스페이서 층
222; : 제2 스페이서 층
218a, 218b, 218c, 218d : 맨드릴 라인

Claims (20)

  1. 집적 회로를 위한 목표 패턴을 형성하는 방법으로서,
    제1 마스크를 이용하여 복수의 라인을 기판 위에 형성하는 단계와,
    상기 기판 위에, 상기 복수의 라인 위에 그리고 상기 복수의 라인의 측벽 상에 제1 스페이서 층을 형성하는 단계와,
    상기 복수의 라인을 노출시키기 위해 상기 제1 스페이서 층의 적어도 일부를 제거하는 단계와,
    상기 복수의 라인을 제거함으로써 패터닝된 제1 스페이서 층을 상기 기판 위에 제공하는 단계와,
    상기 기판 위에, 상기 패터닝된 제1 스페이서 층 위에 그리고 상기 패터닝된 제1 스페이서 층의 측벽 상에 제2 스페이서 층을 형성하는 단계와,
    제2 마스크를 이용하여 패터닝된 재료 층을 상기 제2 스페이서 층 위에 형성하는 단계를 포함하며,
    상기 패터닝된 재료 층과 제2 스페이서 층은 총괄하여 복수의 트렌치를 형성하고,
    복수의 트렌치들이 정의되고 난 이후에 상기 패터닝된 제1 스페이서 층 위에 그리고 상기 패터닝된 제1 스페이서 층의 상기 측벽 상에 상기 제2 스페이서 층이 형성된 채로 남아있는 것인
    목표 패턴 형성 방법.
  2. 제1항에 있어서, 상기 복수의 트렌치를 상기 기판으로 전사하는 단계를 더 포함하는 목표 패턴 형성 방법.
  3. 제1항에 있어서, 상기 기판을 노출시키기 위해 상기 복수의 트렌치의 개구를 통해 상기 제2 스페이서 층을 에칭하는 단계와,
    상기 복수의 트렌치의 개구를 통해 상기 기판을 에칭하는 단계와,
    상기 에칭하는 단계 후에, 상기 제1 스페이서 층, 제2 스페이서 층 및 패터닝된 재료 층을 제거하는 단계를 더 포함하는 목표 패턴 형성 방법.
  4. 제1항에 있어서, 상기 복수의 라인을 형성하는 단계는,
    레지스트 층을 상기 기판 위에 형성하는 단계와,
    상기 제1 마스크를 이용하여 상기 레지스트 층을 패터닝하는 단계를 포함하는 것인 목표 패턴 형성 방법.
  5. 제1항에 있어서, 상기 복수의 라인을 형성하는 단계는,
    하드 마스크 층을 상기 기판 위에 형성하는 단계와,
    레지스트 층을 상기 하드 마스크 층 위에 형성하는 단계와,
    상기 제1 마스크를 이용하여 상기 레지스트 층을 패너팅하는 단계와,
    에칭 마스크로서 상기 패터닝된 레지스트 층을 이용하여 상기 하드 마스크 층을 에칭하는 단계와,
    상기 패터닝된 레지스트 층을 후속적으로 제거하는 단계를 포함하는 것인 목표 패턴 형성 방법.
  6. 제1항에 있어서, 상기 제1 스페이서 층과 제2 스페이서 층을 형성하는 단계는 퇴적 단계를 포함하는 것인 목표 패턴 형성 방법.
  7. 제1항에 있어서, 상기 패터닝된 재료 층을 형성하는 단계는,
    제1 재료 층을 상기 제2 스페이서 층 위에 형성하는 단계와,
    제2 재료 층을 상기 제1 재료 층과 제2 스페이서 층 위에 형성하는 단계와,
    상기 제2 마스크를 이용하여 상기 제2 재료 층을 패터닝하는 단계와,
    에칭 마스크로서 상기 패터닝된 제2 재료 층을 이용하여 상기 제1 재료 층을 에칭하는 단계와,
    상기 제2 재료 층을 후속적으로 제거하는 단계를 포함하는 것인 목표 패턴 형성 방법.
  8. 제1항에 있어서, 상기 복수의 트렌치의 적어도 하나의 치수는 상기 제1 마스크의 패턴 간격과, 상기 복수의 라인의 측벽 위의 제1 및 제2 스페이서 층의 두께에 의해 적어도 부분적으로 결정되는 것인 목표 패턴 형성 방법.
  9. 복수의 하드 마스크 층을 갖는 기판 위에 라인들을 형성하는 단계와,
    상기 기판 위에, 상기 라인들 위에 그리고 상기 라인들의 측벽 상에 제1 재료를 제1 두께로 퇴적하는 단계와,
    상기 라인들을 제거함으로써 패터닝된 제1 재료를 상기 기판 위에 제공하는 단계와,
    상기 기판 위에, 상기 패터닝된 제1 재료 위에 그리고 상기 패터닝된 제1 재료의 측벽 상에 제2 재료를 제2 두께로 퇴적하는 단계와,
    제3 재료를 상기 제2 재료 위에 퇴적하는 단계와,
    트렌치를 형성하기 위해 상기 제2 재료와 제3 재료를 패터닝하는 단계를 포함하고,
    상기 제2 재료는 상기 패터닝된 제1 재료 위에 그리고 상기 패터닝된 제1 재료의 상기 측벽 상에 퇴적된 채로 남아있는 것인 방법.
  10. 집적 회로를 위한 목표 패턴을 형성하는 방법으로서,
    상기 목표 패턴을 적어도 제1 마스크 패턴을 갖는 제1 마스크 및 제2 마스크 패턴을 갖는 제2 마스크로 분해하는 단계로서, 상기 제1 마스크 패턴의 적어도 일부는 상기 제2 마스크 패턴의 적어도 일부와 중첩되는 것인 분해 단계와,
    상기 제1 마스크를 이용하여 기판을 패터닝함으로써 제1의 복수의 특징부를 형성하는 단계와,
    상기 기판 위에, 상기 제1의 복수의 특징부 위에 그리고 상기 제1의 복수의 특징부의 측벽 상에 제1 스페이서 층을 형성하는 단계와,
    상기 기판과 제1의 복수의 특징부를 노출시키기 위해 상기 제1 스페이서 층을 부분적으로 제거하는 단계와,
    상기 제1의 복수의 특징부를 제거하는 단계와,
    상기 기판 위에, 상기 제1 스페이서 층 위에 그리고 상기 제1 스페이서 층의 측벽 상에 제2 스페이서 층을 형성하는 단계와,
    제1 재료 층을 상기 제2 스페이서 층 위에 형성하는 단계와,
    상기 제2 마스크를 이용하여 상기 제1 재료 층을 패터닝하는 단계를 포함하며,
    상기 제2 스페이서 층과 패터닝된 제1 재료 층은 총괄하여 제2의 복수의 특징부를 형성하고,
    상기 제2의 복수의 특징부들이 정의되고 난 이후에 상기 패터닝된 제1 스페이서 층 위에 그리고 상기 패터닝된 제1 스페이서 층의 상기 측벽 상에 상기 제2 스페이서 층이 형성된 채로 남아있는 것인
    목표 패턴 형성 방법.
  11. 삭제
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  18. 삭제
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  20. 삭제
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