TW201601257A - 靜態隨機存取記憶體的鰭式場效電晶體元件與其製備方法 - Google Patents

靜態隨機存取記憶體的鰭式場效電晶體元件與其製備方法 Download PDF

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TW201601257A
TW201601257A TW104100556A TW104100556A TW201601257A TW 201601257 A TW201601257 A TW 201601257A TW 104100556 A TW104100556 A TW 104100556A TW 104100556 A TW104100556 A TW 104100556A TW 201601257 A TW201601257 A TW 201601257A
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layer
germanium
fin structure
fin
effect transistor
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TW104100556A
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TWI567875B (zh
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江國誠
馮家馨
吳志強
迪亞玆 卡羅司
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台灣積體電路製造股份有限公司
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Abstract

一種半導體元件，包含一第一鰭狀結構，位於一基板的一N型鰭式場效電晶體區域之上。第一鰭狀結構包含一矽層，一矽化鍺氧化層位於矽層上以及一鍺特徵結構位於矽化鍺氧化層上。半導體元件更包含一第二鰭狀結構，位於基板的一P型鰭式場效電晶體區域之上，第二鰭狀結構包含矽層，矽化鍺氧化層位於矽層之上，一矽化鍺磊晶層位於矽化鍺氧化層上以及鍺特徵結構位於矽化鍺磊晶層上。

Description

靜態隨機存取記憶體的鰭式場效電晶體元件與其製備方法
本發明係有關於一種半導體結構，且特別有關於一種鰭式場效電晶體元件結構。
半導體積體電路(IC)產業經歷高速的成長。積體電路之材料及設計方面的技術進步已創造數個世代的積體電路，每一代的積體電路都具有比前一代更小且更複雜的電路。在積體電路演進的過程中，特徵結構密度(亦即，每晶片面積中相互連接的元件之數目)通常隨著幾何尺寸(亦即，所使用之製造方法可產生的最小組件或線路)的縮小而增加。這種尺寸縮減的製程將的優點在於提高生產效率.以及降低相關成本。
尺寸的縮減同時也提升加工及製造積體電路的複雜性，為了實現這些進步，在積體電路加工及製造方面需要類似的發展。舉例而言，一種三維電晶體，例如鰭式場效電晶體(fin-like field-effect transistor,FinFET)，已被導 入用以取代平面電晶體(planar transistor)。雖然現有的鰭式場效電晶體元件及其製造方法已普遍足以達成預期的目標，然而卻無法完全滿足所有需求。
本發明之一態樣係提供一種半導體元件，包含一第一鰭狀結構，其位於一基板的一N型鰭式場效電晶體區域之上。第一鰭狀結構包含一矽層，一矽化鍺氧化層位於矽層上，以及一鍺特徵結構位於矽化鍺氧化層上。半導體元件更包含一第二鰭狀結構，位於基板的一P型鰭式場效電晶體區域之上，第二鰭狀結構包含矽層，矽化鍺氧化層位於矽層之上，一矽化鍺磊晶層位於矽化鍺氧化層上，以及鍺特徵結構位於矽化鍺磊晶層上。
根據本發明一或多個實施方式，一高介電常數介電層/金屬閘極堆疊位於基板的N型鰭式場效電晶體區域之上，並包覆第一鰭狀結構一部分的上方部分，以及一第一源/汲極特徵結構位於第一鰭狀結構上方部分的一凹陷上，且高介電常數介電層/金屬閘極堆疊分隔第一源/汲極特徵結構。
根據本發明一或多個實施方式，其中第一源/汲極特徵結構包含磷化矽鍺。
根據本發明一或多個實施方式，一高介電常數介電層/金屬閘極堆疊位於基板的P型鰭式場效電晶體區域之上，並包覆第二鰭狀結構一部分的上方部分，以及一第二 源/汲極特徵結構位於第二鰭狀結構上方部分的一凹陷上，且高介電常數介電層/金屬閘極堆疊分隔第二源/汲極特徵結構。
根據本發明一或多個實施方式，其中第二源/汲極特徵結構包含硼化鍺錫。
本發明之一態樣係提供一種鰭狀場效電晶體元件，包含一第一鰭狀結構，位於一基板的一N型鰭式場效電晶體區域之上。第一鰭狀結構包含一鍺特徵結構作為上方部分，一矽化鍺氧化層作為中間部分以及一矽層作為下方部分。鰭狀場效電晶體元件更包含一第二鰭狀結構，位於基板的一P型鰭式場效電晶體區域之上。第二鰭狀結構包含鍺特徵結構作為上方部分，一矽化鍺磊晶層作為中間部分以及矽層作為下方部分。一高介電常數介電層/金屬閘極堆疊位於基板的N型鰭式場效電晶體區域之上，並包覆第一鰭狀結構一部分的上方部分，以及一第一源/汲極特徵結構位於第一鰭狀結構上方部分的一凹陷上，且高介電常數介電層/金屬閘極堆疊分隔第一源/汲極特徵結構。高介電常數介電層/金屬閘極堆疊也位於基板的P型鰭式場效電晶體區域之上，並包覆第二鰭狀結構一部分的上方部分，以及一第二源/汲極特徵結構位於第二鰭狀結構上方部分的一凹陷上，且高介電常數介電層/金屬閘極堆疊分隔第二源/汲極特徵結構。
根據本發明一或多個實施方式，其中第一源/汲極特徵結構包含磷化矽鍺。
根據本發明一或多個實施方式，第二源/汲極特徵結構包含硼化鍺錫。
本發明之一態樣係提供一種形成半導體元件之方法，包含形成一鰭狀結構於一基板上，鰭狀結構包含一第一半導體材料層作為下方部分，一半導體氧化層作為中間部分以及一第三半導體材料層作為上方部分。接著沉積一含鍺金屬的半導體材料層於鰭狀結構上，更沉積一氧化層於含鍺金屬的半導體材料層上。更進行一高溫退火製程令使鰭狀結構上方部分一中央區內的鍺金屬，以及鰭狀結構上方部分一外圍區內的半導體氧化物凝結。最後移除鰭狀結構上方部分外圍區內的半導體氧化物。
根據本發明一或多個實施方式，其中第一半導體材料層為矽層、半導體氧化層為矽化鍺氧化物、第三半導體材料層為矽層以及含鍺金屬的半導體材料層為鍺層或矽化鍺層。
1000‧‧‧方法
1002-1024‧‧‧步驟
200‧‧‧鰭式場效電晶體元件
450B‧‧‧第二源汲極區
460B‧‧‧第二閘極區
505‧‧‧虛設介電層
200A‧‧‧N型鰭式場效電晶體元件
200B‧‧‧P型鰭式場效電晶體元件
210‧‧‧基板
212‧‧‧第一半導體材料層
214‧‧‧第二半導體材料層
216‧‧‧第三半導體材料層
220‧‧‧第一鰭狀結構
222‧‧‧圖案化鰭狀硬光罩層
230‧‧‧溝渠
310‧‧‧圖案化氧化硬光罩層
324‧‧‧半導體氧化層
330‧‧‧第二鰭狀結構
405‧‧‧襯墊
410‧‧‧介電層
420‧‧‧第四半導體材料層
425‧‧‧氧化覆蓋層
430‧‧‧鍺特徵結構層
435‧‧‧中間區
436‧‧‧外部區
440‧‧‧第三鰭狀結構
445‧‧‧第四鰭狀結構
450A‧‧‧第一源汲極區
510‧‧‧閘極堆疊
512‧‧‧介電層
514‧‧‧電極層
516‧‧‧閘極硬光罩
520‧‧‧側壁間隙壁
610A‧‧‧第一源/汲極
610B‧‧‧第二源/汲極
720‧‧‧層間介電層
810A‧‧‧第一閘極溝渠
810B‧‧‧第二閘極溝渠
910A‧‧‧第一高介電常數介電層/金屬閘極堆疊
910B‧‧‧第二高介電常數介電層/金屬閘極堆疊
2000‧‧‧方法
2002-2024‧‧‧步驟
2210‧‧‧基板
2220‧‧‧第五鰭狀結構
2230‧‧‧溝渠
2234‧‧‧第六鰭狀結構
2235‧‧‧第二圖案化鰭狀硬光罩
2240‧‧‧第三圖案化鰭狀硬光罩
460A‧‧‧第一閘極區
2440‧‧‧第七鰭狀結構
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：第1圖繪示根據本發明部分實施方式一種鰭式場效電晶體元件的製造方法流程圖。
第2圖繪示根據本發明部分實施方式中，依據第1圖的製造方法所製造之鰭式場效電晶體元件，在製程各個階 段的示意圖。
第3A-3B、4A-4B、5A-5B以及6A-6B圖繪示根據本發明部分實施方式中，依據第1圖的製造方法所製造之鰭式場效電晶體元件，在製程各個階段的示意圖。
第7A圖繪示根據本發明部分實施方式，依據第1圖的製造方法所製造之鰭式場效電晶體元件在製程各個階段中，沿著第6A圖A-A線的剖視圖。
第7B圖繪示根據本發明部分實施方式，依據第1圖的製造方法所製造之鰭式場效電晶體元件在製程各個階段的中，沿著第6B圖B-B線的剖視圖。
第7C-7D、8A-8B、9A-9B、10A-10B以及11A-11B圖繪示根據本發明部分實施方式中，依據第1圖的製造方法所製造之鰭式場效電晶體元件，在製程各個階段的示意圖。
第11C圖繪示根據本發明部分實施方式，依據第1圖的製造方法所製造之鰭式場效電晶體元件在製程各個階段中，沿著第11A圖A-A線的剖視圖。
第11D圖繪示根據本發明部分實施方式，依據第1圖的製造方法所製造之鰭式場效電晶體元件在製程各個階段中，沿著第11A圖AA-AA線的剖視圖。
第11E圖繪示根據本發明部分實施方式，依據第1圖的製造方法所製造之鰭式場效電晶體元件在製程各個階段中，沿著第11B圖B-B線的剖視圖。
第11F圖繪示根據本發明部分實施方式，依據第1圖的製造方法所製造之鰭式場效電晶體元件在製程各個階段 中，沿著第11B圖BB-BB線的剖視圖。
第12圖繪示根據本發明部分實施方式一種鰭式場效電晶體元件的製造方法流程圖。
第13A-13B、14A-14B、15A-15B、16A-16B、17A-17B以及18A-18B圖繪示根據本發明部分實施方式中，依據第12圖的製造方法所製造之鰭式場效電晶體元件，在製程各個階段的示意圖。
第18C圖繪示根據本發明部分實施方式，依據第1圖的製造方法所製造之鰭式場效電晶體元件在製程各個階段中，沿著第18B圖B-B線的剖視圖。
第18D圖繪示根據本發明部分實施方式，依據第12圖的製造方法所製造之鰭式場效電晶體元件在製程各個階段中，沿著第18B圖BB-BB線的剖視圖。
以下將以圖式及詳細說明清楚說明本發明之精神，任何所屬技術領域中具有通常知識者在瞭解本發明之較佳實施例後，當可由本發明所教示之技術，加以改變及修飾，其並不脫離本發明之精神與範圍。並為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，熟悉本領域之技術人員應當瞭解到，在本發明部分實施方式中，這些實務上的細節並非必要的，因此不應用以限制本發明。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
以下特舉出本發明之實施例，並配合所附圖式作詳細說明。以下實施例的元件和設計係為了簡化所揭露之發明，並非用以限定本發明。本發明於各個實施例中可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述結構之間的關係。此外，說明書中提及形成第一特徵結構位於第二特徵結構之上，其包括第一特徵結構與第二特徵結構是直接接觸的實施例，另外也包括於第一特徵結構與第二特徵結構之間另外有其他特徵結構的實施例，亦即，第一特徵結構與第二特徵結構並非直接接觸。
本發明係有關於，但不限定於，鰭式場效電晶體元件。舉例而言，鰭式場效電晶體元件可以是互補式金屬氧化物半導體(complementary metal oxide semiconductor,CMOS)元件，其中互補式金屬氧化物半導體(CMOS)元件包含一P型金屬氧化物半導體(P-type metal oxide semiconductor,PMOS)鰭式場效電晶體元件以及一N型金屬氧化物半導體(N-type metal oxide semiconductor,NMOS)鰭式場效電晶體元件。下文將繼續揭露鰭式場效電晶體元件的示範例，用以說明本發明的各種實施例。然而，應可了解的是，除了作為具體請求項之外，本發明之應用範圍不應該受限於特定類型的元件。
第1圖繪示根據本發明部分實施方式之一方法1000之流程圖，其用於製備一鰭式場效電晶體元件200。應可了解的是，在本方法的其他實施例中，實施該方法之 前、實施該方法期間及實施該方法之後，可提供額外的步驟，並且部份在本文中所描述的步驟可以被取代或省略。請參照各圖共同說明以理解鰭式場效電晶體元件200與其製備方法1000。
請參閱第1圖與第2圖，方法1000開始於步驟1002，提供一基板210。基板210可為塊狀矽基板，此外，基板210可為其它元素半導體材料，如結晶結構的矽(silicon)或鍺(germanium)，或化合物的半導體材料，如矽化鍺(silicon germanium)、碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)、及/或銻化銦(indium antimonide)，或其組合。
於本發明其它部分實施例中，基板210可為絕緣體上覆矽(semiconductor-on-insulator,SOI)基板。一合適的絕緣層可為是埋入氧化物層(buried oxide layer,BOX)。絕緣層上覆矽基板可由氧離子佈植隔離矽晶(separation by implantation of oxygen,SIMOX)、晶圓接合(wafer bonding)及/或其它合適的方法形成。
於此實施例中，基板210包含一第一半導體材料層212，一第二半導體材料層214位於第一半導體材料層212上，以及一第三半導體材料層216位於第二半導體材料層214上。第二半導體材料層214與第三半導體材料層216為不同的半導體材料層。更詳細地說，第二半導體層材料層214具有一第一晶格常數，而第三半導體材料層216具 有與第一晶格常數不同的一第二晶格常數。在此實施例中，第二半導體層材料層214為矽化鍺，而第一半導體材料層212與第三半導體材料層216均為矽。在其他部分實施例中，第一、第二與第三半導體材料層212、214與216可為鍺、矽、砷化鎵、砷化鋁鎵(aluminum gallium arsenide)、矽化鍺、磷化砷鎵(gallium arsenide phosphide)、或其它合適的材料。在此實施例中，第二半導體材料層214與第三半導體材料層216係以磊晶成長沉積而得，又被稱為一均厚通道磊晶。在部分實施例中，磊晶成長製程包含化學氣相沉積法(chemistry vapor deposition,CVD)(例如：氣相磊晶(vapor-phase epitaxy,VPE)和/或超高真空化學氣相沉積法(ultra-high vacuum CVD,UHV-CVD))、分子束磊晶成長法(molecular beam epitaxy)、和/或其他合適的方法。
請重新參閱第1圖與第2圖。方法1000繼續至步驟1004，在基板210中形成第一鰭狀結構220與溝渠230。在本發明之部分實施例中，一圖案化鰭狀硬光罩(fin hard mask,FHM)層222形成於基板210上。圖案化鰭狀硬光罩層222包含氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、或其他合適的介電材料。圖案化的鰭狀硬光罩層222可為單層的材料層或為多層的材料層。圖案化鰭狀硬光罩層222的係先由熱氧化(thermal oxidation)、化學氣相沉積、原子層沉積(atomic layer deposition,ALD)、或其他合適的方法沉積一材料層。接著以微影製程形成一圖案化光阻層，並藉由圖案化光阻層上 的開口蝕刻材料層，以形成圖案化鰭狀硬光罩層222。
接著藉由圖案化鰭狀硬光罩層222蝕刻基板210， 以在基板210中形成第一鰭狀結構220與溝渠230。在本發明其他部分實施例中，圖案化光阻層係直接使用圖案化鰭狀硬光罩層222來作為蝕刻過程中的蝕刻光罩，以在基板210中形成第一鰭狀結構220與溝渠230。蝕刻製程可為乾式蝕刻或濕式蝕刻。在本發明之其他實施例中，濕式蝕刻液係使用四甲基氫氧化銨(tetramethylammonium hydroxide,TMAH)溶液，氟化氫/硝酸/醋酸混合溶液，或其他合適的溶液。
在此實施例中，控制蝕刻深度使第二半導體材料層 214與第三半導體材料層216暴露出來，且第一半導體材料層212的一部分也在溝渠230中暴露出來。因此，形成的第一鰭狀結構220具有第三半導體材料層216作為上方部分，第二半導體材料層214作為中間部分以及第一半導體材料層212作為下方部分。
前述關於第1圖與第2圖的討論，其係用於製造一 N型鰭式場效電晶體元件和/或一P型鰭式場效電晶體的方法。接著更進一步介紹N型鰭式場效電晶體元件和/或P型鰭式場效電晶體的製備過程。在本發明之部分實施例中，鰭式場效電晶體元件200包含一N型鰭式場效電晶體元件，其元件符號為200A，並在後續的敘述中以N型鰭式場效電晶體元件200A來表示。鰭式場效電晶體元件200更包含一P型鰭式場效電晶體元件，其元件符號為200B，並在 後續的敘述中以P型鰭式場效電晶體元件200B來表示。
請參閱第1圖以及第3A-3B圖。方法1000繼續至步驟1006，將N型鰭式場效電晶體元件200A中的第二半導體材料層轉換為一半導體氧化層324。在本發明之部分實施例中，先形成一圖案化氧化硬光罩(oxidation hard mask,OHM)層310於基板210上，並覆蓋一部分的第一鰭狀結構220。圖案化氧化硬光罩層310只覆蓋P型鰭式場效電晶體元件200B，使得N型鰭式場效電晶體元件200A中的第二半導體材料層214轉換為半導體氧化層324的過程中，N型鰭式場效電晶體元件200A並未被圖案化氧化硬光罩層310覆蓋。
圖案化氧化硬光罩層310可包含氧化矽、氮化矽、 氮氧化矽、或其他合適的材料。圖案化氧化硬光罩層310可由熱氧化、化學氣相沉積、原子層沉積、或其他合適的方法來沉積一材料層，接著以微影製程形成一圖案化光阻層，並藉由圖案化光阻層上的開口蝕刻材料層，以形成圖案化氧化硬光罩層310。
在本發明之部分實施例中，係使用一熱氧化製程使N型鰭式場效電晶體元件200A中的第二半導體材料層214轉換為半導體氧化層324。在本發明之其他部分實施例中，熱氧化製程係在氧氣環境中進行。在本發明之其他部分實施例中，熱氧化製程係在蒸氣環境與氧氣環境的組合中進行。在本發明之其他部分實施例中，能控制熱氧化製程，使第二半導體材料層214的氧化速度高於第一半導體材料 層212與第三半導體材料層216。據此，第一半導體材料層212與第三半導體材料層216在會在外層形成非常薄的氧化層。在熱氧化製程後，再進行一清洗製程以移除第一半導體材料層212與第三半導體材料層216上的氧化層。清洗製程可使用稀釋的氫氟酸(diluted hydrofluoric,DHF)。
在熱氧化製程後，N型鰭式場效電晶體元件200A中的第一鰭狀結構220與P型鰭式場效電晶體元件200B中的第一鰭狀結構220已不相同。為了更明確的敘述，將N型鰭式場效電晶體元件200A中的第一鰭狀結構220改稱為一第二鰭狀結構330。第二鰭狀結構330具有作為上方部分的第三半導體材料層216，作為中間部分的半導體氧化層324以及作為下方部分的第一半導體材料層212。第二鰭狀結構330中的第三半導體材料層216將在閘極區下形成閘極通道，而半導體氧化物層324將對第三半導體材料層216施加適當的應力，詳細內容將於後續說明。
在本發明之部分實施例中，第二半導體材料層214為矽化鍺，半導體氧化層324為氧化矽鍺(silicon germanium oxide,SiGeO)，而第一半導體材料層212與第三半導體材料層216為矽。
在本發明另外之實施例中，在步驟1006中不形成 圖案化氧化硬光罩層310，因此N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B均暴露在熱氧化環境中。在N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中，第一鰭狀結構220內的第二半導體材 料層214均轉換為半導體氧化層324。
接下來的敘述係對應至只在N型鰭式場效電晶體元件200A中形成半導體氧化層324的實施例，但不以此為限。本領域具有通常知識者應理解方法1000可用於其他部分實施例中，像是N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中均具有半導體氧化層324。
請參閱第1圖與第4A-4B圖。方法1000繼續至步驟1008，在N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中，沉積一襯墊405於基板210上並將一介電層410填入溝渠230中。先以蝕刻製程將圖案化氧化硬光罩層310移除，如選擇性濕式蝕刻。在本發明之部分實施例中，襯墊405將沉積於基板210上並順應的覆蓋第一鰭狀結構220與第二鰭狀結構330。襯墊405可包含氮化矽、氮氧化矽、氧化鋁(aluminum oxide)、或其他合適的材料。在本發明之部分實施例中，係以原子層沉積法沉積襯墊405，使覆蓋第一鰭狀結構220與第二鰭狀結構330的襯墊405達到適當的覆蓋性。此外，亦可使用化學氣相沉積法、物理氣相沉積法(physical vapor deposition,PVD)、或其他合適的方法來沉積襯墊405。在此實施例中，襯墊405係設計作為一緩衝層，以防止第二半導體材料層214在後續製程中被氧化，同時能阻隔第二半導體材料層214向外擴散，此將在後續詳細說明。
介電層410係沉積於基板210中的襯墊405上，其填入N型鰭式場效電晶體元件200A與P型鰭式場效電晶 體元件200B的溝渠230中。介電層可包含氧化矽、氮化矽、氮氧化矽、旋塗式玻璃(spin-on-glass)、旋塗式聚合物(spin-on-polymer)，其他合適的材料、或其組合。介電層410係以化學氣相沉積、物理氣相沉積、原子層沉積、熱氧化、旋轉塗佈(spin-on-coating)、其他合適的方法、或其組合所形成。承前所述，覆蓋第一鰭狀結構220與第二鰭狀結構330的襯墊405能緩衝形成介電層410時產生的不利影響，如介電層410的熱固化製程。
之後，一化學機械研磨(chemical mechanical polishing)製程將移除多餘的襯墊405與介電層410，並同時移除圖案化鰭狀硬光罩222，以使N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B的上表面平坦化。
請參閱第1圖與第5A-5B圖。繼續進行方法1000至步驟1010，凹陷化N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中的襯墊405與介電層410。 襯墊405與介電層410係以合適的蝕刻製程來形成凹陷，例如：選擇性乾蝕刻、選擇性濕蝕刻、或其組合。此外，襯墊405與介電層410係以N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B上的一圖案化光阻層來進行凹陷化。在此實施例中，控制凹陷化製程以將N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中的第三半導體材料層216暴露出來。
請參閱第1圖與第6A-6B圖。繼續進行方法1000 至步驟1012，形成一第四半導體材料層420覆蓋第一鰭狀結構220與第二鰭狀結構330中暴露的第三半導體材料層216，並形成一氧化覆蓋層425於第四半導體材料層420上。在本發明之部分實施例中，當第三半導體材料層216為矽層時，第四半導體材料層420為一鍺層。在本發明之其他部分實施例中，當第三半導體材料層216為矽層時，第四半導體材料層420為矽化鍺層。第四半導體材料層420與氧化覆蓋層425可以化學氣相沉積、物理氣相沉積、原子層沉積、或其他合適的方法來形成。
請參閱第1圖與第7A-7B圖。繼續進行方法1000至步驟1014，鍺金屬在高溫退火下凝結以形成鍺特徵結構(Ge feature)430，且鍺特徵結構430為第一鰭狀結構220與第二鰭狀結構330的上方部分。在本發明之部分實施例中，高溫退火的溫度範圍為約800℃至1100℃。在此實施例中，第三半導體材料層216為矽層，而第四半導體材料層420為鍺層或矽化鍺層。在高溫退火的過程中，鍺層(或矽化鍺層)中的鍺金屬凝結並集中至上方部分的一中央區435，並同時形成氧化矽層作為第一鰭狀結構220與第二鰭狀結構330上方部分的一外圍區436。在此實施例中，控制高溫退火製程以於上部的中央區435中形成純鍺特徵結構430。在高溫退火製程後，以合適的蝕刻製程將外圍區436的氧化矽層移除，如選擇性濕蝕刻。據此，鍺特徵結構430取代第三半導體材料層216作為第一鰭狀結構220與第二鰭狀結構330的上部部分，其分別為第7C圖與第7D圖中所示 的一第四鰭狀結構445與一第三鰭狀結構440。高溫退火鍺金屬形成的鍺特徵結構430能有利於減少磊晶缺陷產生。
在本發明之部分實施例中，鰭狀場效電晶體元件200包含源/汲極區以及閘極區。更詳細地說，其中一源/汲極區為源極區而另一源/汲極區為汲極區，而閘極區分離此源極區與汲極區。為了更清楚且更詳述的描述本發明，N型鰭式場效電晶體元件200A中的源/汲極區與閘極區為一第一源/汲極區450A與一第一閘極區460A，而P型鰭式場效電晶體元件200B中的源/汲極區與閘極區為一第二源汲極區450B與一第二閘極區460B。
請參閱第1圖與第8A-8B圖。繼續進行方法1000至步驟1016，在第一閘極區460A與第二閘極區460B形成一閘極堆疊510，並在閘極堆疊510的側壁形成側壁間隙壁520。在本發明之部分實施例中係使用閘極後製程，閘極堆疊510為一虛設閘極，其於之後的製程中將被最後的閘極堆疊所取代。更清楚地說，虛設閘極堆疊510將於高溫高熱製程後被高介電常數(high-k,HK)介電層以及金屬閘極(metal gate,MG)電極取代，例如在形成源/汲極時以熱退火法活化源/汲極。
在本發明之部分實施例中，一虛設介電層505沉積於基板210上，並覆蓋第三鰭狀結構440與第四鰭狀結構445。在後續製程中形成形成虛設閘極堆疊510時，虛設介電層505能保護第三鰭狀結構440與第四鰭狀結構445，這將在後面詳述。虛設介電層505係以化學氣相沉積、物理 氣相沉積、原子層沉積、或其他合適的方法沉積。在本發明之其他部分實施例中，虛設介電層505包含二氧化矽。
虛設閘極堆疊510形成於基板210上，並有一部分的虛設閘極堆疊510位於第四鰭狀結構445的第一閘極區460A以及第三鰭狀結構440的第二閘極區460B之上。在本發明之部分實施例中，虛設閘極堆疊510包含一介電層512、一電極層514以及一閘極硬光罩(gate hard mask,GHM)516。係以合適的製程來形成虛設閘極堆疊510，包含沉積以及圖案化。圖案化製程則包含微影以及蝕刻。在部分實施例中，沉積係以化學氣相沉積、物理氣相沉積、原子層沉積、熱氧化、或其他合適的方法來進行。微影製程則包含塗佈光阻(例如：旋轉塗佈法)、軟烘烤、光罩對準、曝光、曝光後烘烤、光阻顯影、清洗、乾燥(例如：硬烘烤(hard baking))、其他合適的製程、和/或其組合。蝕刻製程包含濕式蝕刻、乾式蝕刻、或其他合適的蝕刻方法(例如：反應性離子蝕刻法(reactive ion etching))。
介電層512包含二氧化矽。此外，介電層512亦可包含氮化矽、高介電常數材料、或其他合適的材料。電極層514可包含多晶矽。閘極硬光罩516包含合適的介電材料，如氮化矽、氮氧化矽或碳化矽。側壁間隙壁520可為多層結構，通常形成側壁間隙壁520的方法包含沉積一介電材料於閘極堆疊510上，接著非等相性地回蝕刻此介電材料。回蝕刻製程為一多步驟的蝕刻製程，以增加蝕刻的選擇性與彈性，並減少過度蝕刻的情形發生。
請參閱第1圖與第9A-9B圖。繼續進行方法1000至步驟1018，形成第一源/汲極特徵結構610A於第一源/汲極區450A中與第二源/汲極610B特徵結構於第二源/汲極區450B中。在本發明之部分實施例中，凹陷化第一源/汲極區450A中，第四鰭狀結構445上方部分的一部份，並凹陷化第二源/汲極區450B中，第三鰭狀結構440上方部分的一部份。控制凹陷化製程以使第三鰭狀結構440與第四鰭狀結構445中仍留有一部分的鍺特徵結構430。接著磊晶生長第一源/汲極特徵結構610A於第一源/汲極區450A中凹陷的第四鰭狀結構445上，同時磊晶生長第二源/汲極特徵結構610B於第二源/汲極區450B中凹陷的第三鰭狀結構440上。第一源/汲極特徵結構610A與第二源/汲極特徵結構610B包含鍺、矽、砷化鎵、砷化鋁鎵(AlGaAs)、矽化鍺、磷化鍺砷(GaAsP)、或其他合適的材料。第一源/汲極特徵結構610A與第二源/汲極特徵結構610B可利用一或多個磊晶製程來形成。可在磊晶製程中進行第一源/汲極特徵結構610A與第二源/汲極特徵結構610B的原位摻雜(in-situ doped)。在部分實施例中，第一源/汲極特徵結構610A與第二源/汲極特徵結構610B不進行原位摻雜，而是採取佈植製程(亦即，接面佈植製程(junction implant process))進行第一源/汲極特徵結構610A與第二源/汲極特徵結構610B的摻雜。
在本發明之部分實施例中，第一源/汲極特徵結構610A係摻雜磷(phosphorous)於磊晶成長的矽化鍺層，以形 成磷化矽鍺(SiGeP)源極/汲極特徵結構。同時第二源/汲極特徵620A係摻雜硼於磊晶成長的錫化鍺層，以形成硼化鍺錫(GeSnB)源極/汲極特徵結構。
請參閱第1圖與第10A-10B圖。繼續進行方法1000至步驟1020，形成一層間介電層(interlayer dielectric,ILD)720於基板210上，層間介電層720位於虛設閘極堆疊510之間。層間介電層720包含二氧化矽、氮氧化矽、低介電常數(low-k)材料、或其他合適的材料。層間介電層720可為單層或多層結構，並以合適的方法製備，如化學氣相沉積、原子層沉積、或旋轉塗佈。接著可使用化學性機械研磨製程來移除多餘的層間介電層720，並平坦化鰭狀場效電晶體元件200的上表面。
請參閱第1圖與第10A-10B圖。繼續進行方法1000至步驟1022，移除第一閘極區460A的虛設閘極堆疊510以形成一或多個第一閘極溝渠810A。並移除第二閘極區460B的虛設閘極堆疊510以形成一或多個第二閘極溝渠810B。第四鰭狀結構445的上方部分於第一閘極溝渠810A中暴露，而第三鰭狀結構440的上方部分於第二閘極溝渠810B中暴露。虛設閘極堆疊510係以蝕刻製程移除(例如：選擇性濕蝕刻或選擇性乾蝕刻)，以在選擇性蝕刻後殘留鍺特徵結構430於第一閘極溝渠810A以及第二閘極溝渠810B中。蝕刻製程包含一或多個蝕刻步驟，其分別使用不同的蝕刻液。閘極硬光罩516與側壁間隙壁520也同時被移除。此外，虛設閘極堆疊510係以一系列的製程來移除， 包含微影圖案化以及蝕刻製程。
請參閱第1圖與第11A-11B圖。繼續進行方法1000至步驟1024，形成第一高介電常數介電層/金屬閘極堆疊910A與第二高介電常數介電層/金屬閘極堆疊910B於基板210上。第一高介電常數介電層/金屬閘極堆疊910A覆蓋第一閘極溝渠810A中第四鰭狀結構445的一部分，而第二高介電常數介電層/金屬閘極堆疊910B覆蓋第二閘極溝渠810B中第三鰭狀結構440的一部分。第一高介電常數介電層/金屬閘極堆疊910A與第二高介電常數介電層/金屬閘極堆疊910B包含一閘極介電層以及一金屬閘極層於閘極介電層上。在本發明之部分實施例中，閘極介電層為高介電常數的一介電材料層(在此實施方式中，介電材料層的介電常數高於熱氧化矽)，而金屬閘極層為金屬、金屬合金或金屬矽化物。在第一高介電常數介電層/金屬閘極堆疊910A與第二高介電常數介電層/金屬閘極堆疊910B的製備過程中，包含沉積不同的閘極材料，並使用化學性機械研磨法來移除多餘的閘極材料，以平坦化N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B的上表面。
在本發明之部分實施例中，閘極介電層包含一界面層(interfacial layer,IL)，其係由合適的方法所沉積，例如原子層沉積，化學氣相沉積、熱氧化或臭氧氧化(ozone oxidation)。界面層包含氧化物、鉿矽酸鹽(HfSiO)以及氮氧化物。一高介電常數介電層係以合適的方法沉積於界面層上，例如原子層沉積、化學氣相沉積、有機金屬化學汽相 沈積(metal organic CVD,MOCVD)、物理氣相沉積、其他合適的方法、或其組合。高介電常數介電層可包含氧化鑭(LaO)、氧化鋁(AlO)、氧化鋯(ZrO)、氧化鈦(TiO)、氧化鉭(Ta2O5)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3,STO)、鈦酸鋇(BaTiO3,BTO)、氧化鋯鋇(BaZrO)、氧化鋯鉿(HfZrO)、氧化鑭鉿(HfLaO)、氧化矽鉿(HfSiO)、氧化矽鑭(LaSiO)、氧化矽鋁(AlSiO)、氧化鉭鉿(HfTaO)氧化鈦鉿(HfTiO)、(HfTiO)、鈦酸(鋇、鍶)((Ba,Sr)TiO3,BST)、三氧化二鋁(Al2O3)、氮化矽(Si3N4)、氮氧化矽(SiON)、或其他合適的材料。閘極介電層覆蓋第一閘極區460A中第四鰭狀結構445的上方部分與第二閘極區460B中第三鰭狀結構440的上方部分。
金屬閘極層可包括單層結構或多層結構，例如具有功函數(work function)的金屬層(功函數金屬層(work function metal layer))以提升元件效能、襯層(liner layer)、濕潤層(wetting layer)、黏接層(adhesion layer)以及包含金屬、金屬合金或金屬矽化物的一導電層。金屬閘極層可包含下列材料：鈦(Ti)、銀(Ag)、鋁(Al)、氮化鈦鋁(TiAlN)、碳化鉭(TaC)、氮碳化鉭(TaCN)、氮矽化鉭(TaSiN)、錳(Mn)、鋯(Zr)、氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鋁(Al)、氮化鎢(WN)、銅(Cu)、鎢(W)或任何合適的材料。可藉由下列方法形成金屬閘極層，包含原子層沉積、物理氣相沉積、化學氣相沉積或其他合適的製程。金屬閘極層可利用與N型鰭式場效電晶體元件200A與P型鰭式場效電 晶體元件200B不同的金屬層個別獨立形成。接著以化學機械研磨製程將多餘的金屬閘極層移除。
請繼續參閱第11C圖與第11D圖，在N型鰭式場效電晶體元件200A中，第一閘極區460A包含第一高介電常數介電層/金屬閘極堆疊910A，其覆蓋第四鰭狀結構445的上部部分。第四鰭狀結構445中，鍺特徵結構430為上方部分、半導體氧化層324為中間部分以及第一半導體材料層212為下方部分。據此，在第四鰭狀結構445中形成半導體氧化層324時，將誘發適當的應力至第一閘極區460A，並增加第一閘極區460A中一通道區的電子遷移率。襯墊405則覆蓋第四鰭狀結構445中間部分與下方部分的側壁。半導體氧化層324更隔離鍺特徵結構430與第一半導體材料層212，避免產生不利影響。第一源/汲極區450A包含磷化矽鍺的源/汲極特徵結構610A，其位於一凹陷的鍺特徵結構430上並作為磊晶晶種層。
在本發明之部分實施例中，半導體氧化層324為矽化鍺氧化層，其厚度範圍為約20奈米至90奈米。在本發明之其他部分實施例中，鍺特徵結構430殘留於第一源/汲極區450A的凹陷上部，其厚度範圍為約3奈米至10奈米。
請繼續參閱第11E圖與第11F圖，在P型鰭式場效電晶體元件200B中，第二閘極區460B包含第二高介電常數介電層/金屬閘極堆疊910B，其覆蓋第三鰭狀結構440的上方部分。第三鰭狀結構440中，鍺特徵結構430為上方部分、矽化鍺層214為中間部分以及第一半導體材料層 212為下部部分。襯墊405覆蓋第三鰭狀結構440中間部分與下部部分的側壁。第二源/汲極區450B包含硼化鍺錫的源/汲極特徵結構610B，其位於一凹陷的鍺特徵結構430上並作為磊晶晶種層。此外，第二源/汲極區450B可包含矽鍺錫的源/汲極特徵結構。
在本發明之部分實施例中，矽化鍺層214中鍺金屬所佔之原子百分比為約20%至80%。在本發明之其他部分實施例中，鍺特徵結構430殘留於第二源/汲極區450B的凹陷上部，其厚度範圍為約3奈米至10奈米。
本揭露內容更討論鰭式場效電晶體元件200及其製備方法的多個不同實施例，如第12、13A-13B、14A-14B、15A-15B、16A-16B、17A-17B以及18A-18D圖所示。在此必須說明，下述實施例沿用前述實施例中的元件標號與部分內容號來表示相同或近似的元件。重複的目的是為了簡化和清楚說明，並非用於限定所討論的各種實施例和/或配置之間的關係。
請參閱第12圖與第13A-13B圖，方法2000開始於步驟2002，在N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中，形成第五鰭狀結構2220與溝渠2230於一基板2210中。基板2210包含位於第一半導體材料層212上的第二半導體料料層214，以及圖案化鰭狀硬光罩層222。第五鰭狀結構2220與溝渠2230係以微影以及蝕刻製程製備。第五鰭狀結構2220與溝渠2230的形成方法在許多方面與前述討論中第2圖的第一鰭狀結構220相 似。藉由控制蝕刻的深度，使剩餘的第二半導體材料層214具有第一厚度t1。
請參閱第12圖與第14A-14B圖。方法2000繼續至步驟2004，移除一部分的第二半導體材料層214以延伸P型鰭式場效電晶體元件200B中溝渠2230的深度。如圖所示，P型鰭式場效電晶體元件200B中溝渠2230在延伸後(或進一步的凹陷)，會殘留一部分的第二半導體材料層214在P型鰭式場效電晶體元件200B中，並具有第二厚度t2。為使發明說明更為明確，P型鰭式場效電晶體元件200B中的第五鰭狀結構2220將改稱為一第六鰭狀結構2234。
此外，步驟2004在延伸P型鰭式場效電晶體元件200B中溝渠2230的深度前，先形成一第二圖案化鰭狀硬光罩2235在N型鰭式場效電晶體元件200A上。如第14A圖所示，第二圖案化鰭狀硬光罩2235覆蓋N型鰭式場效電晶體元件200A中的第五鰭狀結構2220。第二圖案化鰭狀硬光罩2235與前述討論中第2圖的圖案化鰭狀硬光罩222相似。
請參閱第15A-15B圖，形成一第三圖案化鰭狀硬光罩2240於基板2210上，並更進一步的凹陷溝渠2230。一第三圖案化鰭狀硬光罩2240形成於N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中，並覆蓋第五鰭狀結構2220與第六鰭狀結構2234。第三圖案化鰭狀硬光罩2240與前述討論中第2圖的圖案化鰭狀硬光罩222相似。並且，更進一步凹陷化N型鰭式場效電晶體元件200A 與P型鰭式場效電晶體元件200B中的溝渠2230，以延伸第一半導體材料層212。如此一來，在N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中，一部分的第二半導體材料層214將暴露在延伸的溝渠2230中。
請參閱第12圖與第16A-16B圖。方法2000繼續至步驟2006，將N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中暴露的第二半導體材料層214轉換為一半導體氧化層324。步驟2006與前述討論中第3A-3B圖中方法1000進行的步驟1006相似。在形成半導體氧化層324，再以合適的蝕刻製程將第三圖案化鰭狀硬光罩2240移除。在本發明之部分實施例中，導體氧化層324為矽化鍺氧化層，其厚度範圍為約20奈米至90奈米。
請參閱第12圖。方法2000繼續至步驟2008，在N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中，沉積襯墊405於基板210上並將介電層410填入溝渠230中。步驟2010與前述討論中第4A-4B圖中方法1000進行的步驟1008相似。
請繼續參閱第12圖與第17A-17B圖。方法2000繼續至步驟2010，凹陷化N型鰭式場效電晶體元件200A與P型鰭式場效電晶體元件200B中的襯墊405與介電層410。步驟2010與前述討論中方法1000進行的步驟1010相似。在P型鰭式場效電晶體元件200B中，部分的第二半導體材料層214被暴露出來，形成第六鰭狀結構2234的上方部分。未暴露出來的第二半導體材料層214為中間部分 的上半部，半導體氧化層324則為中間部分的下半部，而第一半導體材料層212為下方部分。在N型鰭式場效電晶體元件200A中，第二半導體材料層214完全暴露出來，形成一第七鰭狀結構2440的上方部分。而半導體氧化層324作為中間部分，第一半導體材料層212作為下方部分。
源/汲極區係被閘極區分離。為了更清楚且更詳述的描述本發明，N型鰭式場效電晶體元件200A中的源/汲極區與閘極區為第一源汲極區450A與第一閘極區460A，而P型鰭式場效電晶體元件200B中的源/汲極區與閘極區為第二源汲極區450B與第二閘極區460B。
請參閱第12圖。方法2000繼續至步驟2012，以一第四半導體材料層420覆蓋第六鰭狀結構2234與第七鰭狀結構2440中暴露的第二半導體材料層214，並形成氧化覆蓋層425於第四半導體材料層420上。步驟2012與前述討論中第6A-6B圖中方法1000進行的步驟1012相似。
請參閱第12圖。方法2000繼續至步驟2014，鍺在高溫退火下凝結以形成鍺特徵結構430，以做為第六鰭狀結構2234與第七鰭狀結構2440上方部分的一中央區435，並同時形成氧化層作為第六鰭狀結構2234與第七鰭狀結構2440上方部分的一外圍區436。後續將以合適的蝕刻製程將氧化的外圍區436移除。步驟2014與前述討論中第7A-7D圖中方法1000進行的步驟1014相似。
請參閱第12圖。方法2000繼續至步驟2016，在第一閘極區460A與一第二閘極區460B形成一閘極堆疊 510，並在閘極堆疊510的側壁形成側壁間隙壁520。步驟2016與前述討論中第8A-8B圖中方法1000進行的步驟1016相似。
請參閱第12圖。方法2000繼續至步驟2018，形成第一源/汲極特徵結構610A於第一源/汲極區450A中與第二源/汲極特徵結構610B於第二源/汲極區450B中。步驟2018與前述討論中第9A-9B圖中方法1000進行的步驟1018相似。在本發明之部分實施例中，鍺特徵結構430殘留於第一源/汲極區450A的凹陷上部，其厚度範圍為約10奈米至30奈米。相同地，鍺特徵結構430殘留於第二源/汲極區450B的凹陷上部，其厚度範圍為約3奈米至10奈米。
請參閱第12圖。方法2000繼續至步驟2020，形成一層間介電層720於基板上，其位於虛設閘極堆疊510之間。步驟2020與前述討論中第10A-10B圖中方法1000進行的步驟1020相似。
請參閱第12圖。方法2000繼續至步驟2022，移除第一閘極區460A的虛設閘極堆疊510以形成一或多個第一閘極溝渠810A，並移除第二閘極區460B的虛設閘極堆疊510以形成一或多個第二閘極溝渠810B。步驟2022與前述討論中第10A-10B圖中方法1000進行的步驟1022相似。
請參閱第12圖與第18A-18B圖。繼續進行方法2000至步驟2024，分別形成第一高介電常數介電層/金屬 閘極堆疊910A與第二高介電常數介電層/金屬閘極堆疊910B於第一閘極溝渠810A與第二閘極溝渠810B。步驟2024與前述討論中第11A-11B圖中方法1000進行的步驟1024相似。
請參閱第18C圖與第18D圖，在P型鰭式場效電晶體元件200B中，第二閘極區460B包含第二高介電常數介電層/金屬閘極堆疊910B，其覆蓋第六鰭狀結構2234的上方部分。第六鰭狀結構2234中，鍺特徵結構430為上方部分、矽化鍺層214為中間部分的上半部，半導體氧化層324為中間部分的下半部，以及第一半導體材料層212為下方部分。襯墊405覆蓋第六鰭狀結構2234中間部分與下方部分的側壁。據此，第六鰭狀結構2234的矽化鍺層214(中間部分的上半部)提供適當的應力至第二閘極區460B，並增加第二閘極區460B中通道區的電子遷移率。半導體氧化層324(中間部分的下半部)更隔離鍺特徵結構430與第一半導體材料層212，避免產生不利影響。
在本發明之部分實施例中，第六鰭狀結構2234中間部分上半部的矽化鍺層214的厚度範圍為約10奈米至30奈米，而中間部分下半部的矽化鍺氧化層324的厚度範圍為約10奈米至60奈米。
在本方法的其他實施例中，實施方法2000之前、實施方法2000期間及實施方法2000之後，可提供額外的步驟，並且部份在本文中所描述的步驟可以被取代或省略。舉例來說，在部分實施例中，可跳過步驟2004。如此 一來，P型鰭式場效電晶體元件200B中的第六鰭狀結構2234將與N型鰭式場效電晶體元件200A中的第七鰭狀結構2440將具有相同的結構。
承前所述，本發明揭露鰭式場效電晶體元件的鰭狀結構。鰭狀結構採用純鍺特徵結構作為上方部分，其係在高溫退火下凝結矽化鍺層中的鍺金屬，並將鍺金屬集中至上部部分的中央區中。與磊晶成長相較之下，凝結鍺金屬的方式形成的鍺特徵結構能具有較少的磊晶缺陷。鰭狀結構更採用矽化鍺氧化層以隔離鍺特徵結構與位於下方部分的矽層，以減少產生不利影響。在P型鰭式場效電晶體元件中，鰭狀結構的鍺特徵結構與矽化鍺氧化層間為矽化鍺層，其能提供適當的通道層壓縮應力。鰭狀結構更採用一薄矽化鍺層作為磊晶晶種層，以形成源/汲極特徵結構。據此，鰭狀結構能提升元件性能。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200A‧‧‧N型鰭式場效電晶體元件
200B‧‧‧P型鰭式場效電晶體元件
212‧‧‧第一半導體材料層
324‧‧‧半導體氧化層
405‧‧‧襯墊
410‧‧‧介電層
420‧‧‧第四半導體材料層
450A‧‧‧第一源汲極區
460A‧‧‧第一閘極區
450B‧‧‧第二源汲極區
460B‧‧‧第二閘極區
505‧‧‧虛設介電層
610A‧‧‧第一源/汲極
610B‧‧‧第二源/汲極
720‧‧‧層間介電層
910A‧‧‧第一高介電常數介電層/金屬閘極堆疊
910B‧‧‧第二高介電常數介電層/金屬閘極堆疊
2210‧‧‧基板
2234‧‧‧第六鰭狀結構
2440‧‧‧第七鰭狀結構

Claims (10)

  1. 一種半導體元件，包含：一第一鰭狀結構，位於一基板的一N型鰭式場效電晶體區域之上，該第一鰭狀結構包含：一矽層；一矽化鍺氧化層位於該矽層上；以及一鍺特徵結構位於該矽化鍺氧化層上；以及一第二鰭狀結構，位於該基板的一P型鰭式場效電晶體區域之上，該第二鰭狀結構包含：該矽層；該矽化鍺氧化層位於該矽層上；一矽化鍺磊晶層位於該矽化鍺氧化層上；以及該鍺特徵結構位於該矽化鍺磊晶層上。
  2. 如請求項1所述之半導體元件，更包含：一高介電常數介電層/金屬閘極堆疊位於該基板的該N型鰭式場效電晶體區域之上，並包覆該第一鰭狀結構一部分的上方部分；以及一第一源/汲極特徵結構位於該第一鰭狀結構上方部分的一凹陷上，且該高介電常數介電層/金屬閘極堆疊分隔該第一源/汲極特徵結構。
  3. 如請求項2所述之半導體元件，其中該第一源/汲極特徵結構包含磷化矽鍺。
  4. 如請求項1所述之半導體元件，更包含：一高介電常數介電層/金屬閘極堆疊位於該基板的該P型鰭式場效電晶體區域之上，並包覆該第二鰭狀結構一部分的上方部分；以及一第二源/汲極特徵結構位於該第二鰭狀結構上方部分的一凹陷上，且該高介電常數介電層/金屬閘極堆疊分隔該第二源/汲極特徵結構。
  5. 如請求項4所述之半導體元件，其中該第二源/汲極特徵結構包含硼化鍺錫。
  6. 一鰭狀場效電晶體元件，包含：一第一鰭狀結構，位於一基板的一N型鰭式場效電晶體區域之上，該第一鰭狀結構包含：一鍺特徵結構作為上方部分；一矽化鍺氧化層作為中間部分；以及一矽層作為下方部分；一第二鰭狀結構，位於該基板的一P型鰭式場效電晶體區域之上，該第二鰭狀結構包含：該鍺特徵結構作為上方部分；一矽化鍺磊晶層作為中間部分；以及該矽層作為下方部分；一高介電常數介電層/金屬閘極堆疊位於該基板的該N 型鰭式場效電晶體區域之上，並包覆該第一鰭狀結構一部分的上方部分；一第一源/汲極特徵結構位於該第一鰭狀結構上方部分的一凹陷上，且該高介電常數介電層/金屬閘極堆疊分隔該第一源/汲極特徵結構；該高介電常數介電層/金屬閘極堆疊位於該基板的該P型鰭式場效電晶體區域之上，並包覆該第二鰭狀結構一部分的上方部分；以及一第二源/汲極特徵結構位於該第二鰭狀結構上方部分的一凹陷上，且該高介電常數介電層/金屬閘極堆疊分隔該第二源/汲極特徵結構。
  7. 如請求項6所述之鰭狀場效電晶體元件，其中該第一源/汲極特徵結構包含磷化矽鍺。
  8. 如請求項6所述之鰭狀場效電晶體元件，其中該第二源/汲極特徵結構包含硼化鍺錫。
  9. 一種形成半導體元件之方法，包含：形成一鰭狀結構於一基板上，該鰭狀結構包含：一第一半導體材料層作為下方部分；一半導體氧化層作為中間部分；以及一第三半導體材料層作為上方部分；沉積一含鍺金屬的半導體材料層於該鰭狀結構上； 沉積一氧化層於該含鍺金屬的半導體材料層上；進行一高溫退火製程令使該鰭狀結構上方部分一中央區內的鍺金屬，以及該鰭狀結構上方部分一外圍區內的半導體氧化物凝結；以及移除該鰭狀結構上方部分該外圍區內的半導體氧化物。
  10. 如請求項9所述之方法，其中：該第一半導體材料層為矽層；該半導體氧化層為矽化鍺氧化物；該第三半導體材料層為矽層；以及該含鍺金屬的半導體材料層為鍺層或矽化鍺層。
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