CN105322014A - Sram finfet器件的结构和方法 - Google Patents

Sram finfet器件的结构和方法 Download PDF

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CN105322014A
CN105322014A CN201410778074.8A CN201410778074A CN105322014A CN 105322014 A CN105322014 A CN 105322014A CN 201410778074 A CN201410778074 A CN 201410778074A CN 105322014 A CN105322014 A CN 105322014A
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fin structure
layer
parts
silicon
stack
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CN105322014B (zh
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江国诚
冯家馨
吴志强
卡洛斯·H.·迪亚兹
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种鳍式场效应晶体管(FINFET)器件的实施例。该器件包括设置在衬底的n型FinFET(NFET)区域上方的第一鳍结构。第一鳍结构包括：硅(Si)层、设置在硅层上方的氧化硅锗(SiGeO)层和设置在SiGeO层上方的锗(Ge)部件。该器件还包括位于p型FinFET(PFET)区域中的衬底上方的第二鳍结构。第二鳍结构包括：硅(Si)层、设置在硅层上方的凹进的氧化硅锗(SiGeO)层、设置在凹进的SiGeO层上方的外延硅锗(SiGe)层以及设置在外延SiGe层上方的锗(Ge)部件。本发明还提供了形成FINFET器件的方法。

Description

SRAM FINFET器件的结构和方法
相关申请的交叉引用
本申请与2013年1月14日提交的标题为“半导体器件及其制造方法”的美国专利申请第13/740,373号；2013年5月24日提交的标题为“FinFET器件及其制造方法”的美国专利申请第13/902,322号；2013年7月3日提交的标题为“半导体器件的鳍结构”的美国专利申请第13/934,992号；2014年1月15日提交的标题为“半导体器件及其形成方法”的美国专利申请第14/155,793号；2014年4月16日提交的标题为“FinFET器件的方法和结构”的美国专利申请第14/254,072号；以及2014年4月16日提交的标题为“具有高K金属栅极堆叠件的FinFET器件”的美国专利申请第14/254,035号相关，其全部公开内容结合于此作为参考。
技术领域
本发明涉及集成电路器件，更具体地，涉及SRAMFinFET器件的结构和方法。
背景技术
半导体集成电路(IC)工业已经经历了指数增长。IC材料和设计中的技术进步已经产生了数代IC，每一代IC都具有比前一代IC更小且更复杂的电路。在IC发展的过程中，功能密度(即，每芯片面积上的互连器件的数量)已普遍增加，而几何尺寸(即，使用制造工艺可以制造的最小部件(或线))减小。这种按比例缩小工艺通常通过提高生产效率以及降低相关成本来提供益处。
这种按比例缩小也增加了加工和制造IC的复杂度，并且为了实现这些进步，需要IC加工和制造中的类似的发展。例如，已引入诸如鳍式场效应晶体管(FinFET)的三维晶体管来代替平面晶体管。虽然现有的FinFET器件和制造FinFET器件的方法通常已能够满足它们的预期目的，但是它们不是在所有方面都完全令人满意。
发明内容
为了解决现有技术中的问题，本发明提供了一种器件，包括：第一鳍结构，设置在衬底的n型FinFET(NFET)区域上方，所述第一鳍结构包括：硅(Si)层；氧化硅锗(SiGeO)层，设置在所述硅层上方；及锗(Ge)部件，设置在所述SiGeO层上方；以及第二鳍结构，位于p型FinFET(PFET)区域中的所述衬底上方，所述第二鳍结构包括：硅(Si)层；凹进的氧化硅锗(SiGeO)层，设置在所述硅层上方；外延硅锗(SiGe)层，设置在所述凹进的SiGeO层上方；及锗(Ge)部件，设置在所述外延SiGe层上方。
在上述器件中，其中，所述第一鳍结构的中间部分的SiGeO层的厚度介于约20nm至约90nm的范围内。
在上述器件中，其中，所述第二鳍结构的中间部分的上部的外延SiGe层的厚度介于约10nm至约30nm的范围内。
在上述器件中，其中，所述第二鳍结构的中间部分的下部的凹进的SiGeO层的厚度介于约10nm至约60nm的范围内。
在上述器件中，其中，所述器件还包括：高k(HK)/金属栅极(MG)堆叠件，位于所述NFET区域中的所述衬底上方，包裹在所述第一鳍结构的一部分的上部上方；以及第一源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第一鳍结构的凹进的上部的上方。
在上述器件中，其中，所述器件还包括：高k(HK)/金属栅极(MG)堆叠件，位于所述NFET区域中的所述衬底上方，包裹在所述第一鳍结构的一部分的上部上方；以及第一源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第一鳍结构的凹进的上部的上方。其中，所述第一鳍结构的凹进的上部具有厚度在约3nm至约10nm的范围内的剩余的Ge部件。
在上述器件中，其中，所述器件还包括：高k(HK)/金属栅极(MG)堆叠件，位于所述NFET区域中的所述衬底上方，包裹在所述第一鳍结构的一部分的上部上方；以及第一源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第一鳍结构的凹进的上部的上方。其中，所述第一S/D部件包括硅锗磷(SiGeP)。
在上述器件中，其中，所述器件还包括：高k(HK)/金属栅极(MG)堆叠件，位于所述PFET区域中的所述衬底上方，包裹在所述第二鳍结构的部分的上部上方；第二源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第二鳍结构的凹进的上部的上方。
在上述器件中，其中，所述器件还包括：高k(HK)/金属栅极(MG)堆叠件，位于所述PFET区域中的所述衬底上方，包裹在所述第二鳍结构的部分的上部上方；第二源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第二鳍结构的凹进的上部的上方。其中，所述第二鳍结构的凹进的上部具有厚度在约3nm至10nm的范围内的剩余的Ge部件。
在上述器件中，其中，所述器件还包括：高k(HK)/金属栅极(MG)堆叠件，位于所述PFET区域中的所述衬底上方，包裹在所述第二鳍结构的部分的上部上方；第二源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第二鳍结构的凹进的上部的上方。其中，所述第二S/D部件包括锗锡硼(GeSnB)。
根据本发明的另一方面，提供了一种鳍式场效应晶体管(FinFET)器件，包括：第一鳍结构，位于衬底的n型FinFET(NFET)区域上方，所述第一鳍结构包括：锗(Ge)部件，作为所述第一鳍结构的上部；氧化硅锗(SiGeO)层，作为所述第一鳍结构的中间部分；以及硅(Si)层，作为所述第一鳍结构的底部；及第二鳍结构，位于所述衬底的p型FinFET(PFET)区域上方，所述第二鳍结构包括：锗(Ge)部件，作为所述第二鳍结构的上部；外延硅锗(SiGe)层，作为所述第二鳍结构的中间部分；及硅(Si)层，作为所述第二鳍结构的底部；高k(HK)/金属栅极(MG)堆叠件，位于所述NFET区域中的所述衬底上方，包裹在所述第一鳍结构的一部分的上部上方；第一源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第一鳍结构的凹进的上部的上方；高k(HK)/金属栅极(MG)堆叠件，位于所述PFET区域中的所述衬底上方，包裹在所述第二鳍结构的一部分的上部上方；以及第二源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第二鳍结构的凹进的上部的上方。
在上述FinFET器件中，其中，所述第一鳍结构的中间部分的SiGeO层的厚度介于约20nm至约90nm的范围内。
在上述FinFET器件中，其中，所述外延SiGe层具有原子百分比为约20％至约80％的Ge组分。
在上述FinFET器件中，其中，所述第一鳍结构的凹进的上部具有厚度在约3nm至10nm的范围内的剩余的Ge部件。
在上述FinFET器件中，其中，所述第二鳍结构的凹进的上部具有厚度在约3nm至10nm的范围内的剩余的Ge部件。
在上述FinFET器件中，其中，所述第一S/D部件包括硅锗磷(SiGeP)。
在上述FinFET器件中，其中，所述第二S/D部件包括锗锡硼(GeSnB)。
根据本发明的又一方面，提供了一种方法，包括：在衬底上方提供鳍结构；所述鳍结构包括：第一半导体材料层，作为所述鳍结构的底部；半导体氧化物层，作为所述鳍结构的中间部分；以及第三外延半导体材料层，作为所述鳍结构的上部；在所述鳍结构上方沉积含锗半导体材料层；在所述含锗半导体材料层上方沉积氧化物层；应用高温退火以使锗(Ge)浓缩在所述鳍结构的上部的中心部分中并且在所述鳍结构的上部的外部中形成半导体氧化物；以及去除所述鳍结构的上部的外部的所述半导体氧化物。
在上述方法中，其中，所述第一半导体材料层包括硅(Si)层；所述半导体氧化物层包括氧化硅锗(SiGeO)；所述第三外延半导体材料层包括Si层；以及所述含锗半导体材料层包括锗(Ge)层。
在上述方法中，其中，所述第一半导体材料层包括硅(Si)层；所述半导体氧化物层包括氧化硅锗(SiGeO)；所述第三外延半导体材料层包括Si层；以及所述含锗半导体材料层包括锗(Ge)层。其中，所述含锗半导体材料层包括硅锗(SiGe)层。
附图说明
当结合附图进行阅读时，从下面的详细说明书能够最佳地理解本发明的各个方面。应该注意的是，根据工业中的标准实践，附图中的各个部件未按比例绘制。实际上，为了清楚的讨论，可以任意增大或减小所示出的部件的尺寸。
图1是根据一些实施例的用于制造FinFET器件的示例性方法的流程图。
图2是根据一些实施例的正在加工的示例性FinFET器件的示意性立体图。
图3A至图3B、图4A至图4B、图5A至图5B和图6A至图6B是根据图1的方法构造的处于制造阶段的示例性FinFET器件的示意性立体图。
图7A是沿着图6A中的线A-A所截取的根据图1的方法构造的处于制造阶段的示例性FinFET器件的截面图。
图7B是沿着图6B中的线B-B所截取的根据图1的方法构造的处于制造阶段的示例性FinFET器件的截面图。
图7C至图7D、图8A至图8B、图9A至图9B、图10A至图10B和图11A至图11B是根据一些实施例的正在加工的FinFET器件的示意性立体图。
图11C是沿着图11A中的线A-A所截取的根据图1的方法构造的处于制造阶段的示例性FinFET器件的截面图。
图11D是沿着图11A中的线AA-AA所截取的根据图1的方法构造的处于制造阶段的示例性FinFET器件的截面图。
图11E是沿着图11B中的线B-B所截取的根据图1的方法构造的处于制造阶段的示例性FinFET器件的截面图。
图11F是沿着图11B中的线BB-BB所截取的根据图1的方法构造的处于制造阶段的示例性FinFET器件的截面图。
图12是根据一些实施例的用于制造FinFET器件的另一示例性方法的流程图。
图13A至图13B、图14A至图14B、图15A至图15B、图16A至图16B、图17A至图17B和图18A至图18B是根据一些实施例的正在加工的FinFET器件的示意性立体图。
图18C是沿着图18B中的线B-B所截取的根据图12的方法构造的处于制造阶段的示例性FinFET器件的截面图。
图18D是沿着图18B中的线BB-BB所截取的根据图12的方法构造的处于制造阶段的示例性FinFET器件的截面图。
具体实施方式
为了实现本发明的不同特征，以下公开内容提供了多个不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然，这些仅仅是实例而并不旨在限制。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件使得第一部件和第二部件可以不直接接触的实施例。另外，在各个实例中，本发明可以重复参考标号和/或字母。这种重复是为了简明和清楚的目的，其本身并不表示所论述的各个实施例和/或配置之间的关系。
本发明针对但不限于鳍式场效应晶体管(FinFET)器件。例如，FinFET器件可以是包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件的互补金属氧化物半导体(CMOS)器件。以下公开内容将继续以FinFET实例来说明本发明的各个实施例。然而，应当理解，除非明确声明，否则本申请不应限于特定类型的器件。
图1是根据一些实施例的用于制造FinFET器件200的方法1000的流程图。应当理解，可以在该方法之前、期间和之后实施额外的步骤，并且对于该方法的其他实施例，所描述的一些步骤可被取代或消除。参照各个附图共同描述FinFET器件200及其制造方法1000。
参照图1和图2，方法1000开始于步骤1002：提供衬底210。衬底210可以包括块状硅衬底。可选地，衬底210可以包括诸如晶体结构的硅或锗的元素半导体；诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；或它们的组合。
在另一实施例中，衬底210包括在衬底中具有绝缘层的绝缘体上硅(SOI)结构。示例性绝缘层可以是埋氧层(BOX)。可以使用注氧隔离(SIMOX)、晶圆接合和/或其他合适的方法来制造SOI衬底。
在本实施例中，衬底210包括第一半导体材料层212、设置在第一半导体材料层212上方的第二半导体材料层214以及设置在第二半导体材料层214上方的第三半导体材料层216。第二半导体材料层214和第三半导体材料层216彼此不同。第二半导体材料层214具有第一晶格常数，而第三半导体材料层216具有不同于第一晶格常数的第二晶格常数。在本实施例中，第二半导体材料层214包括硅锗(SiGe)，而第一半导体材料层212和第三半导体材料层216二者均包括硅(Si)。在各个实例中，第一、第二和第三半导体材料层212、214和216可以包括锗(Ge)、硅(Si)、砷化镓(GaAs)、砷化铝镓(AlGaAs)、硅锗(SiGe)、磷砷化镓(GaAsP)或其他合适的材料。在本实施例中，通过外延生长沉积第二半导体材料层214和第三半导体材料层216，称为毯式沟道外延(blanketchannelepi)。在各个实例中，外延工艺包括CVD沉积技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延和/或其他合适的工艺。
参照图1和图2，方法1000进行至步骤1004，在衬底210中形成第一鳍结构220和沟槽230。在一个实施例中，在衬底210上方形成图案化的鳍式硬掩模(FHM)层222。图案化的FHM层222包括氧化硅、氮化硅、氮氧化硅或任意其他合适的介电材料。图案化的硬掩模层222可以包括单个材料层或多个材料层。图案化的FHM层222可以通过以下步骤形成：通过热氧化、化学汽相沉积(CVD)、原子层沉积(ALD)或任意其他合适方法沉积材料层；通过光刻工艺形成图案化的光刻胶(抗蚀剂)层；以及穿过该图案化的光刻胶层的开口蚀刻材料层以形成图案化的FHM层222。
然后，穿过图案化的FHM层222蚀刻衬底210以在衬底210中形成第一鳍结构220和沟槽230。在另一实施例中，将图案化的光刻胶层直接用作蚀刻工艺的蚀刻掩模(图案化的FHM层222)以在衬底210中形成第一鳍结构220和沟槽230。蚀刻工艺可以包括湿蚀刻或干蚀刻。在一个实施例中，湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液或其他合适的溶液。
在本实施例中，控制蚀刻深度，使得暴露第三半导体材料层216和第二半导体材料层214而第一半导体材料层212的部分暴露于沟槽230中。因此，第一鳍结构220形成为具有作为其上部的第三半导体材料层216、作为其中间部分的第二半导体材料层214和作为其底部的第一半导体材料层212。
关于图1和图2的以上论述适用于制造n型FinFET(NFET)器件和/或制造p型FinFET(PFET)器件的方法。下文中描述的工艺论述了制造NFET器件和/或PFET器件的工艺。在一些实施例中，FinFET器件200包括NFET器件，以参考标号200A表示并称为NFET器件200A。FinFET器件200也包括PFET器件，以参考标号200B表示并称为PFET器件200B。
参照图1和图3A至图3B，方法1000进行至步骤1006，将NFET器件200A中的第二半导体材料层214转化为半导体氧化物层324。在一个实施例中，首先，图案化的氧化硬掩模(OHM)310形成在衬底210上方，包括包裹第一鳍结构220的部分。在将NFET器件200A中的第二半导体材料层214转化为半导体氧化物层324的步骤期间，图案化的OHM310覆盖PFET器件200B而留下NFET器件200A未被覆盖。
图案化的OHM层310可以包括氧化硅、氮化硅、氮氧化硅或任意其他合适的介电材料。图案化的OHM层310可以通过以下步骤形成：通过热氧化、化学CVD、ALD或任意其他合适的方法沉积材料层；通过光刻工艺形成图案化的光刻胶(抗蚀剂)层；以及穿过该图案化的光刻胶层的开口蚀刻材料层以形成图案化的OHM层310。
在本实施例中，实施热氧化工艺以将NFET器件200A中的第二半导体材料层214转化为半导体氧化物层324。在一个实施例中，在氧环境下进行热氧化工艺。在另一实施例中，在蒸汽环境和氧环境的组合下进行热氧化工艺。在一个实施例中，控制热氧化工艺，从而使得第二半导体材料层214比第一和第三半导体材料层212和216氧化得快得多。因此，被氧化的第一和第三半导体材料层212和216的外层很薄。在氧化工艺之后，实施清洗工艺以去除第一和第三半导体材料层212和216的氧化的外层。可以使用稀释的氢氟酸(DHF)实施清洗工艺。
在热氧化工艺之后，NFET器件200A中的第一鳍结构220具有与PFET器件200B中的第一鳍结构220不同的结构。为了清楚地更好描述，NFET器件200A中的第一鳍结构220称为第二鳍结构330。因此，第二鳍结构330具有作为其上部的第三半导体材料层216、作为其中间部分的半导体氧化物层324和作为其底部的第一半导体材料层212。半导体氧化物层324对第二鳍结构330中的第三半导体材料层216施加充足的应力，其中，栅极沟道将限定在栅极区下方，这将在后文中描述。
在一个实施例中，第二半导体材料层214包括硅锗(SiGe)，半导体氧化物层324包括氧化硅锗(SiGeO)，并且第一和第三半导体材料层212和216均包括硅(Si)。
在可选实施例中，在步骤1006期间跳过OHM310的形成，并且将NFET器件200A和PFET器件200B中的第一鳍结构220均暴露于热氧化中。NFET器件200A和PFET器件200B中的第一鳍结构220的第二半导体材料层214均被转化为半导体氧化物层324。
以下描述将针对仅在NFET器件200A中具有半导体氧化物层324的实施例。本领域普通技术人员也应当意识到，方法1000将类似地适用于不同实施例，诸如在NFET器件200A和PFET器件200B中均具有半导体氧化物层324的实施例。
参照图1和图4A至图4B，方法1000进行至步骤1008，在衬底210上方沉积衬垫405，以及然后在NFET器件200A和PFET器件200B中的沟槽230中均填充介电层410。首先，通过诸如选择性湿蚀刻的蚀刻工艺去除图案化的OHM层310。在本实施例中，然后在衬底210上方沉积衬垫405，包括共形地包裹在第一和第二鳍结构220和330上方。衬垫405可以包括氮化硅、氮氧化硅、氧化铝或其他合适的材料。在一个实施例中，通过ALD沉积衬垫405以实现包裹在第一和第二鳍结构220和330上方的足够的膜覆盖。可选地，可以通过CVD、物理汽相沉积(PVD)或其他合适的技术沉积衬垫405。在本实施例中，将衬垫405设计成防止第二半导体材料层214在下游或后续加工中被进一步氧化的缓冲层以及防止第二半导体材料层214向外扩散的阻挡层，这将在下文中详细描述。
介电层410沉积在衬底210中的衬垫405上方，包括填充在NFET器件200A和PFET器件200B中的沟槽230中。介电层410可以包括氧化硅、氮化硅、氮氧化硅、旋涂玻璃、旋涂聚合物、其他合适的材料或它们的组合。可以通过CVD、物理汽相沉积(PVD)、ALD、热氧化、旋涂、其他合适的技术或它们的组合来沉积介电层410。如前文所述，使得衬垫405覆盖第一和第二鳍结构220和330，衬垫405提供了对在形成介电层410期间(诸如在介电层410的热固化工艺中)引起的不利影响的缓冲。
之后可以实施CMP工艺以去除多余的衬垫405和介电层410以及FHM222，并且平坦化NFET器件200A和PFET器件200B的顶面。
参照图1和图5A至图5B，方法1000进行至步骤1010，使NFET器件200A和PFET器件200B中的衬垫405和介电层410凹进。通过诸如选择性湿蚀刻、选择性干蚀刻或它们的组合的合适的蚀刻工艺使衬垫405和介电层410凹进。可选地，穿过形成在NFET器件200A和PFET器件200B上方的图案化的光刻胶层来使衬垫405和介电层410凹进。在本实施例中，控制凹进工艺，使得NFET器件200A和PFET器件200B中的第三半导体材料层216完全暴露。
参照图1和图6A至图6B，方法1000进行至步骤1012，在第一和第二鳍结构220和330中的暴露的第三半导体材料层216的上方包裹第四半导体材料层420和位于第四半导体材料层420上方的氧化物覆盖层425。在一个实施例中，第四半导体材料层420包括Ge层而第三半导体材料层包括Si层。在另一实施例中，第四半导体材料层420包括SiGe层而第三半导体材料层包括Si层。可以通过CVD、ALD、PVD或其他合适的工艺来沉积第四半导体材料层420和氧化物覆盖层425。
参照图1和图7A至图7B，方法1000进行至步骤1014，实施高温退火使Ge浓缩以形成Ge部件430，Ge部件430作为第一和第二鳍结构220和330的上部。在一个实施例中，温度范围从约800℃至约1100℃。在本实施例中，第三半导体材料层216是Si层，而第四半导体材料层420是Ge层或SiGe层。在高温退火期间，Ge从Ge(或SiGe)层420中浓缩以集中在上部的中间部分435，同时形成氧化硅层作为第一和第二鳍结构220和330的上部的外层436。在本实施例中，控制高温退火工艺以使上部的中间部分435为纯Ge部件430。在退火工艺之后，通过诸如选择性湿蚀刻的合适的蚀刻工艺去除氧化硅外层436。因此，如图7C和图7D所示，代替第三半导体材料层216的Ge部件430作为第一和第二鳍结构220和330的上部，分别称为第三和第四鳍结构440和445。通过在高温退火中浓缩Ge而形成的Ge部件430提供了低外延缺陷的优势。
在一些实施例中，FinFET器件200包括源极/漏极(S/D)区和栅极区。在又一实施例中，S/D区中的一个为源极区，而S/D区中的另一个为漏极区。S/D区通过栅极区分隔开。为了清楚地更好描述，NFET器件200A中的S/D区和栅极区被称为第一S/D区450A和第一栅极区460A；PFET器件200B中的S/D区和栅极区被称为第二S/D区450B和第二栅极区460B。
参照图1和图8A至图8B，方法1000进行至步骤1016，在第一和第二栅极区460A和460B中，形成栅极堆叠件510以及栅极堆叠件510的侧壁上的侧壁间隔件520。在使用后栅极工艺的一个实施例中，栅极堆叠件510为伪栅极并在随后阶段将被最终栅极堆叠件所取代。具体地，在高温热工艺(诸如源极/漏极形成期间用于S/D活化的热退火)之后，伪栅极堆叠件510随后将被高k(HK)介电层和金属栅(MG)电极所取代。
在一个实施例中，伪介电层505沉积在衬底210上方，包括包裹在第三和第四鳍结构440和445上方。伪介电层505设计为在形成伪栅极堆叠件的后续工艺期间保护第三和第四鳍结构440和445，这将在后文中描述。可以通过ALD、CVD、PVD或其他合适的技术来沉积伪介电层505。在一个实施例中，伪介电层505包括氧化硅。
伪栅极堆叠件510形成在衬底210上方并部分地设置在第一栅极区460A中的第四鳍结构445以及第二栅极区460B中的第三鳍结构440上方。在一个实施例中，伪栅极堆叠件510包括介电层512、电极层514和栅极硬掩模(GHM)516。通过包括沉积和图案化的合适的步骤形成伪栅极堆叠件510。图案化工艺还包括光刻和蚀刻。在多个实例中，沉积包括CVD、物理汽相沉积(PVD)、ALD、热氧化、其他合适的技术或它们的组合。光刻工艺包括光刻胶(或抗蚀剂)涂布(例如，旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶、冲洗、干燥(例如，硬烘烤)、其他合适的工艺和/或它们的组合。蚀刻工艺包括干蚀刻、湿蚀刻和/或其他蚀刻方法(例如，反应离子蚀刻)。
介电层512包括氧化硅。可选地或额外地，介电层512可以包括氮化硅、高k介电材料或其他合适材料。电极层514可以包括多晶体硅(多晶硅)。GHM516包括诸如氮化硅、氮氧化硅或碳化硅的合适的介电材料。侧壁间隔件520可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅或它们的组合的介电材料。侧壁间隔件520可以包括多层。侧壁间隔件520的典型的形成方法包括在栅极堆叠件510上方沉积介电材料，然后各向异性地回蚀刻介电材料。回蚀刻工艺可以包括多步蚀刻以获得蚀刻选择性、灵活性以及期望的过蚀刻控制。
参照图1和图9A至图9B，方法1000进行至步骤1018，在第一S/D区450A中形成第一S/D部件610A并在第二S/D区450B中形成第二S/D部件610B。在一个实施例中，使第一S/D区450A中的第四鳍结构445的上部的部分和第二S/D区450B中的第三鳍结构440的上部的部分凹进。控制凹进工艺以使Ge部件430的部分保留在第三和第四鳍结构440和445中。然后，分别在第一和第二S/D区450A和450B中的凹进的第三和第四鳍结构440和445上外延生长第一S/D部件610A和第二S/D部件610B。第一S/D部件610A和第二S/D部件610B包括Ge、Si、GaAs、AlGaAs、SiGe、GaAsP或其他合适材料。可以通过一个或多个外延或外延的(epi)工艺形成第一S/D部件610A和第二S/D部件610B。也可以掺杂(诸如在外延工艺期间进行原位掺杂)第一S/D部件610A和第二S/D部件610B。可选地，不原位掺杂第一S/D部件610A和第二S/D部件610B，而是实施注入工艺(即，结注入工艺)以掺杂第一S/D部件610A和第二S/D部件610B。
在一个实施例中，通过外延生长掺杂有磷的SiGe层以形成SiGe:PS/D部件来形成第一S/D部件610A。而通过外延生长掺杂有硼的GeSn层以形成GeSnBS/D部件来形成第二S/D部件610B。
参照图1和图10A至图10B，方法1000进行至步骤1020，在衬底210上的伪栅极堆叠件510的间隙之间形成层间介电(ILD)层720。ILD层720包括氧化硅、氮氧化硅、低k介电材料或其他合适的介电材料。ILD层720可以包括单层或可选的多层。通过诸如CVD、ALD和旋涂(SOG)的合适的技术形成ILD层720。此后，可实施化学机械抛光(CMP)工艺以去除多余的ILD层720并平坦化SRAMFinFET器件200的顶面。
继续参照图1和图10A至图10B，方法1000进行至步骤1022，去除第一栅极区460A中的伪栅极堆叠件510以形成一个或多个第一栅极沟槽810A并去除第二栅极区460B中的伪栅极堆叠件510以形成一个或多个第二栅极沟槽810B。第二鳍结构330的上部暴露于第一栅极沟槽810A中，而第三鳍结构440的上部暴露于第二栅极沟槽810B中。伪栅极堆叠件510通过蚀刻工艺(诸如选择性湿蚀刻或选择性干蚀刻)去除，该蚀刻工艺被设计成相对于第一栅极沟槽810A中的第三半导体材料层216以及第二栅极沟槽810B中的第四半导体材料层420具有足够的蚀刻选择性。该蚀刻工艺可以包括利用相应的蚀刻剂的一个或多个蚀刻步骤。栅极硬掩模层516和间隔件520也被去除。可选地，可以通过包括光刻图案化和蚀刻工艺的一系列工艺去除伪栅极堆叠件510。
图1和图11A至图11B，方法1000进行至步骤1024，在衬底210上方形成第一高k/金属栅极(HK/MG)堆叠件910A和第二高k/金属栅极(HK/MG)堆叠件910B，包括分别包裹在第一栅极沟槽810A中的第四鳍结构445的部分上方以及第二栅极沟槽810B中的第三鳍结构440的部分上方。第一HK/MG堆叠件910A和第二HK/MG堆叠件910B包括栅极介电层和栅极介电层上的栅电极。在一个实施例中，栅极介电层包括具有高介电常数(在本实施例中，HK介电层的介电常数大于热氧化硅的介电常数)的介电材料层，并且栅电极包括金属、金属合金或金属硅化物。第一HK/MG堆叠件910A和第二HK/MG堆叠件910B的形成包括：沉积以形成各种栅极材料，以及CMP工艺以去除多余的栅极材料并平坦化NFET器件200A和PFET器件200B的顶面。
在一个实施例中，栅极介电层包括通过诸如原子层沉积(ALD)、CVD、热氧化或臭氧氧化的合适的方法沉积的界面层(IL)。IL包括氧化物、HfSiO和氮氧化物。HK介电层通过合适的技术沉积在IL上，合适的技术诸如ALD、CVD、金属有机CVD(MOCVD)、物理汽相沉积(PVD)、其他合适的技术或它们的组合。HK介电层可以包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)或其他合适的材料。栅极介电层包裹在第一栅极区460A中的第二鳍结构330的上部和第二栅极区460B中的第三鳍结构440的上部的上方。
金属栅(MG)电极可以包括单个层或可选的多层结构，诸如具有增强器件性能的功函的金属层(功函金属层)、衬垫层、润湿层、粘附层以及由金属、金属合金或金属硅化物构成的导电层的各种组合。MG电极可以包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、任意合适的材料或它们的组合。可以通过ALD、PVD、CVD或其他合适工艺形成MG电极。可以利用不同的金属层分别形成用于NFET200A和PFET200B的MG电极。可以实施CMP工艺以去除多余的MG电极。
参照图11C和图11D，在NFET器件200A中，第一栅极区460A包括包裹第四鳍结构445的上部上方的第一HM/MG910A。第四鳍结构445包括作为其上部的Ge部件430、作为其中间部分的半导体氧化物层324以及作为其底部的第一半导体材料层212。因此，在形成第四鳍结构445中的半导体氧化物层324期间，向第一栅极区460A引入适当的应变，而这会增大第一栅极区460A中的沟道区的电子迁移率。衬垫405覆盖第四鳍结构445的底部和中间部分的侧壁。半导体氧化物层324也将Ge部件430与第一半导体材料层212隔离以避免其不利影响。第一S/D区450A包括位于凹进的Ge部件430上方的SiGePS/D部件610A，SiGePS/D部件610A提供外延晶种层。
参照图11E和图11F，在PFET器件200B中，第二栅极区460B包括包裹第三鳍结构440的上部上方的第二HM/MG910B。第三鳍结构440包括作为其上部的Ge部件430、作为其中间部分的SiGe层214以及作为其底部的第一半导体材料层212。衬垫405覆盖第三鳍结构440的底部和中间部分的侧壁。第二S/D区450B包括位于凹进的Ge部件430上方的GeSnBS/D部件610B，GeSnBS/D部件610B提供外延晶种层。可选地，第二S/D区450B包括SiGeSnS/D部件。
本发明还论述了根据方法2000制造的如图12、图13A至图13B、图14A至图14B、图15A至图15B、图16A至图16B、图17A至图17B和图18A至图18D所示的FinFET器件200的若干不同的实施例。本发明在各个实施例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，而其本身并不表示所论述的各个实施例和/或配置之间的关系。
参照图12和图13A至图13B，方法2000开始于步骤2002，在NFET200A和PFET200B中的衬底2210中形成第五鳍结构2220和沟槽2230。衬底2210包括位于第一半导体材料层212上方的第二半导体材料层214和图案化的FHM222。第五鳍结构2220和沟槽2230通过诸如光刻和蚀刻工艺的工序形成。第五鳍结构2220和沟槽2230的形成在很多方面与以上结合图2所论述的第一鳍结构220的形成相类似。控制蚀刻工艺的深度，使得第二半导体材料层214的剩余部分具有第一厚度t1。
参考图12和图14B，方法2000进行至步骤2004，通过去除第二半导体材料层214的部分来延伸PFET200B中的沟槽2230的深度。如图所示，在对PFET器件200B中的沟槽2230进行延伸(或进一步凹进)之后，第二半导体材料层214的部分保留在PFET器件200B中并且具有第二厚度t2。为了清楚地更好描述，PFET中的第五鳍结构2220被称为第六鳍结构2234。
此外，在对PFET器件200B中的沟槽2230进行延伸之前，步骤2004包括在NFET器件200A上方形成第二FHM2235。如图14A所示，第二FHM2235包裹在NFET器件200A的第五鳍结构2220上方。第二FHM2235在很多方面与以上结合图2所论述的FHM222相类似。
参考图12和图15A至图15B，方法2000进行至步骤2006，在衬底2210上方形成第三FHM2240并且使沟槽2230进一步凹进。第三FHM2240形成在NFET器件200A和PFET器件200B中，包括包裹在第五和第六鳍结构2220和2234上方。第三FHM2240在很多方面与以上结合图2所论述的FHM222相类似。NFET器件200A和PFET器件200B中的沟槽2230均进一步凹进以延伸至第一半导体材料层212。因此，第二半导体材料层214的部分暴露在NFET器件200A和PFET器件200B的延伸的沟槽2230中。
参照图12和图16A至图16B，方法2000进行至步骤2008，将NFET器件200A和PFET器件200B中的暴露的第二半导体材料层214转化为半导体氧化物层324。步骤2008在很多方面与以上结合图3A至图3B论述的方法1000的步骤1006相类似。在形成半导体氧化物层324之后，通过合适的蚀刻工艺去除第三FHM2240。
参照图12，方法2000进行至步骤2010，在NFET器件200A和PFET器件200B中，在衬底210上方沉积衬垫405，然后用介电层410填充沟槽230。步骤2010在很多方面与以上结合图4A至图4B论述的方法1000的步骤1008相类似。
参照图12和图17A至图17B，方法2000进行至步骤2012，使NFET器件200A和PFET器件200B中的衬垫405和介电层410凹进。步骤2012在很多方面与方法1000的步骤1010相类似。在PFET器件200B中，第二半导体材料层214部分暴露，其形成第六鳍结构2234的上部，而未暴露的第二半导体材料层的214形成中间部分的上部，并且半导体氧化物层324形成中间部分的下部，以及第一半导体材料层212形成底部。在NFET器件200A中，第二半导体材料层214完全暴露，其形成第七鳍结构2440的上部，而半导体氧化物层324形成中间部分，并且第一半导体材料层212形成底部。
S/D区通过栅极区分隔开。为了清楚地更好描述，NFET器件200A中的S/D区和栅极区被称为第一S/D区450A和第一栅极区460A；PFET器件200B中的S/D区和栅极区被称为第二S/D区450B和第二栅极区460B。
参照图12，方法2000进行至步骤2014，在第六和第七鳍结构2234和2240中的暴露的第二半导体材料214上方包裹第四半导体材料层420和位于第四半导体材料层420上方的氧化物覆盖层425。步骤2014在很多方面与以上结合图6A至图6B论述的方法1000的步骤1012相类似。
参照图12，方法2000进行至步骤2016，实施高温退火以形成作为第六和第七鳍结构2234和2240的中心部分435的Ge部件430和作为第六和第七鳍结构2234和2240的上部的外层的氧化物层436。随后通过合适的蚀刻工艺去除氧化物外层436。步骤2016在很多方面与以上结合图7A至图7D论述的方法1000的步骤1014相类似。
参照图12，方法2000进行至步骤2018，在第一和第二栅极区460A和460B中，形成栅极堆叠件510以及位于栅极堆叠件510的侧壁上的侧壁间隔件520。步骤2018在很多方面与以上结合图8A至图8B论述的方法1000的步骤1016相类似。
参照图12，方法2000进行至步骤2020，在第一S/D区450A中形成第一S/D部件610A，并在第二S/D区450B中形成第二S/D部件610B。步骤2020在很多方面与以上结合图9A至图9B论述的方法1000的步骤1018相类似。
参照图12，方法2000进行至步骤2022，在衬底210上的伪栅极堆叠件510的间隙之间形成层间介电(ILD)层720。步骤2022在很多方面与以上结合图10A至图10B论述的方法1000的步骤1020相类似。
参照图12，方法2000进行至步骤2024，去除第一栅极区460A中的伪栅极堆叠件510以形成一个或多个第一栅极沟槽810A，以及去除第二栅极区460B中的伪栅极堆叠件510以形成一个或多个第二栅极沟槽810B。步骤2024在很多方面与以上结合图10A至图10B论述的方法1000的步骤1022相类似。
参照图12和图18A至图18B，方法2000进行至步骤2026，在衬底2210上方形成第一高k/金属栅极(HK/MG)堆叠件910A和第二高k/金属栅极(HK/MG)堆叠件910B，包括分别包裹在第一栅极沟槽810A中的第七鳍结构2440的部分上方以及第二栅极沟槽810B中的第六鳍结构2234的部分上方。步骤2026在很多方面与方法1000的步骤1024相类似。
参照图18C和图18D，在PFET器件200B中，第二栅极区460B包括包裹第六鳍结构2234的上部上方的第二HM/MG910B。第六鳍结构2234包括作为其上部的Ge部件430、作为其中间部分的上部的SiGe层214、作为其中间部分的下部的半导体氧化物层324、以及作为其底部的第一半导体材料层212。衬垫405覆盖第三鳍结构440的底部和中间部分的侧壁。第六鳍结构2234中的SiGe层214(中间部分的上部)给第二栅极区460B提供适当的应变以增强第二栅极区460B中的沟道区的沟道迁移率。半导体氧化物层324(中间部分的下部)将Ge部件430与第一半导体材料层212隔离开以避免其不利影响。
可以在方法1000之前、期间或之后执行额外的操作，并且对于该方法的其他实施例，上述的一些操作可以被取代或消除。例如，在一个实施例中，消除了步骤2004。因此，PFET器件200B中的第六鳍结构2234与NFET器件200A中的第七鳍结构2440相同。
基于以上所述，本发明提供了用于FinFET器件的鳍结构。该鳍结构使用纯Ge部件作为它的上部，通过在高温退火期间浓缩SiGe层中的Ge以使Ge集中于上部的中间部分而形成纯Ge部件。与通过外延生长形成纯Ge部件不同，通过浓缩Ge形成的Ge部件提供了低外延缺陷的优势。鳍结构还采用SiGeO层以将Ge部件与Si层(鳍结构的下部)分隔开，以减小不利的衬底的影响。在PFET器件中，鳍结构在Ge部件和SiGeO层之间采用SiGe层以提供合理的压缩沟道应变。鳍结构还采用薄SiGe层作为用于S/D部件形成的外延晶种层。该鳍结构展示了器件性能的改进。
本发明提供了半导体器件器件的实施例。该器件包括设置在衬底的n型FinFET(NFET)区域上方的第一鳍结构。第一鳍结构包括：硅(Si)层、设置在硅层上方的氧化硅锗(SiGeO)层和设置在SiGeO层上方的锗(Ge)部件。该器件还包括在p型FinFET(PFET)区域中的衬底上方的第二鳍结构。第二鳍结构包括：硅(Si)层、设置在硅层上方的凹进的氧化硅锗(SiGeO)层、设置在凹进的SiGeO层上方的外延硅锗(SiGe)层以及设置在外延SiGe层上方的锗(Ge)部件。
本发明还提供了一种鳍式场效应晶体管(FinFET)器件的另一个实施例。该器件包括具有n型FinFET(NFET)区域和p型FinFET(PFET)区域的衬底。该器件还包括在NFET区域中的衬底上方的第一鳍结构。第一鳍结构包括：作为第一鳍结构的上部的锗(Ge)层、作为第一鳍结构的中间部分的氧化硅锗(SiGeO)层和作为第一鳍结构的底部的硅(Si)层。该器件还包括位于PFET区域中的衬底上方的第二鳍结构。第二鳍结构包括：作为第二鳍结构的上部的锗(Ge)层、作为第二鳍结构的中间部分的外延硅锗(SiGe)层和作为第二鳍结构的底部的硅(Si)层。该器件还包括位于NFET区域中的衬底上方的高k(HK)/金属栅极(MG)堆叠件，其包裹在第一鳍结构的部分的上部上方；由HK/MG堆叠件分隔开且位于第一鳍结构的凹进的上部的上方的第一源极/漏极(S/D)部件；位于PFET区域中的衬底上方的高k(HK)/金属栅极(MG)堆叠件，其包裹在第二鳍结构的部分的上部上方；由HK/MG堆叠件分隔开且位于第二鳍结构的凹进的上部的上方的第二源极/漏极(S/D)部件。
本发明还提供了一种制造FinFET的方法。该方法包括：在衬底上方提供鳍结构。鳍结构包括：作为鳍结构的底部的第一半导体材料层；作为鳍结构的中间部分的半导体氧化物层；和作为鳍结构的上部的第三外延半导体材料层。该方法还包括在鳍结构上方沉积含锗半导体材料层；在含锗半导体材料层上方沉积氧化物层；应用高温退火以使锗(Ge)浓缩于鳍结构的上部的中心部分中并且在鳍结构的上部的外部中形成半导体氧化物；以及去除鳍结构的上部的外部的半导体氧化物。
以上概述了若干实施例的特征，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域普通技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以进行多种变化、替换以及改变。

Claims (10)

1.一种器件，包括：
第一鳍结构，设置在衬底的n型FinFET(NFET)区域上方，所述第一鳍结构包括：
硅(Si)层；
氧化硅锗(SiGeO)层，设置在所述硅层上方；及
锗(Ge)部件，设置在所述SiGeO层上方；以及
第二鳍结构，位于p型FinFET(PFET)区域中的所述衬底上方，所述第二鳍结构包括：
硅(Si)层；
凹进的氧化硅锗(SiGeO)层，设置在所述硅层上方；
外延硅锗(SiGe)层，设置在所述凹进的SiGeO层上方；及
锗(Ge)部件，设置在所述外延SiGe层上方。
2.根据权利要求1所述的器件，其中，所述第一鳍结构的中间部分的SiGeO层的厚度介于约20nm至约90nm的范围内。
3.根据权利要求1所述的器件，其中，所述第二鳍结构的中间部分的上部的外延SiGe层的厚度介于约10nm至约30nm的范围内。
4.根据权利要求1所述的器件，其中，所述第二鳍结构的中间部分的下部的凹进的SiGeO层的厚度介于约10nm至约60nm的范围内。
5.根据权利要求1所述的器件，还包括：
高k(HK)/金属栅极(MG)堆叠件，位于所述NFET区域中的所述衬底上方，包裹在所述第一鳍结构的一部分的上部上方；以及
第一源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第一鳍结构的凹进的上部的上方。
6.根据权利要求5所述的器件，其中，所述第一鳍结构的凹进的上部具有厚度在约3nm至约10nm的范围内的剩余的Ge部件。
7.根据权利要求5所述的器件，其中，所述第一S/D部件包括硅锗磷(SiGeP)。
8.根据权利要求1所述的器件，还包括：
高k(HK)/金属栅极(MG)堆叠件，位于所述PFET区域中的所述衬底上方，包裹在所述第二鳍结构的部分的上部上方；
第二源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第二鳍结构的凹进的上部的上方。
9.一种鳍式场效应晶体管(FinFET)器件，包括：
第一鳍结构，位于衬底的n型FinFET(NFET)区域上方，所述第一鳍结构包括：
锗(Ge)部件，作为所述第一鳍结构的上部；
氧化硅锗(SiGeO)层，作为所述第一鳍结构的中间部分；以及
硅(Si)层，作为所述第一鳍结构的底部；及
第二鳍结构，位于所述衬底的p型FinFET(PFET)区域上方，所述第二鳍结构包括：
锗(Ge)部件，作为所述第二鳍结构的上部；
外延硅锗(SiGe)层，作为所述第二鳍结构的中间部分；及
硅(Si)层，作为所述第二鳍结构的底部；
高k(HK)/金属栅极(MG)堆叠件，位于所述NFET区域中的所述衬底上方，包裹在所述第一鳍结构的一部分的上部上方；
第一源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第一鳍结构的凹进的上部的上方；
高k(HK)/金属栅极(MG)堆叠件，位于所述PFET区域中的所述衬底上方，包裹在所述第二鳍结构的一部分的上部上方；以及
第二源极/漏极(S/D)部件，由所述HK/MG堆叠件分隔开，位于所述第二鳍结构的凹进的上部的上方。
10.一种方法，包括：
在衬底上方提供鳍结构；所述鳍结构包括：
第一半导体材料层，作为所述鳍结构的底部；
半导体氧化物层，作为所述鳍结构的中间部分；以及
第三外延半导体材料层，作为所述鳍结构的上部；
在所述鳍结构上方沉积含锗半导体材料层；
在所述含锗半导体材料层上方沉积氧化物层；
应用高温退火以使锗(Ge)浓缩在所述鳍结构的上部的中心部分中并且在所述鳍结构的上部的外部中形成半导体氧化物；以及
去除所述鳍结构的上部的外部的所述半导体氧化物。
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US11563118B2 (en) 2023-01-24
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US20200052119A1 (en) 2020-02-13
US9224736B1 (en) 2015-12-29
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