TWI742607B - 半導體裝置結構及其形成方法 - Google Patents

半導體裝置結構及其形成方法 Download PDF

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TWI742607B
TWI742607B TW109112148A TW109112148A TWI742607B TW I742607 B TWI742607 B TW I742607B TW 109112148 A TW109112148 A TW 109112148A TW 109112148 A TW109112148 A TW 109112148A TW I742607 B TWI742607 B TW I742607B
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fin structure
source
dielectric
semiconductor
drain
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TW109112148A
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TW202107709A (zh
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江國誠
朱熙甯
蔡慶威
程冠倫
王志豪
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台灣積體電路製造股份有限公司
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Abstract

提供半導體裝置結構,半導體裝置結構包含基底和位於基底之上的介電鰭結構。半導體裝置結構還包含相鄰介電鰭結構的半導體鰭結構。半導體裝置結構還包含橫跨介電鰭結構和半導體鰭結構的金屬閘極堆疊。半導體裝置結構還包含位於半導體鰭結構之上的源極/汲極部件。半導體裝置結構還包含插入源極/汲極部件與介電鰭結構之間的源極/汲極間隔物。

Description

半導體裝置結構及其形成方法
本發明實施例是關於一種半導體裝置結構,且特別是有關於具有源極/汲極間隔物的半導體裝置結構及其形成方法。
電子工業對越來越小且越快的電子裝置的需求不斷增長,這些電子裝置同時能夠支持更多越來越複雜且精密的功能。 因此,製造低成本、高性能和低功率積體電路(integrated circuit,IC)是半導體工業持續的趨勢。 迄今為止,透過縮小半導體積體電路的尺寸(例如,最小特徵尺寸),並由此提高生產效率且降低相關成本,在很大程度上已實現了這些目標。 然而,這種小型化亦使半導體製造製程更趨複雜。 因此,實現半導體積體電路和裝置的持續發展要求在半導體製造製程和技術上有相似的發展。
最近導入多閘極(multi-gate)裝置,以致力於透過增加閘極-通道耦合(gate-channel coupling)來改善閘極控制,減少截止(OFF)狀態電流,並且減少短通道效應(short-channel effect,SCE)。 已導入的一種多閘極裝置是閘極全環繞(gate-all-around,GAA)電晶體。 閘極全環繞裝置名稱緣由是它的閘極結構可以環繞通道區延伸,從而自兩側或四側開啟通道。閘極全環繞裝置能與傳統的互補式金屬-氧化物-半導體(complementary metal oxide semiconductor,CMOS)製程兼容,並且這種結構允許它們在保持閘極控制和減輕短通道效應的同時大幅縮小尺寸。 在傳統製程中,閘極全環繞裝置在矽納米線(nanowire)中提供通道。 然而,圍繞納米線的閘極全環繞部件的製造整合可能具有挑戰性。 舉例而言,儘管目前的方法在許多方面都令人滿意,但是仍然需要持續的進行改進。
本發明實施例提供半導體裝置結構,半導體裝置結構包含基底和位於基底之上的介電鰭結構。半導體裝置結構還包含相鄰介電鰭結構的半導體鰭結構。半導體裝置結構還包含橫跨介電鰭結構和半導體鰭結構的金屬閘極堆疊。半導體裝置結構還包含位於半導體鰭結構之上的源極/汲極部件。半導體裝置結構還包含插入源極/汲極部件與介電鰭結構之間的源極/汲極間隔物。
本發明實施例提供半導體裝置結構,半導體裝置結構包含基底和位於基底之上的半導體鰭結構。半導體裝置結構含包含隔離結構,隔離結構包含圍繞半導體鰭結構的一直部分以及沿著基底的水平部分。半導體裝置結構還包含位於隔離結構的水平部分之上的介電鰭結構。半導體裝置結構還包含位於隔離結構的垂直部分正上方的多個源極/汲極間隔物。半導體裝置結構還包含插入源極/汲極間隔物之間的源極/汲極部件。
本發明實施例提供半導體裝置結構的形成方法,此方法包含形成半導體鰭結構於基底之上。此方法還包含順應性地形成絕緣材料沿著半導體鰭結構和基底。此方法還包含形成介電鰭結構相鄰半導體鰭結構且於絕緣材料之上。此方法還包含凹蝕絕緣材料以形成間隙於半導體鰭結構與介電鰭結構之間。此方法還包含形成第一介電材料於半導體鰭結構和介電鰭結構之上且填充間隙。此方法還包含蝕刻第一介電材料在半導體鰭結構和介電鰭結構之上的第一部分,以形成源極/汲極間隔物於間隙中。
以下內容提供了多個不同的實施例或範例,用於實現本發明實施例的不同部件。組件和配置的具體實施例或範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例來說,敘述中若提及第一部件形成於第二部件上(或之上),可能包含形成第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不直接接觸的實施例。另外,本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的,她們本身並非代表所討論各種實施例及/或配置之間有特定的關係。
本文描述實施例的一些變化。在各種示意圖與圖示實施例中,使用相似元件符號來表示相似元件。應注意的是,方法的前中後可提供額外步驟,並且對於其他一些方法實施例,可以取代或刪減一些步驟。
可透過任何適合方法圖案化以下所述的閘極全環繞(GAA)電晶體結構。舉例而言,可使用一或多道微影製程圖案化閘極全環繞電晶體結構,微影製程包含雙圖案(double patterning)或多圖案(multi-patterning)製程。一般而言,雙圖案或多圖案製程結合了微影與自對準(self-aligned)製程,其與直接的單微影製程所得到的圖案相比,得以創造出更小的節距(pitch)的圖案。舉例而言,在一實施例中,形成犧牲層於基底之上,並使用微影製程將其圖案化。使用自對準製程形成間隔物於圖案化犧牲層旁邊。接著移除犧牲層,留下的間隔物之後用來圖案化閘極全環繞結構。
提供半導體裝置結構的實施例,半導體裝置結構可包含半導體鰭結構、隔離結構、多個源極/汲極間隔物、以及源極/汲極部件。隔離結構包含圍繞半導體鰭結構的垂直部件。源極/汲極間隔物位於隔離部件的垂直部分正上方。源極/汲極部件插入這些源極/汲極間隔物之間。因為源極/汲極間隔物限制了源極/汲極部件的橫向成長,可形成源極/汲極部件具有較窄的寬度。由此,能降低半導體裝置的寄身電容(parasitic capacitance),從而提升半導體裝置的操作速度。
第1A-1M圖是根據本發明的一些實施例,繪示形成半導體裝置100在各種中間階段的透視示意圖。第1A-1至1M-1圖是根據本發明的一些實施例,繪示第1A-1M圖沿著線I-I之半導體結構的剖面示意圖。第1E-2至1M-2圖是根據本發明的一些實施例,繪示第1A-1M圖沿著線II-II之半導體結構的剖面示意圖。第1F-3至1M-3圖是根據本發明的一些實施例,繪示第1A-1M圖沿著線III-III之半導體結構的剖面示意圖。
根據一些實施例,提供基底102,如第1A和1A-1圖所示。根據一些實施例,形成多個半導體鰭結構104於基底102之上。
在一些實施例中,基底102是半導體基底,例如,矽基底。在一些實施例中,基底102包含元素半導體(例如,鍺);化合物半導體(例如,氮化鎵(GaN)、碳化矽(SiC)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)、及/或銻化銦(InSb));合金半導體(例如,SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP);或前述之組合。
在一些實施例中,基底102包含磊晶層(epi-layer)形成於基底之上。在一些實施例中,基底102是半導體上覆絕緣體(semiconductor-on-insulator,SOI)基底,其包含半導體基底、半導體基底之上的埋藏氧化物層、以及埋藏氧化物層之上的半導體層。
根據一些實施例,半導體鰭結構104在X方向上排列,且在Y方向上延伸。根據一些實施例,這些半導體鰭結構104各自包含下部104L和上部104U。根據一些實施例,半導體鰭結構104的下部104L是由部分的基底102形成。根據一些實施例,半導體鰭結構104的上部104U是由堆疊半導體結構形成,半導體結構包含交替堆疊於下部104L之上的第一半導體層106和第二半導體層108。
如後續將詳細說明,根據一些實施例,半導體鰭結構104的第一半導體層106會被移除,使得半導體鰭結構104的第二半導體層108形成奈米線結構,奈米線結構延伸於源極/汲極部件之間。根據一些實施例,第二半導體層108的奈米線結構會被閘極堆疊圍繞,以作為半導體裝置的通道區。舉例而言,第1A至1M-3所述實施例描述的製程和材料可用於形成的奈米線結構,此奈米線結構具有用於n型鰭式場效電晶體及/或p型鰭式場效電晶體之閘極全環繞設計。
在一些實施例中,半導體鰭結構104的形成包含形成堆疊半導體結構於基底102之上,堆疊半導體結構包含用於第一半導體層106的第一半導體材料與用於第二半導體層108的第二半導體材料。
根據一些實施例,用於第一半導體層106的第一半導體材料具有與用於第二半導體層108的第二半導體材料不同的晶格常數。在一些實施例中,第一半導體層106由矽鍺(SiGe)形成,其中鍺(Ge)在矽鍺中的百分比範圍在約20原子(atomic)/%至約50原子/%,而第二半導體層108由矽形成。在一些實施例中,第一半導體層106由Si1-x Gex 形成,其中x大於約0.3,或由鍺(Ge)形成;第二半導體層108是矽(Si)或Si1-y Gey 其中y小於0.4且x>y。
在一些實施例中,使用低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)、磊晶成長製程、其他適合方法、或前述之組合形成第一半導體材料和第二半導體材料。在一些實施例中,磊晶成長製程包含分子束磊晶法(molecular beam epitaxy,MBE)、金屬有機化學氣相沉積(metal organic chemical vapor deposition,MOCVD)、或氣相磊晶法(vapor phase epitaxy,VPE)。
在一些實施例中,每一個第一半導體層106的厚度範圍在約1.5奈米(nm)至約20奈米。在一些實施例中,這些第一半導體層106的厚度大致均勻。在一些實施例中,每一個第二半導體層108的厚度範圍在約1.5奈米至約20奈米。在一些實施例中,這些第二半導體層108的厚度大致均勻。
根據一些實施例,接著將包含第一半導體材料與第二半導體材料的堆疊半導體結構和下方的基底102圖案化為多個鰭結構104。
在一些實施例中,圖案化製程包含形成雙層硬遮罩層(包含硬遮罩層110和112)於堆疊半導體結構之上,並且通過雙層硬遮罩層蝕刻堆疊半導體結構與下方的基底102。在一些實施例中,第一硬遮罩層110是由氧化矽形成的墊氧化物層(pad oxide),其可透過熱氧化或化學氣相沉積(CVD)形成。在一些實施例中,第二硬遮罩層112是由氮化矽形成,其可透過化學氣相沉積(CVD)形成,例如低壓化學氣相沉積(LPCVD)或電漿增強化學氣相沉積(plasma-enhanced CVD,PECVD)形成。
在一些實施例中,圖案化製程的蝕刻製程移除堆疊半導體結構未被雙層硬遮罩層覆蓋的部分,並且進一步凹蝕基底102,從而形成多個溝槽105。
在一些實施例中,在蝕刻製程之後,基底102具有自溝槽105之間突出的部分,以形成半導體鰭結構104的下部104L。在一些實施例中,位於下部104L正上方之堆疊半導體結構的剩餘部分形成半導體鰭結構104的上部104U。
根據一些實施例,順應性地(conformally)形成絕緣材料114沿著半導體鰭結構104和基底102,如第1B和1B-1圖所示。根據一些實施例,絕緣材料114更沿著雙層硬遮罩層形成。根據一些實施例,絕緣材料114覆蓋基底102的上表面、半導體鰭結構104的側壁、以及雙層硬遮罩層的上表面和側壁。根據一些實施例,溝槽105被絕緣材料114部分填充。
在一些實施例中,絕緣材料114包含氧化矽、氮化矽、氮氧化矽(SiON)、其他適合絕緣材料、或前述之組合。在一些實施例中,使用低壓化學氣相沉積(LPCVD)、電漿增強化學氣相沉積(PECVD)、高密度電漿化學氣相沉積(high density plasma CVD,HDP-CVD)、高縱深比填溝製程(high aspect ratio process,HARP)、可流動化學氣相沉積(flowable CVD,FCVD)、原子層沉積(atomic layer deposition,ALD)、其他適合方法、或前述之組合,形成絕緣材料。
根據一些實施例,形成多個介電鰭結構116填充溝槽105的剩餘部分,如第1C和1C-1圖所示。根據一些實施例,形成介電鰭結構116相鄰半導體鰭結構104且於絕緣材料114之上。根據一些實施例,介電鰭結構116與半導體鰭結構104被絕緣材料114隔開。根據一些實施例,介電鰭結構116在X方向上排列,並且在Y方向上延伸。在一些實施例中,介電鰭結構116的上表面的水平低於半導體鰭結構104的上表面。
在一些實施例中,介電鰭結構116由具有小於約7之介電常數的介電材料形成。在一些實施例中,用於介電鰭結構116的介電材料為SiN、SiCN、SiOC、SiOCN、或前述之組合。在一些實施例中,形成介電鰭結構116包含沉積介電材料於絕緣材料114之上且填充溝槽105,後續進行回蝕(etch-back)製程。在一些實施例中,沉積製程是低壓化學氣相沉積(LPCVD)、電漿增強化學氣相沉積(PECVD)、高密度電漿化學氣相沉積(HDP-CVD)、高縱深比填溝製程(HARP)、可流動化學氣相沉積(FCVD)、原子層沉積(ALD)、其他適合技術、或前述之組合。在一些實施例中,回蝕製程是等向性(isotropic)蝕刻製程(例如,乾式化學蝕刻或濕蝕刻)、或異向性(anisotropic)蝕刻(例如,乾式電漿蝕刻)。
根據一些實施例,形成多個保護層118填充溝槽105的剩餘部分,如第1C和1C-1圖所示。根據一些實施例,形成保護層118在溝槽105中於介電鰭結構116正上方。根據一些實施例,溝槽105的剩餘部分大致上被保護層118完全填充。
在一些實施例中,保護層118由具有大於約7之介電常數的介電材料形成。在一些實施例中,用於保護層118的介電材料為Al2 O3 、HfO2 、ZrO2 、HfAlO、HfSiO、或前述之組合。在一些實施例中,形成保護層118包含沉積介電材料於介電鰭結構116之上且填充溝槽105,後續進行回蝕製程。在一些實施例中,沉積製程是低壓化學氣相沉積(LPCVD)、電漿增強化學氣相沉積(PECVD)、高密度電漿化學氣相沉積(HDP-CVD)、高縱深比填溝製程(HARP)、可流動化學氣相沉積(FCVD)、原子層沉積(ALD)、其他適合技術、或前述之組合。在一些實施例中,回蝕製程是等向性蝕刻製程(例如,乾式化學蝕刻或濕蝕刻)、或異向性蝕刻(例如,乾式電漿蝕刻)。
根據一些實施例,移除形成於半導體鰭結構104上方的絕緣材料114,以暴露出半導體鰭結構104的上表面,如第1C和1C-1圖所示。根據一些實施例,也移除雙層硬遮罩層(包含硬遮罩層110和112)。在一些實施例中,移除製程是化學機械研磨(chemical mechanical polish,CMP)製程或回蝕製程。在一些實施例中,在平坦化之後,半導體鰭結構104、絕緣材料114、與保護層118的上表面大致共平面。
根據一些實施例,凹蝕絕緣材料114以形成間隙122,如第1D和1D-1圖所示。根據一些實施例,每一個間隙122形成於一個半導體鰭結構104與一個介電鰭結構116之間。根據一些實施例,間隙122暴露出半導體鰭結構104的上部104U的側壁、介電鰭結構116的側壁、以及保護層118的側壁。在一些實施例中,凹蝕製程包含乾蝕刻、濕蝕刻、或前述之組合。
根據一些實施例,在凹蝕製程之後,絕緣材料114的剩餘部分形成隔離結構120。根據一些實施例,隔離結構120包含垂直部分120V和水平部分120H。
根據一些實施例,隔離結構120的垂直部分120V圍繞半導體鰭結構104的下部104L。根據一些實施例,隔離結構120的垂直部分120V也圍繞介電鰭結構116的下部。根據一些實施例,每一個隔離結構120的垂直部分120V插入一個半導體鰭結構104與一個介電鰭結構116之間。
根據一些實施例,隔離結構120的水平部分120H沿著基底102的上表面延伸於兩個相鄰的半導體鰭結構104之間。根據一些實施例,介電鰭結構116形成於隔離結構120的水平部分120H之上。
根據一些實施例,形成虛設閘極結構124橫跨半導體鰭結構104和介電鰭結構116,如第1E、1E-1和1E-2圖所示。根據一些實施例,虛設閘極結構124在Y方向上排列,且在X方向上延伸。根據一些實施例,虛設閘極結構124填入間隙122中。根據一些實施例,虛設閘極結構124覆蓋半導體鰭結構104的上表面和側壁、介電鰭結構116的側壁、以及保護層118的上表面和側壁。
在一些實施例中,虛設閘極結構124界定出半導體裝置的源極/汲極區和通道區。
根據一些實施例,虛設閘極結構124包含虛設閘極介電層126和虛設閘極電極層128。在一些實施例中,虛設閘極介電層126由一或多個介電材料形成,例如氧化矽、氮化矽、氮氧化矽(SiON)、HfO2 、HfZrO、HfSiO、HfTiO、HfAlO、或前述之組合。在一些實施例中,使用熱氧化、化學氣相沉積(CVD)、原子層沉積、物理氣相沉積(physical vapor deposition,PVD)、其他適合方法、或前述之組合,形成介電材料。
在一些實施例中,虛設閘極電極層128由導電材料形成。在一些實施例中,導電材料包含多晶矽(poly-Si)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬、或前述之組合。在一些實施例中,使用化學氣相沉積(CVD)、物理氣相沉積(PVD)、或前述之組合形成導電材料。
在一些實施例中,形成虛設閘極結構124包含順應性地形成用於虛設閘極介電層126的介電材料沿著基底102、半導體鰭結構104、介電鰭結構116、以及保護層118,形成用於虛設閘極電極層128的導電材料於介電材料之上,以及形成雙層硬遮罩層130於導電材料之上。
在一些實施例中,形成雙層硬遮罩層130包含形成氧化物層(例如氧化矽)於導電材料之上,形成氮化物層於氧化物層之上,以及使用微影與蝕刻製程,將氧化物層圖案化為層132且將氮化物層圖案化為層134。
在一些實施例中,形成虛設閘極結構124還包含通過雙層硬遮罩層130蝕刻介電材料和導電材料,以移除未被雙層硬遮罩層130覆蓋的介電材料和導電材料。在蝕刻製程之後,半導體鰭結構104的源極/汲極區暴露出來。在一些實施例中,蝕刻製程包含一或多乾蝕刻製程、濕蝕刻製程、或前述之組合。
根據一些實施例,全面地形成介電材料136於第1E圖的半導體結構之上,如第1F、1F-1、1F-2和1F-3圖所示。根據一些實施例,介電材料136順應性地沿著雙層硬遮罩層130的上表面和側壁、虛設閘極結構124的側壁、半導體鰭結構104的上表面、以及保護層118的上表面延伸。根據一些實施例,介電材料136填入間隙122中以覆蓋半導體鰭結構104的側壁、保護層118的側壁、介電鰭結構116的側壁、以及隔離結構120的垂直部分120V的上表面。在一些實施例中,間隙122大致上被介電材料136完全填充。
在一些實施例中,介電材料136具有大於約7的介電常數。舉例而言,介電材料136為Al2 O3 、HfO2 、ZrO2 、HfAlO、HfSiO、或前述之組合。在一些實施例中,使用低壓化學氣相沉積(LPCVD)、電漿增強化學氣相沉積(PECVD)、高密度電漿化學氣相沉積(HDP-CVD)、高縱深比填溝製程(HARP)、可流動化學氣相沉積(FCVD)、原子層沉積(ALD)、其他適合技術、或前述之組合,形成介電材料136。
根據一些實施例,蝕刻介電材料136以形成源極/汲極間隔物138,如第1G、1G-1、1G-2和1G-3圖所示。在一些實施例中,蝕刻製程是等向性蝕刻製程(例如,乾式化學蝕刻或濕蝕刻)、或異向性蝕刻(例如,乾式電漿蝕刻)。根據一些實施例,蝕刻製程移除介電材料136形成於半導體鰭結構104和保護層118上方的部分。根據一些實施例,在蝕刻製程之後,虛設閘極結構124的側壁的上部、半導體鰭結構104的上表面、以及保護層118的上表面暴露出來。
根據一些實施例,介電材料136的剩餘部分留在間隙122中,以形成源極/汲極間隔物138。根據一些實施例,源極/汲極間隔物138形成於隔離結構120的垂直部分120V正上方且介於半導體鰭結構104與介電鰭結構116之間。根據一些實施例,源極/汲極間隔物138沿著虛設閘極結構124的側壁的下部形成。源極/汲極間隔物138用於限制後續形成的源極/汲極部件的橫向成長,從而形成具有期望輪廓的源極/汲極部件。
根據一些實施例,形成閘極間隔物140沿著虛設閘極結構124的側壁,如第1H、1H-1、1H-2和1H-3圖所示。根據一些實施例,閘極間隔物140更沿著雙層硬遮罩層130的側壁形成。根據一些實施例,閘極間隔物140部分覆蓋半導體鰭結構104、源極/汲極間隔物138、以及保護層118。
在一些實施例中,閘極間隔物140由介電材料形成,例如氧化矽(SiO2 )、氮化矽(SiN)、碳化矽(SiC)、氮氧化矽(SiON)、氮碳化矽(SiCN)、氮碳氧化矽(SiOCN)、或前述之組合。在一些實施例中,使用沉積製程,後續進行蝕刻製程,形成閘極間隔物140。在些實施例中,沉積製程包含化學氣相沉積(例如,電漿增強化學氣相沉積(PECVD)、低壓化學氣相沉積(LPCVD)或高縱深比填溝製程(HARP))、及/或原子層沉積(ALD)。在一些實施例中,蝕刻製程是異向性蝕刻製程,例如乾式電漿蝕刻製程。
根據一些實施例,凹蝕半導體鰭結構104以形成源極/汲極凹陷142,如第1I、1I-1、1I-2和1I-3圖所示。根據一些實施例,蝕刻製程凹蝕未被閘極間隔物140、虛設閘極結構124、以及雙層硬遮罩層130覆蓋的半導體鰭結構104。根據一些實施例,源極/汲極凹陷142形成於這些源極/汲極間隔物138之間,並且暴露出半導體鰭結構104的下部104的上表面。在一些實施例中,凹蝕製程包含乾式蝕刻製程、濕式蝕刻製程、或前述之組合。
根據一些實施例,凹蝕半導體鰭結構104的蝕刻製程期間,蝕刻劑也蝕刻半導體結構的介電材料。根據一些實施例,在蝕刻製程期間,具有高介電常數的介電材料(例如,源極/汲極間隔物138和保護層118)的蝕刻速率低於具有低介電常數的介電材料(例如,介電鰭結構116)。由此,根據一些實施例,源極/汲極間隔物138和保護層118能保護介電鰭結構116。
根據一些實施例,蝕刻製程部分移除源極/汲極間隔物138未被閘極間隔物140覆蓋的上部。根據一些實施例,在蝕刻製程之後,凹蝕的源極/汲極間隔物138具有突出部138P於它的上表面處並且被閘極間隔物140覆蓋。
蝕刻製程也移除未被閘極間隔物140、虛設閘極結構124、以及雙層硬遮罩層130覆蓋的保護層118。根據一些實施例,在蝕刻製程之後,介電鰭結構116的上表面暴露出來。
根據一些實施例,形成源極/汲極部件144於源極/汲極凹陷142中,如第1J、1J-1、1J-2和1J-3圖所示。根據一些實施例,源極/汲極部件144形成於半導體鰭結構104的下部104L正上方。根據一些實施例,源極/汲極部件144形成於源極/汲極間隔物138之間,並且自源極/汲極間隔物138之間突出。
在一些實施例中,源極/汲極部件144由任何適合用於n型半導體裝置及p型半導體裝置的材料形成,例如,Ge、Si、GaAs、AlGaAs、SiGe、GaAsP、SiP、SiC、SiCP、或前述之組合。在一些實施例中,使用磊晶成長製程形成源極/汲極部件144,例如分子束磊晶法(MBE)、金屬有機化學氣相沉積(MOCVD)、氣相磊晶法(VPE)、其他適合磊晶成長製程、或前述之組合。
在一些實施例中,在磊晶成長製程期間,原位(in-situ)摻雜源極/汲極部件144。舉例而言,源極/汲極部件144可以是以硼(B)摻雜的磊晶成長的矽鍺(SiGe)。舉例而言,源極/汲極部件144可以是以碳(C)摻雜的磊晶成長的矽(Si)以形成矽:碳(Si:C)源極/汲極部件,是以磷(P)摻雜的磊晶成長的矽以形成矽:磷(Si:P)源極/汲極部件,或是以碳和磷兩者一起摻雜的磊晶成長的矽以形成矽碳磷(SiCP)源極/汲極部件。在一些實施例中,在磊晶成長製程之後,在一或多道植入製程中摻雜源極/汲極部件144。
根據一些實施例,因為源極/汲極部件144自源極/汲極間隔物138之間成長,源極/汲極部件144的橫向成長受到了源極/汲極間隔物138的限制。由此,源極/汲極部件144具有位於源極/汲極間隔物138之間的主體部144B。根據一些實施例,被源極/汲極間隔物138限制的主體部144B具有柱狀輪廓。
根據一些實施例,源籍/汲極部件144持續成長超出源極/汲極間隔物138上方。由此,根據一些實施例,源極/汲極部件144具有自源極/汲極間隔物138突出的頭部144H。根據一些實施例,未被源極/汲極間隔物138限制的頭部144橫向成長並且具有刻面(faceted)輪廓。
在一些實施例中,主體部144B在主體部144B底面處沿著X方向量測具有寬度W1。在一些實施例中,寬度W1範圍在約8奈米至約70奈米之間。在一些實施例中,主體部144B在主體部144B中間高度處沿著X方向量測具有寬度W2。在一些實施例中,寬度W2範圍在約8奈米至約70奈米。在一些實施例中,主體部144B在主體部144B的頂端處(或在源極/汲極間隔物138上表面的位置處)沿著X方向量測具有寬度W3。在一些實施例中,寬度W3範圍在約8奈米至約70奈米。在一些實施例中,寬度W1等於或大於寬度W2。在一些實施例中,寬度W2等於或大於寬度W3。也就是說,主體部144B可具有大致上一致的寬度或向上漸縮的寬度。
在一些實施例中,主體部144B沿著Z方向量測具有高度H1。在一些實施中,高度H1範圍在約40奈米至約80奈米。在一些實施例中,高度H1對寬度H1範圍在約0.5至約10。
在一些實施例中,頭部144H沿著X方向量測具有最大寬度W4。在一些實施例中,寬度W4範圍在約14奈米至約90奈米。在一些實施例中,寬度W4對寬度W1的比值範圍在約1.2至約1.8。
在一些實施例中,頭部144H沿著Z方向量測具有高度H2。在一些實施例中,高度H2範圍在約14奈米至約90奈米。在一些實施例中,高度H1對高度H2的比值範圍在約0.8至約3。
因為源極/汲極間隔物138限制源極/汲極部件144的橫向成長,所以與如果沒有形成源極/汲極間隔物的情況相比,源極/汲極部件144可具有更細長的柱狀輪廓(即,高度H1對寬度W1有較大的比值)。
根據一些實施例,形成接觸蝕刻停止層(contact etching stop layer,CESL)146於第1J圖的半導體結構之上,如第1K、1K-1、1K-2和1K-3圖所示。根據一些實施例,形成層間介電層(interlayer dielectric,ILD)148於接觸蝕刻停止層146之上。
根據一些實施例,順應性地形成接觸蝕刻停止層146沿著源極/汲極部件144的頭部144H的刻面、源極/汲極間隔物138的上表面、介電鰭結構116的上表面、源極/汲極間隔物138的突出部分138P的側壁、保護層118的側壁、以及閘極間隔物140的側壁。
在一些實施例中,接觸蝕刻停止層146由介電材料形成,例如氮化矽、氧化矽、氮氧化矽、其他適合介電材料、或前述之組合。在一些實施例中,全面地沉積用於接觸蝕刻停止層146的介電材料於第1J圖的半導體結構之上。沉積製程包含化學氣相沉積(例如,電漿增強化學氣相沉積(PECVD)、高縱深比填溝製程(HARP)、或前述之組合)、原子層沉積(ALD)、其他適合方法、或前述之組合。
在一些實施例中,層間介電層148由介電材料形成,例如四乙氧基矽烷(tetraethylorthosilicate,TEOS)氧化物、未摻雜的矽酸鹽玻璃(un-doped silicate glass,USG)、或摻雜的氧化矽,例如,硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、摻雜氟的矽酸鹽玻璃(fluoride-doped silicate glass,FSG)、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、及/或其他適合介電材料。在一些實施例中,使用化學氣相沉積(例如,高密度電漿化學氣相沉積(HDP-CVD)、電漿增強化學氣相沉積(PECVD)、高縱深比填溝製程(HARP))、原子層沉積(ALD)、其他適合方法、或前述之組合,形成用於層間介電層148的介電材料。
根據一些實施例,之後,對用於接觸蝕刻停止層146和層間介電層148的介電材料進行平坦化製程,例如,化學機械研磨(CMP)或回蝕製程。根據一些實施例,移除形成於虛設閘極結構124之上的介電材料,以暴露出虛設閘極電極層128的上表面。根據一些實施例,平坦化製程也移除雙層硬遮罩層130。
根據一些實施例,以金屬閘極堆疊150置換虛設閘極結構124,如第1L、1L-1、1L-2和1L-3圖所示。根據一些實施例,置換製程包含移除虛設閘極結構124、移除半導體鰭結構104的第一半導體層106、以及形成金屬閘極結構150以圍繞第二半導體層108。
在一些實施例中,移除虛設閘極結構124(包含虛設閘極電極層128和虛設閘極介電層126),以形成溝槽(未顯示)於閘極間隔物140之間。移除製程包含一或多道蝕刻製程。舉例而言,當虛設閘極電極層128是多晶矽時,可使用例如四甲基氫氧化銨(tetramethylammonium hydroxide,TMAH)溶液的濕蝕刻劑,以選擇性移除虛設閘極電極層128。舉例而言,接著可使用電漿乾蝕刻、乾式化學蝕刻、及/或濕蝕刻移除虛設閘極介電層126。
在一些實施例中,移除半導體鰭結構104的第一半導體層106,以形成間隙(未顯示)於第二半導體層108之間,且於最下面的第二半導體層108與下部104L之間。根據一些實施例,在移除第一半導體層106之後,每一個第二半導體層108的四個主表面(上表面、兩個側表面和下表面)暴露出來。根據一些實施例,暴露出來的第二半導體層108形成奈米線結構,奈米線結構可作用為所得到的半導體裝置的通道區,並且被金屬閘極堆疊150圍繞。
在一些實施例中,蝕刻製程包含選擇性濕蝕刻製程,例如,氫氧化氨-過氧化氫-水混合物(ammonia hydroxide-hydrogen peroxide-water mixture,APM)。在一些實施例中,濕蝕刻製程使用蝕刻劑,例如,氫氧化銨(ammonium hydroxide,NH4 OH)、四甲基氫氧化銨(TMAH)、乙二胺鄰苯(ethylenediamine pyrocatechol,EDP)、及/或氫氧化鉀(potassium hydroxide,KOH)溶液。
根據一些實施例,在虛設閘極結構124和第一半導體層106移除處的溝槽和間隙中,依序形成界面層152、閘極介電層154、和閘極電極層156。根據一些實施例,界面層152、閘極介電層154和閘極電極層156一起作用為金屬閘極堆疊150。
根據一些實施例,金屬閘極堆疊150圍繞第二半導體層108的奈米線結構。根據一些實施例,金屬閘極堆疊150在Y方向上排列,且在X方向上延伸。根據一些實施例,金屬閘極堆疊150延伸橫跨半導體鰭結構104和介電鰭結構116。
根據一些實施例,界面層152順應性地沿著第二半導體層108的主表面形成,以圍繞第二半導體層108。在一些實施例中,界面層152由化學形成的氧化矽形成。
根據一些實施例,閘極介電層154順應性地形成於界面層152上,以圍繞第二半導體層108。根據一些實施例,閘極介電層154更沿著保護層118的上表面和側壁、介電鰭結構116的側壁、隔離結構120的上表面、以及半導體鰭結構104的下部104L的上表面形成。在一些實施例中,閘極介電層154更沿著層間介電層148的上表面形成。
在一些實施例中,閘極介電層154由一或多層的介電材料形成,例如HfO2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2 -Al2O3 )合金、其他適合的高介電常數介電材料、或前述之組合。在一些實施例中,使用化學氣相沉積(CVD)、原子層沉積(ALD)、其他適合方法、或前述之組合形成閘極介電層154。
根據一些實施例,閘極電極層156形成於閘極介電層154上。根據一些實施例,虛設閘極結構124和第一半導體層106被移除之處的溝槽和間隙的剩餘部分被閘極電極層156完全填充。
在一些實施例中,閘極電極層156由一或多層的導電材料形成,例如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他適合材料、或前述之組合。在一些實施例中,使用化學氣相沉積(CVD)、原子層沉積(ALD)、電鍍(electroplating)、其他適合方法、或前述之組合形成閘極電極層156。
根據一些實施例,之後,對金屬閘極堆疊150進行平坦化製程,例如化學機械研磨(CMP)或回蝕製程,以移除形成於層間介電層148之上的金屬閘極堆疊150。根據一些實施例,在平坦化製程之後,層間介電層148的上表面暴露出來。
根據一些實施例,形成隔離結構162通過層間介電層148和金屬閘極堆疊150,如第1M、1M-1、1M-2和1M-3圖所示。根據一些實施例,隔離結構162在Y方向上延伸。根據一些實施例,隔離結構162形成於介電鰭結構116和保護層118正上方。
在一些實施例中,隔離結構162由絕緣材料形成。在一些實施例中,用於隔離結構162的絕緣材料包含SiO2 、SiON、SiN、SiC、SiOC、SiOCN、或前述之組合。
在一些實施例中,形成隔離結構162包含進行切割製程以形成溝槽通過層間介電層148和金屬閘極堆疊150。切割製程將金屬閘極堆疊150切割為多個子金屬閘極堆疊151。在一些實施例中,溝槽暴露出保護層118的上表面和側壁、以及介電鰭結構116的上表面。在一些實施例中,切割製程包含微影和蝕刻製程。
在一些實施例中,沉積用於隔離結構162的絕緣材料以填充溝槽。在一些實施例中,絕緣材料更沉積於層間介電層148和金屬閘極堆疊150之上。
在一些實施例中,之後,移除在層間介電層148和金屬閘極堆疊150之上的絕緣材料。在一些實施例中,移除製程是化學機械研磨(CMP)或回蝕製程。
根據一些實施例,形成多個接觸開口(未顯示)通過層間介電層148和接觸蝕刻停止層146。在一些實施例中,使用微影製程和蝕刻製程形成接觸開口。根據一些實施例,接觸開口暴露出源極/汲極部件144的上表面。在一些實施例中,蝕刻製程更凹蝕源極/汲極部件144的頭部144H。
在一些實施中,在蝕刻製程之後,頭部144H在頭部144H的上表面處沿著X方向量測具有寬度W5。在一些實施例中,寬度W5範圍在約14奈米至約90奈米。在一些實施例中,寬度W5對寬度W1的比值範圍在約1.2至約1.8。
在一些實施例中,在蝕刻製程之後,源極/汲極部件144的頭部144H沿著Z方向量測具有高度H3。在一些實施例中,高度H3。在一些實施例中,高度H3範圍在約7奈米至約45奈米。在一些實施例中,高度H1對高度H3的比值範圍在約1.5至約6。
根據一些實施例,形成矽化物158於源極/汲極部件144的上表面上,如第1M、1M-1、1M-2和1M-3圖所示。
在一些實施例中,矽化物158由WSi、NiSi、TiSi、CoSi、及/或其他適合矽化物材料形成。在一些實施例中,形成矽化物158包含沉積金屬材料於層間介電層148之上、且沿著接觸開口的側壁和底面,對金屬材料進行退火,使得金屬材料與源極/汲極部件144反應,並且蝕刻移除金屬材料未反應的部分。在一些實施例中,沉積製程包含化學氣相沉積、原子層沉積、物理氣相沉積、及/或其他適合方法。在一些實施例中,退火製程包含快速熱退火(rapid temperature anneal,RTA)製程。在一些實施例中,蝕刻製程包含濕蝕刻。
根據一些實施例,形成多個接觸件160通過層間介電層148並且落在矽化物158上,如第1M、1M-1、1M-2和1M-3圖所示。
在一些實施例中,接觸件160由導電材料形成,例如Co、Ni、W、Ti、Ta、Cu、Al、TiN、TaN、及/或其他適合導電材料。形成接觸件160包含沉積導電材料於層間介電層148之上且填充接觸開口,並且移除層間介電層148之上的導電材料。在一些實施例中,沉積製程包含化學氣相沉積(CVD)、原子層沉積(ALD)、物理氣相沉積(PVD)、及/或其他適合方法。在一些實施例中,移除製程是化學機械研磨(CMP)。
在形成接觸件160之後,製得半導體裝置100。
透過形成源極/汲極間隔物138來限制源極/汲極部件144的橫向成長,源極/汲極部件144的主體部144B可具有細長的柱狀輪廓。具有較窄寬度的源極/汲極部件144可降低閘極堆疊與源極/汲極部件之間的寄生電容,從而提升半導體裝置的操作速度。
此外,源極/汲極間隔物138由具有高介電常數(例如大於7)的介電材料形成,使得在形成源極/汲極凹陷142的蝕刻製程期間,源極/汲極間隔物138的消耗得以降低。如果源極/汲極間隔物138的消耗太多,則可能降低源極/汲極部件144的主體部144B的高度H1。因此,可形成源極/汲極部件144具有佔較大比例的主體部144B、以及占較小比例的頭部144H。也就是說,增加了高度H1對高度H3的比值。由此,可進一步降低閘極堆疊與源極/汲極部件之間的寄生電容,從而進一步提升半導體裝置的操作速度。
儘管第1A至1M-3圖所述實施例是使用於閘極全環繞裝置,但是實施例的觀點也可使用於鰭式場效電晶體(FinFET),並且於第2A至2E-3圖描述。
第2A-2E圖是根據本發明的一些實施例,繪示形成半導體裝置200在各種中間階段的透視示意圖。第2A-1至2E-1圖是根據本發明的一些實施例,繪示第2A-2E圖沿著線I-I之半導體結構的剖面示意圖。第2B-2至2E-2圖是根據本發明的一些實施例,繪示第2A-2E圖沿著線II-II之半導體結構的剖面示意圖。第2B-3至2E-3圖是根據本發明的一些實施例,繪示第2A-2E圖沿著線III-III之半導體結構的剖面示意圖。
根據一些實施例,提供基底102,如第2A和2A-1圖所示。根據一些實施例,形成多個半導體鰭結構204於基底102之上。根據一些實施例,半導體鰭結構204在X方向上排列,且在Y方向上延伸。
在一些實施例中,這些半導體鰭結構204是由部分的基底102形成。舉例而言,可對基底102進行圖案化製程形成半導體鰭結構204。
根據一些實施例,形成隔離結構120、介電鰭結構116、和保護層118於基底102之上,如第2A和2A-1圖所示。形成隔離結構120、介電鰭結構116、和保護層118的方法可與前述第1B至1D-1圖所述的方法相同或相似。
根據一些實施例,隔離結構120包含垂直部分120V和水平部分120H。隔離結構120的垂直部分120V圍繞半導體鰭結構204的下部和介電鰭結構116的下部。根據一些實施例,隔離結構120的水平部分120H沿著基底102的上表面延伸於兩個相鄰的半導體鰭結構204之間。
根據一些實施例,介電鰭結構116形成相鄰半導體鰭結構204且於隔離結構120的水平部分120H之上。根據一些實施例,介電鰭結構116在X方向上排列,並且在Y方向上延伸。根據一些實施例,保護層118形成於介電鰭結構116正上方。
根據一些實施例,形成虛設閘極結構124橫跨半導體鰭結構204和介電鰭結構116,如第2B、2B-1、2B-2和2B-3圖所示。根據一些實施例,雙層硬遮罩層130形成於虛設閘極結構124之上。根據一些實施例,虛設閘極結構124在Y方向上排列,且在X方向上延伸。根據一些實施例,虛設閘極結構124填入間隙122中。
根據一些實施例,形成源極/汲極間隔物138於間隙122中,如第2B、2B-1、2B-2和2B-3圖所示。根據一些實施例,源極/汲極間隔物138形成於隔離結構120的垂直部分120V正上方且介於半導體鰭結構204與介電鰭結構116之間。根據一些實施例,源極/汲極間隔物138沿著虛設閘極結構124的側壁的下部形成。
根據一些實施例,形成閘極間隔物140沿著虛設閘極結構124的側壁,如第2C、2C-1、2C-2和2C-3圖所示。根據一些實施例,閘極間隔物140部分覆蓋源極/汲極間隔物138和保護層118。
根據一些實施例,凹蝕半導體鰭結構204以形成源極/汲極凹陷(未顯示)。根據一些實施例,形成源極/汲極部件144於源極/汲極凹陷中,如第2C、2C-1、2C-2和2C-3圖所示。根據一些實施例,源極/汲極部件144形成於半導體鰭結構204的下部204L正上方。根據一些實施例,源極/汲極部件144形成於源極/汲極間隔物138之間,並且自源極/汲極間隔物138之間突出。
根據一些實施例,順應性地形成接觸蝕刻停止層146沿著源極/汲極部件144的頭部144H的刻面、源極/汲極間隔物138的上表面、介電鰭結構116的上表面、源極/汲極間隔物138的突出部分138P的側壁、保護層118的側壁、以及閘極間隔物140的側壁,如第2D、2D-1、2D-2和2D-3圖所示。根據一些實施例,形成層間介電層148於接觸蝕刻停止層146之上。
根據一些實施例,以金屬閘極堆疊150置換虛設閘極結構124,如第2D、2D-1、2D-2和2D-3圖所示。根據一些實施例,置換製程包含透過一或多道蝕刻製程移除虛設閘極結構124、以及形成金屬閘極結構150以覆蓋半導體鰭結構204的上部。
根據一些實施例,金屬閘極結構150包含界面層152、閘極介電層154和閘極電極層156。根據一些實施例,界面層152順應性地沿著半導體鰭結構204的上表面和側壁形成。
根據一些實施例,閘極介電層154順應性地形成於界面層152上。根據一些實施例,閘極介電層154更沿著保護層118的上表面和側壁、介電鰭結構116的側壁、以及隔離結構120的上表面形成。根據一些實施例,閘極電極層156形成於閘極介電層154上。
根據一些實施例,形成隔離結構162通過層間介電層148和金屬閘極堆疊150,如第2E、2E-1、2E-2和2E-3圖所示。根據一些實施例,隔離結構162在Y方向上延伸。根據一些實施例,隔離結構162形成於介電鰭結構116和保護層118正上方。
根據一些實施例,在形成隔離結構162之後,金屬閘極結構150被切割為多個子金屬閘極堆疊151。
根據一些實施例,形成矽化物158於源極/汲極部件144的上表面上,如第2E、2E-1、2E-2和2E-3圖所示。根據一些實施例,形成接觸件160通過層間介電層148並且落在矽化物158上,以製得半導體裝置200。形成矽化物158和接觸件160的方法可與前述第1M至1M-3圖所述的方法相同或相似。
如前所述,根據一些實施例,半導體裝置結構包含基底102、半導體鰭結構104、隔離結構120、多個源極/汲極間隔物138、以及源極/汲極部件144。根據一些實施例,隔離結構120包含圍繞半導體鰭結構104的垂直部分120V。根據一些實施例,源極/汲極間隔物138形成於隔離部件120的垂直結構120V正上方。根據一些實施例,源極/汲極部件144插入源極/汲極間隔物138之間。因為源極/汲極間隔物138限制了源極/汲極部件144的橫向成長,所以與如果沒有形成源極/汲極間隔物的情況相比,可形成源極/汲極部件144具有較窄的寬度。由此,具有較窄寬度的源極/汲極部件144能降低閘極結構與源極/汲極部件之間的寄身電容,從而提升半導體裝置的操作速度。
本文提供半導體裝置結構的實施例。半導體裝置結構可包含半導體鰭結構、圍繞半導體鰭結構的隔離部件、位於隔離部件之上的源極/汲極間隔物、以及插入源極/汲極間隔物之間的源極/汲極部件。因為源極/汲極間隔物限制了源極/汲極部件的橫向成長,所以源極/汲極部件可具有較窄的寬度。由此,可降低半導體裝置的寄身電容,從而提升半導體裝置的操作速度。
在一些實施例中,提供半導體裝置結構。半導體裝置結構包含基底和位於基底之上的介電鰭結構。半導體裝置結構還包含相鄰介電鰭結構的半導體鰭結構。半導體裝置結構還包含橫跨介電鰭結構和半導體鰭結構的金屬閘極堆疊。半導體裝置結構還包含位於半導體鰭結構之上的源極/汲極部件。半導體裝置結構還包含插入源極/汲極部件與介電鰭結構之間的源極/汲極間隔物。在一些實施例中,半導體裝置結構還包含圍繞介電鰭結構和半導體鰭結構的第一隔離結構。第一隔離結構包含插入介電鰭結構與半導體鰭結構之間的垂直部分、以及沿著基底的上表面的水平部分。在一些實施例中,源極/汲極間隔物位於第一隔離結構的垂直部分的正上方,且介電鰭結構位於第一隔離結構的水平部分之上。在一些實施例中,源極/汲極間隔物由Al2 O3 、HfO2 、ZrO2 、HfAlO、或 HfSiO形成,且介電鰭結構由SiN、SiCN、SiOC、或SiOCN形成。在一些實施例中,半導體裝置結構還包含位於介電鰭結構正上方的保護層、沿著金屬閘極堆疊且部分覆蓋保護層和源極/汲極間隔物的閘極間隔物、以及位於保護層和介電鰭結構正上方的第二隔離結構。在一些實施例中,源極/汲極間隔物具有位於源極/汲極間隔物的上表面的突出部分,突出部分被閘極間隔物覆蓋。 在一些實施例中,半導體裝置結構還包含位於半導體鰭結構之上且被金屬閘極堆疊圍繞的奈米線結構。
在一些實施例中,提供半導體裝置結構。半導體裝置結構包含基底和位於基底之上的半導體鰭結構。半導體裝置結構含包含隔離結構,隔離結構包含圍繞半導體鰭結構的一垂直部分以及沿著基底的水平部分。半導體裝置結構還包含位於隔離結構的水平部分之上的介電鰭結構。半導體裝置結構還包含位於隔離結構的垂直部分正上方的多個源極/汲極間隔物。半導體裝置結構還包含插入源極/汲極間隔物之間的源極/汲極部件。在一些實施例中,源極/汲極部件包含介於源極/汲極間隔物之間的主體部、以及自源極/汲極間隔物突出的頭部。在一些實施例中,主體部具有位於主體部的中間高度的第一寬度、以及位於主體部的底面的第二寬度,第二寬度等於或大於第一寬度。在一些實施例中,主體部具有第一高度,頭部具有第二高度,第一高度對第二高度的比值範圍在1.5至6。在一些實施例中,半導體裝置結構還包含沿著源極/汲極部件的頭部和源極/汲極間隔物的接觸蝕刻停止層、以及位於接觸蝕刻停止層之上的層間介電層。在一些實施例中,源極/汲極間隔物由介電常數大於7的第一介電材料形成,且介電鰭結構由介電常數小於7的第二介電材料形成。
在一些實施例中,提供半導體裝置結構的形成方法。此方法包含形成半導體鰭結構於基底之上。此方法還包含順應性地形成絕緣材料沿著半導體鰭結構和基底。此方法還包含形成介電鰭結構相鄰半導體鰭結構且於絕緣材料之上。此方法還包含凹蝕絕緣材料以形成間隙於半導體鰭結構與介電鰭結構之間。此方法還包含形成第一介電材料於半導體鰭結構和介電鰭結構之上且填充間隙。此方法還包含蝕刻第一介電材料在半導體鰭結構和介電鰭結構之上的第一部分,以形成源極/汲極間隔物於間隙中。此方法還包含蝕刻半導體鰭結構的上部,從而暴露出半導體鰭結構的下部。此方法還包含形成源極/汲極部件於半導體鰭結構的下部之上。在一些實施例中,第一介電材料具有第一介電常數,且介電鰭結構由第二介電材料形成,第二介電材料具有小於第一介電常數的第二介電常數。在一些實施例中,此方法還包含在形成第一介電材料之前,形成虛設閘極結構橫跨半導體鰭結構和介電鰭結構。第一介電材料更沿著虛設閘極結構形成,且蝕刻第一介電材料的第一部分的步驟包含蝕刻第一介電材料沿著虛設閘極結構形成的第二部分。在一些實施例中,此方法還包含形成閘極間隔物沿著虛設閘極結構且部分覆蓋源極/汲極間隔物、以及以金屬閘極堆疊置換虛設閘極結構。在一些實施例中,此方法還包含形成隔離結構通過金屬閘極堆疊且在介電鰭結構正上方。在一些實施例中,半導體鰭結構的上部包含多個第一半導體層與多個第二半導體層交替的一堆疊。
以上概述數個實施例之部件,以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解,他們能輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
100:半導體裝置 102:基底 104:半導體鰭結構 104L:下部 104U:上部 105:溝槽 106:第一半導體層 108:第二半導體層 110:硬遮罩層 112:硬遮罩層 114:絕緣材料 116:介電鰭結構 118:保護層 120:隔離結構 120V:垂直部分 120H:水平部分 122:間隙 124:虛設閘極結構 126:虛設閘極介電層 128:虛設閘極電極層 130:硬遮罩層 132:層 134:層 136:介電材料 138:源極/汲極間隔物 138P:突出部 140:閘極間隔物 142:源極/汲極凹陷 144:源極/汲極部件 144B:主體部 144H:頭部 146:接觸蝕刻停止層 148:層間介電層 150:金屬閘極堆疊 151:子金屬閘極堆疊 152:界面層 154:閘極介電層 156:閘極電極層 158:矽化物 160:接觸件 162:隔離結構 200:半導體裝置 204:半導體鰭結構 H1:高度 H2:高度 H3:高度 W1:寬度 W2:寬度 W3:寬度 W4:寬度 W5:寬度
藉由以下的詳細描述配合所附圖式,可以更加理解本發明實施例的內容。需強調的是,根據產業上的標準慣例,許多部件(feature)僅用於說明目的,並未按照比例繪製。事實上,為了能清楚地討論,各種部件的尺寸可能被任意地增加或減少。 第1A-1M圖是根據本發明的一些實施例,繪示形成半導體裝置在各種中間階段的透視示意圖。 第1A-1至1M-1圖是根據本發明的一些實施例,繪示第1A-1M圖沿著線I-I之半導體結構的剖面示意圖。 第1E-2至1M-2圖是根據本發明的一些實施例,繪示第1A-1M圖沿著線II-II之半導體結構的剖面示意圖。 第1F-3至1M-3圖是根據本發明的一些實施例,繪示第1A-1M圖沿著線III-III之半導體結構的剖面示意圖。 第2A-2E圖是根據本發明的一些實施例,繪示形成半導體裝置在各種中間階段的透視示意圖。 第2A-1至2E-1圖是根據本發明的一些實施例,繪示第2A-2E圖沿著線I-I之半導體結構的剖面示意圖。 第2B-2至2E-2圖是根據本發明的一些實施例,繪示第2A-2E圖沿著線II-II之半導體結構的剖面示意圖。 第2B-3至2E-3圖是根據本發明的一些實施例,繪示第2A-2E圖沿著線III-III之半導體結構的剖面示意圖。
102:基底
104L:下部
116:介電鰭結構
120:隔離結構
120H:水平部分
120V:垂直部分
138:源極/汲極間隔物
144:源極/汲極部件
146:接觸蝕刻停止層
148:層間介電層
158:矽化物
160:接觸件
162:隔離結構
H1:高度
H3:高度
W1:寬度
W2:寬度
W3:寬度
W5:寬度

Claims (15)

  1. 一種半導體裝置結構,包括:一基底;一介電鰭結構,位於該基底之上;一半導體鰭結構,相鄰該介電鰭結構;一金屬閘極堆疊,橫跨該介電鰭結構和該半導體鰭結構;一源極/汲極部件,位於該半導體鰭結構之上;一源極/汲極間隔物,插入該源極/汲極部件與該介電鰭結構之間;以及一第一隔離結構,橫跨該金屬閘極堆疊並形成於該介電鰭結構正上方。
  2. 如請求項1之半導體裝置結構,更包括:一第二隔離結構,圍繞該介電鰭結構和該半導體鰭結構,其中該第二隔離結構包括:一垂直部分,插入該介電鰭結構與該半導體鰭結構之間;以及一水平部分,沿著該基底的一上表面。
  3. 如請求項2之半導體裝置結構,其中:該源極/汲極間隔物位於該第二隔離結構的該垂直部分正上方,以及該介電鰭結構位於該第二隔離結構的該水平部分之上。
  4. 如請求項1至3任一項之半導體裝置結構,更包括:一保護層,位於該介電鰭結構正上方;以及一閘極間隔物,沿著該金屬閘極堆疊且部分覆蓋該保護層和該源極/汲極間隔物。
  5. 如請求項4之半導體裝置結構,其中該源極/汲極間隔物具有位 於該源極/汲極間隔物的一上表面的一突出部分,該突出部分被該閘極間隔物覆蓋。
  6. 如請求項1至3任一項之半導體裝置結構,更包括:一奈米線結構,位於該半導體鰭結構之上且被該金屬閘極堆疊圍繞。
  7. 一種半導體裝置結構,包括:一基底;一半導體鰭結構,位於該基底之上;一第一隔離結構,包括圍繞該半導體鰭結構的一垂直部分以及沿著該基底的一水平部分;一介電鰭結構,位於該第一隔離結構的該水平部分之上;一金屬閘極堆疊,圍繞該介電鰭結構與該半導體鰭結構;多個源極/汲極間隔物,位於該第一隔離結構的該垂直部分正上方;一源極/汲極部件,插入該等源極/汲極間隔物之間;以及一第二隔離結構,橫跨該金屬閘極堆疊並形成於該介電鰭結構正上方。
  8. 如請求項7之半導體裝置結構,其中該源極/汲極部件包括:一主體部,介於該等源極/汲極間隔物之間;以及一頭部,自該等源極/汲極間隔物突出。
  9. 如請求項8之半導體裝置結構,其中該主體部具有:一第一寬度,位於該主體部的中間高度;以及一第二寬度,位於該主體部的一底面,該第二寬度等於或大於該第一寬度。
  10. 如請求項8之半導體裝置結構,其中: 該主體部具有一第一高度,該頭部具有一第二高度,以及該第一高度對該第二高度的比值範圍在1.5至6。
  11. 如請求項8之半導體裝置結構,更包括:一接觸蝕刻停止層,沿著該源極/汲極部件的該頭部和該源極/汲極間隔物;以及一層間介電層,位於該接觸蝕刻停止層之上。
  12. 如請求項7至11任一項之半導體裝置結構,其中:該源極/汲極間隔物由介電常數大於7的一第一介電材料形成,以及該介電鰭結構由介電常數小於7的一第二介電材料形成。
  13. 一種半導體裝置結構的形成方法,包括:形成一半導體鰭結構於一基底之上;順應性地形成一絕緣材料沿著該半導體鰭結構和該基底;形成一介電鰭結構相鄰該半導體鰭結構且於該絕緣材料之上;凹蝕該絕緣材料以形成一間隙於該半導體鰭結構與該介電鰭結構之間;形成一第一介電材料於該半導體鰭結構和該介電鰭結構之上且填充該間隙;蝕刻該第一介電材料在該半導體鰭結構和該介電鰭結構之上的一第一部分,以形成一源極/汲極間隔物於該間隙中;蝕刻該半導體鰭結構的一上部,從而暴露出該半導體鰭結構的一下部;以及形成一源極/汲極部件於該半導體鰭結構的該下部之上。
  14. 如請求項13之半導體裝置結構的形成方法,更包括:在形成該第一介電材料之前,形成一虛設閘極結構橫跨該半導體鰭結構和該介電鰭結構,其中:該第一介電材料更沿著該虛設閘極結構形成,以及蝕刻該第一介電材料的該第一部分的步驟包括蝕刻該第一介電材料沿著該虛設閘極結構形成的一第二部分。
  15. 如請求項14之半導體裝置結構的形成方法,更包括:形成一閘極間隔物沿著該虛設閘極結構且部分覆蓋該源極/汲極間隔物;以及以一金屬閘極堆疊置換該虛設閘極結構。
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