TW201911389A - 鰭式場效電晶體的製造方法 - Google Patents
鰭式場效電晶體的製造方法 Download PDFInfo
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- TW201911389A TW201911389A TW106136211A TW106136211A TW201911389A TW 201911389 A TW201911389 A TW 201911389A TW 106136211 A TW106136211 A TW 106136211A TW 106136211 A TW106136211 A TW 106136211A TW 201911389 A TW201911389 A TW 201911389A
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Classifications
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Abstract
一種鰭式場效電晶體的製造方法,包含形成延伸進入半導體基板的複數個隔離區,凹陷這些隔離區,使得這些隔離區之間的複數個半導體條的部分突出高於這些隔離區以形成複數個半導體鰭片。此方法更包含凹陷這些半導體鰭片以形成複數個凹部,自這些凹部磊晶成長第一半導體材料,蝕刻第一半導體材料,以及自已回蝕刻的第一半導體材料磊晶成長第二半導體材料。
Description
本揭露實施例是關於一種鰭式場效電晶體的製造方法。
積體電路(IC)材料及設計的技術進步已經產生了好幾代的IC,每一代都具有比前幾代更小及更複雜的電路。在IC進化過程中,功能密度,例如,每一晶片面積的互連元件的數量通常增加,而幾何尺寸卻減小。這種縮減製程藉由提高生產效率及降低相關成本提供了好處。
這種縮減也增加了IC的製程及製造的複雜性。並且為了實現這些進步,類似於IC製程及製造方面的發展是需要的。舉例而言,鰭式場效電晶體(Fin Field-Effect Transistors,FinFET)已引入來替代平面電晶體。FinFET的結構及製造FinFET的方法正在開發中。
形成FinFET通常包含形成半導體鰭片、植入半導體鰭片以形成阱區、在半導體鰭片上形成虛擬閘極、蝕刻部分的半導體鰭片以及執行磊晶以再形成源極/汲極區。
本揭露實施例提供一種鰭式場效電晶體的製造方法,包含形成延伸進入半導體基板的複數個隔離區;凹陷這些隔離區,使得這些隔離區之間的複數個半導體條的部分突出高於這些隔離區以形成複數個半導體鰭片;凹陷這些半導體鰭片以形成複數個凹部;自這些凹部磊晶成長第一半導體材料;蝕刻第一半導體材料;以及自已回蝕刻的第一半導體材料磊晶成長第二半導體材料。
本揭露實施例提供一種鰭式場效電晶體的製造方法,包含形成閘極堆疊在第一半導體鰭片及第二半導體鰭片上;蝕刻第一半導體鰭片該第二半導體鰭片以形成第一凹部及第二凹部;分別自第一凹部及第二凹部成長第一磊晶區及第二磊晶區;回蝕刻第一磊晶區及第二磊晶區;以及分別自第一磊晶區及第二磊晶區成長第三磊晶區及第四磊晶區。
本揭露實施例提供一種鰭式場效電晶體的製造方法,包含形成閘極堆疊在半導體鰭片上;自半導體鰭片成長磊晶區以形成源極/汲極區的第一部分;蝕刻磊晶區;再成長磊晶區;以及形成矽化物區在磊晶區的頂表面上。
20‧‧‧基板
22‧‧‧襯墊氧化物
24‧‧‧硬遮罩
26‧‧‧溝槽
28‧‧‧半導體條
29‧‧‧間隙
30‧‧‧硬遮罩層
30’‧‧‧水平部分
30”‧‧‧底部
32‧‧‧半導體條基底
34‧‧‧STI區
34A‧‧‧組內STI區
34B‧‧‧組間STI區
36‧‧‧半導體鰭片
38‧‧‧虛擬閘極堆疊
40‧‧‧虛擬閘極介電質
42‧‧‧虛擬閘極電極
44‧‧‧硬遮罩
44A‧‧‧氧化矽
44B‧‧‧氮化矽層
46‧‧‧間隔層
48‧‧‧閘極間隔物
50‧‧‧鰭片間隔物
52‧‧‧凹部
53、60‧‧‧虛線
56、56A、56B‧‧‧磊晶區
57、59‧‧‧虛線區
58‧‧‧實線
70‧‧‧氣隙
72‧‧‧接觸蝕刻停止層
74‧‧‧層間介電質
76‧‧‧閘極介電質
78‧‧‧閘極電極
80‧‧‧替換閘極
82‧‧‧接觸開口
84‧‧‧金屬層
86‧‧‧金屬氮化物層
88‧‧‧源極/汲極矽化物區
90‧‧‧鰭式場效電晶體
92‧‧‧源極/汲極接觸插塞
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、222、224‧‧‧步驟
S1‧‧‧間隔
D1、D2‧‧‧深度
T1、T2‧‧‧厚度
A-A‧‧‧線
當與附圖一起閱讀時,自以下的詳細描述中可以最好地理解本揭露的各方面。值得注意的是,依照行業的標準方法,各 種特徵並未按比例繪製。事實上,為了討論的明確性,各種特徵的尺寸可任意增加或減少。
第1至20圖是依據一些實施例之形成鰭式場效電晶體(Fin Field-Effect Transistors,FinFETs)的中間階段的剖面圖及透視圖。
第21圖繪示依據一些實施例之用於形成FinFETs的製程流程。
以下揭露的內容提供了用於實現所提供標的之不同特徵的許多不同實施例或示例。以下描述組件及佈置的具體示例以簡化本揭露。當然,這些僅僅是示例,而不是限制性的。例如,於隨後的描述中在第二特徵上形成第一特徵可以包括第一及第二特徵的形成為直接接觸的實施例,亦可包括在第一及第二特徵之間可形成及/或設置附加特徵的實施例,使得第一及第二特徵可為非直接接觸。此外,本揭露可重複各種示例中的參考標號或字母。前述作法本身並不表示所討論的各種實施例及/或配置之間的關係。
此外,在本文中可使用諸如「在...之下」、「在下方」、「較低的」、「在...之上」、「較高的」等相對空間術語,以便於描述如圖所示之一個元件或特徵與另一個元件或特徵。相對空間術語旨在包括除了圖中所示的取向之外的使用或操作裝置的不同取向。裝置可以其它方式定向,例如,旋轉90度或其它取向,並且本文使用的相對空間描述符同樣可相 應地解釋。
依據各種示例性實施利提供鰭式場效電晶體及其製造方法,並說明形成FinFETs的中間階段。討論實施例的變型。在各種視圖及說明性實施例中,相同的參考標號用於表示類似的元件。
第1至20圖是依據一些實施例之形成FinFETs的中間階段的剖面圖及透視圖。第21圖所示的製程流程200中亦示意性地顯示第1至20圖所示的步驟。
第1圖繪示作為半導體晶片之一部分的基板20的透視圖。基板20為半導體基板,例如,矽基板、矽碳基板、矽鍺基板、絕緣體上矽基板或由其它半導體材料形成的基板。基板20也可以由其它半導體材料,例如,III-V化合物半導體材料形成。基板20可輕摻雜p型或n型雜質。
襯墊氧化物22及硬遮罩24形成在半導體基底20上。根據本揭露的一些實施例,襯墊氧化物22由氧化矽形成,氧化矽可以藉由氧化半導體機體20的表面層而形成。硬遮罩24可由氮化矽、氮氧化矽、碳化矽、碳氮化矽等形成。
接著,如第2圖所示,圖案化硬遮罩24、襯墊氧化物22及基板20以形成溝槽26。因此形成半導體條28。相應的步驟在第21圖所示之製程流程的步驟202中說明。溝槽26延伸至半導體基板20中,並且在長度方向彼此平行。依據本揭露的一些實施例,溝槽26的深度D1在約80nm與約130nm之間的範圍。應當理解,在整個說明書中引用的數值是示例,亦可採用不同的數值而不背離本揭露的原理。
所示的元件區是相應晶圓及晶片中的多鰭片元件區。依據本揭露的一些實施例,所示的元件區是將形成n型FinFET的n型FinFET區。依據本揭露的一些實施例,所示的元件區是將形成p型FinFET的p型FinFET區。在本揭露所示的示例性實施例中,描述兩個半導體條作為示例,且兩個半導體條組合使用以形成相同的FinFET。如第19圖所示的示例,應當理解地,可使用更多的半導體條以形成相同的FinFET。在整個說明書中,用於形成相同FinFET的多個半導體條組合並稱之為半導體條組。依據本揭露的一些實施例,相同條組中的相鄰半導體條28具有間隔S1,稱為「組內間隔」。組內間隔小於相鄰條組之間的間隔,相鄰條組之間的間隔稱為「組間間隔」。相鄰條組用於形成不同的FinFET。
參考第3A圖,形成硬遮罩層30以覆蓋半導體條28。相應的步驟在第21圖所示之製程流程的步驟204中說明。硬遮罩層30在半導體條28的頂表面及側壁上延伸。此外,硬遮罩層30在溝槽26下的部分半導體基板20的頂表面上延伸。選擇沉積方法使得所得到的硬遮罩層30實質上共形,垂直部分的厚度T1等於或實質上等於水平部分的厚度T2。舉例而言,厚度T1可以是厚度T2的大約80%到100%之間。依據本揭露的一些實施例,沉積方法包含原子層沉積(Atomic Layer Deposition,ALD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition,LPCVD)、化學氣相沉積(Chemical Vapor Deposition,CVD)等。
硬遮罩層30可由氧化鋁(Al2O3)、氮化矽、氧 化矽等形成。硬遮罩層30包含在相鄰半導體條28之間的兩個垂直部分,每一個垂直部分在其中之一半導體條28的側壁上。硬遮罩層30的兩個相鄰垂直部分彼此由間隙29間隔開,其亦顯示在第3B圖中。圖3B繪示第3A圖所示之結構的剖面圖,並繪示硬遮罩層30的兩個相鄰垂直部分之間的間隙29。間隙29具有非常高的縱橫比,縱橫比可以大於約15,並可在約15與約30之間。應當理解,間隙29是相應於溝槽26的未填充部分。在隨後的討論中,術語「外溝槽」用於表示位於相同條組中的最外側半導體條28的外側,即圖示的左側和右側上的溝槽26。術語「內溝槽」用於指在相同條組中的半導體條28之間的溝槽26。外溝槽26具有比間隙29更小的縱橫比。
接著參考第4圖,執行第一非等向性蝕刻以去除硬遮罩層30的水平部分。相應的步驟在第21圖所示之製程流程的步驟206中說明。可使用例如氟化氫(hydrogen fluoride,HF)作為蝕刻氣體,藉由乾蝕刻來執行第一非等向性蝕刻。在第一非等向性蝕刻之後保留半導體條28的側壁上的硬遮罩層30之垂直部分。
蝕刻的結果為露出硬遮罩24的頂表面。此外,亦露出外部溝槽26底部的半導體基板20的頂表面。在第一次非等向性蝕刻後,執行第二非等向性蝕刻以進一步蝕刻半導體基板20,使得外溝槽26進一步向下延伸至低於硬遮罩層30的底部邊緣。相應的步驟在第21圖所示之製程流程的步驟206中說明。依據本揭露的一些實施例,溝槽26的深度D2增加至約120nm與約160nm之間的範圍。依據一些示例性實施例,深度 差(D2-D1)可在約30nm與約50nm之間之間的範圍。
依據本揭露的一些實施例,使用與在第一非等向性蝕刻中使用的蝕刻劑氣體不同的蝕刻劑氣體來執行第二非等向性蝕刻。依據替代實施例,第一及第二非等向性蝕刻使用相同的蝕刻劑氣體,例如含氟氣體或含氯氣體來執行。第一非等向性蝕及第二非等向性蝕刻步驟可在相同的製程腔體中執行,兩步驟之間無間歇。在整個說明書中,半導體基板20中比延伸的外部溝槽26的底部高且低於半導體條28的部分稱為半導體條基底32,半導體條基底32是半導體條28所在的基底。半導體條基底32是在半導體基板20下面的主體部分之上。
在第二蝕刻步驟中,將硬遮罩24與硬遮罩層30的垂直部分組合用作第二非等向性蝕刻的蝕刻遮罩,因此半導體條基底32的側壁可垂直對準硬遮罩層30的垂直部分的外側壁。依據蝕刻製程,可能會形成一些底切,導致半導體條基底32之露出的側壁自硬遮罩層30的垂直部分相應的外邊緣傾斜及凹陷。
再參考第3B圖,在間隙29中,硬遮罩層30的水平部分30’位於間隙29的底部並露出於間隙29。水平部分30’可具有等於厚度T2的厚度,亦即外溝槽26中的底部30”之厚度。外溝槽26具有比間隙29更低的縱橫比。依據本揭露的一些實施例,由於間隙29(第3B圖)的高縱橫比,在第一及第二非等向性蝕刻製程中,在間隙29下的硬遮罩層30之底部30’的蝕刻速率比外溝槽26中底部30”的蝕刻速度低得多。因此,在第一蝕刻步驟及第二蝕刻步驟之後保留了底部30’。因此,直接 在間隙29下方的半導體條基底32的部分被保護免於第4圖所示的蝕刻步驟。
接著執行等向性蝕刻,例如濕蝕刻以去除硬遮罩層30的剩餘部分,因而露出半導體條基底32的側壁。相應的步驟在第21圖所示之製程流程的步驟208中說明。所得到的結構如第5圖所示,其顯示了位於同一半導體條基底32上的多個半導體條28。雖然說明了兩個半導體條28以作為示例,但是可以有單個、三個、四個或更多個半導體條28位於同一半導體條基底32上。在整個說明書中,半導體條基底32可認為是基板20的一部分,或者可認為是主體基板20上的分離部分。
接著如第6A圖所示,在溝槽26(第5圖)中形成隔離區34,隔離區34可以是淺溝槽隔離(Shallow Trench Isolation,STI)區。相應的步驟在第21圖所示之製程流程的步驟210中說明。前述形成可包含在半導體區20、28及32的露出部分上形成例如氧化矽的襯氧化物。用介電材料填充剩餘的溝槽26,例如,使用可流動化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)的氧化矽,並執行CMP對電介質材料的頂表面進行平坦化,使其與硬遮罩24的頂表面齊平,如第5圖所示。在CMP之後,去除第5圖的硬遮罩24。或者,CMP在半導體條28的頂表面上停止。在第6A圖所示的結構的俯視中,每一個半導體條基底32可以是由各個STI區34包圍的條帶,或者可以是細長條帶,細長條帶的相對端連接至主體半導體基板20。在整個說明書中,相同條組中兩個相鄰半導體條28之間的STI區34的部分稱為組內STI區34,亦表示為 34A。所示的組內STI區34A可代表複數個組內STI區34A。相同條組的最外側半導體條28之外側的STI區34稱為組間STI區,表示為34B。
第6B圖繪示依據本揭露之替代實施例所形成的STI區34。依據本揭露的一些實施例,藉由分開的製程形成組間STI區34B及組內STI區34A。舉例而言,組間STI區34B的形成包含第一蝕刻製程以蝕刻半導體基底20,然後填充相應的溝槽。在形成組間STI區34B之前或之後,形成組內STI區域34A,前述形成包含第二蝕刻製程以蝕刻半導體基底20,然後填充相應的溝槽。由於組內STI區34A及組間STI區34B是分別形成,所以它們可以由相同的介電質材料或選自氧化矽、氮化矽、碳化矽、氮氧化矽等不同的材料來形成。
接著參考第7圖,STI區34是凹陷的,使得所得到的STI區34的頂表面比半導體條28的頂表面低。相應的步驟在第21圖所示之製程流程的步驟212中說明。在整個說明書中,突出於STI區34頂表面之上的半導體條28的頂部稱為半導體鰭片36。剩餘STI區34的頂表面進一步高於半導體條基底32的頂表面。
參考第8圖,虛擬閘極堆疊38形成在半導體鰭片36上。相應的步驟在第21圖所示之製程流程的步驟214中說明。雖然說明了單個虛擬閘極堆疊38,但可同時形成複數個平行的虛擬閘極堆疊38,複數個虛擬閘極堆疊38中的每一個橫跨每個半導體條28。虛擬閘極堆疊38覆蓋半導體鰭片36的一些部分,留下未覆蓋的其它部分。依據本揭露的一些實施例, 虛擬閘極堆疊38包含虛擬閘極介電質40及虛擬閘極介電質40上方的虛擬閘極電極42。虛擬閘極介電質40可由氧化矽形成,且虛擬閘極電極42可由,例如多晶矽形成。硬遮罩44形成在虛擬閘極電極42上,並且在形成虛擬閘極電極42時用作蝕刻遮罩。硬遮罩44可包含氮化矽及/或氧化矽,且可以是單層或包含複數個層的複合層。舉例而言,硬遮罩44可包含氧化矽44A以及在氧化矽44A上的氮化矽層44B。虛擬閘極堆疊38的形成可包含將各個層作為覆蓋層沉積,然後蝕刻覆蓋層。虛擬閘極堆疊38可具有長度方向,前述長度方向實質上垂直於各個半導體鰭片36的長度方向。
進一步參考第8圖,形成間隔層46。I依據本揭露的一些實施例,間隔層46是由氧化矽、氮化矽、氮氧化矽、氧化碳氮化矽(SiOCN)、碳氮化矽(SiOC)、氧化鋁或前述之多層所形成。依據本揭露的一些實施例,間隔層46是由SiOCN形成,並可具有單層結構。依據替代實施例,間隔層46具有包含複數個層的複合結構。舉例而言,間隔層46可包含氧化矽層及氧化矽層上的氮化矽層。間隔層46使用共形沉積方法,例如ALD來形成。
第9圖繪示間隔層46的蝕刻以形成位於虛擬閘極堆疊38之側壁上的閘極間隔物48。依據本揭露的一些實施例,執行非等向性蝕刻以蝕刻間隔層46。去除間隔層46的水平部分。此外,由於半導體鰭片36的高度低於虛擬閘極堆疊38的高度,所以半導體鰭片36之側壁上的間隔層46垂直部分的高度相對較小,因此可在蝕刻中完全去除。或者,間隔層46 的一些部分可以留作鰭片間隔物50。另一方面,虛擬閘極堆疊38之側壁上的間隔層46垂直部分在蝕刻之後具有剩餘部分,剩餘部分稱為閘極間隔物48。由於蝕刻,閘極間隔物48的頂表面比虛擬閘極堆疊38的頂表面低。
第10圖繪示第9圖所示結構的剖面圖,其中自包含第9圖中的線A-A的垂直平面獲得剖面圖。此外,垂直平面與未被虛擬閘極堆疊38及閘極間隔物48覆蓋的半導體鰭片36的部分相交。在第10圖中,依據本揭露的一些實施例,鰭片間隔物50顯示為留在半導體鰭片36的側壁上。依據替代實施例,沒有鰭片間隔物留下。因此,使用虛線繪示出鰭片間隔件50,以表示它們可存在或可不存在。
接著如第11圖所示,蝕刻未被虛擬閘極堆疊38及第9圖之閘極間隔物48覆蓋的半導體鰭片36的露出部分以形成凹部52。相應的步驟在第21圖所示之製程流程的步驟216中說明。蝕刻是非等向性的,使得直接在第9圖之虛擬閘極堆疊38下方的半導體鰭片36的部分受到保護而不被蝕刻。在蝕刻半導體鰭片36之後,繼續蝕刻以去除STI區34之間的半導體條28的一些部分,使得凹部52在STI區34之間進一步延伸。可以使用例如混合氣體HBr/Cl2/O2、混合氣體HBr/Cl2/O2或混合氣體HBr/Cl2/O2/CF2來進行蝕刻。在形成溝槽52之後,可執行額外的蝕刻以去除如果此時仍留下之剩餘的鰭片間隔物50。蝕刻可以是等向性的,且可使用乾蝕刻或濕蝕刻來執行。
依據本揭露的一些實施例,在如第11圖所示的凹 陷及蝕刻步驟之後,組內STI區34A的頂表面實質上與組間STI區34B的頂表面齊平。依據替代實施例,調整蝕刻製程,例如調整蝕刻劑的組成,使得組內STI區34A的頂表面低於組間STI區34B的頂表面。無論組內STI區34A及組間STI區34B是否由相同或不同的材料形成,都可以實現這一點。使用虛線53繪示組內STI區34A的下表面。依據第6B圖所示的一些實施例,組內STI區34A及組間STI區34B是由不同的材料形成,這使得容易調整STI區34A及34B的頂表面高度。
第12至16圖繪示自剩餘半導體條28成長的重新成長磊晶區56之製程。磊晶區56形成所得之FinFET的源極/汲極區。當相應的FinFET是p型FinFET時,磊晶區56可包含摻雜有硼的矽鍺,或者當相應的FinFET是n型FinFET時,磊晶區56可包含矽磷或矽碳磷。
第12圖繪示磊晶區56進行磊晶之中間階段。藉由磊晶步驟形成的各個磊晶區56可選擇性地表示為磊晶區56A。依據其中各個元件是n型FinFET的一些實施例,磊晶區56A包含矽磷,其中磷具有第一濃度,依據一些實施例,濃度可在約1×1018/cm3至約1×1020/cm3之間。製程氣體可包含矽烷及含磷製程氣體。此外,可將蝕刻氣體,例如HCl加入至製程氣體中以達到選擇性生長。依據其中各個元件是p型FinFET的一些實施例,磊晶區56A包含矽鍺硼,硼具有第一濃度,依據一些實施例,濃度亦可在約1×1018/cm3至約1×1020/cm3之間。製程氣體可包含矽烷、鍺烷及含硼製程氣體。此外,可將蝕刻氣體,例如HCl加入至製程氣體中。
然後在第12圖中的磊晶區56A上執行回蝕刻。因此,去除虛線區57中的磊晶區56A的轉角部,所得到的磊晶區56A如第13圖所示。第12及13圖中所示的步驟在第21圖所示之製程流程的步驟218中說明。當蝕刻磊晶區56A的轉角部時,磊晶區56露出之非轉角部分也被回蝕刻。然而,磊晶區56A的轉角區比非轉角部分蝕刻得更快,因此磊晶區56A平滑化且為圓角狀。依據本揭露的一些實施例,用製程氣體,包含例如HCl之蝕刻氣體執行回蝕刻,且製程氣體不包含用於沉積磊晶區56的製程氣體。舉例而言,在回蝕中使用的製程氣體不包含矽烷及鍺烷。依據本揭露的替代實施例,使用蝕刻氣體,包含例如HCl的製程氣體及用於沉積磊晶區56的製程氣體,像是矽烷及鍺烷,來執行回蝕刻。因此,沉積及蝕刻同時發生。控制例如蝕刻氣體及沈積氣體的流速之製程條件,使得蝕刻速率高於沉積速率以達到淨效應為蝕刻。在整個說明書中,將沉積步驟及隨後的回蝕刻相結合稱為沈積-回蝕刻循環,沉積-回蝕循環的最終結果是沉積。
依據本揭露的一些實施例,回蝕刻例如,在蝕刻期間不在蝕刻腔體中施加偏壓功率時,是等向性的,使得磊晶區56A的側轉角區及頂轉角區以相似的速率回蝕刻。這可以在相鄰的FinFET接近時使用,且理想上限制磊晶區56A的橫向生長以防止不同FinFET的磊晶區彼此橋接。依據替代實施例,除了等向性效應,回蝕刻具有非等向性效應,例如,藉由在回蝕刻時在蝕刻腔體中施加偏壓功率,使得頂轉角比側轉角更加平坦。這將導致所得到的合併磊晶區的頂部表面輪廓更平 坦,如將在接下來的段落中討論的那樣。
在整個說明書中,磊晶區56A的磊晶被稱為層-1沉積。磊晶區56A具有比隨後成長之如第15圖中的磊晶區56B更低的磷濃度、硼濃度或鍺濃度。依據本揭露的一些實施例,層-1沉積包含一個沉積-回蝕刻循環或複數個沉積-回蝕循環,每個循環產生擴大的磊晶區56A。
第14圖繪示磊晶區56額外的沉積-回蝕刻循環。依據本揭露的一些實施例,磊晶區56在進一步成長之後具有由實線58標示位置的表面。在磊晶區56上執行回蝕刻,使表面凹陷至虛線60標示的位置。額外的沉積-回蝕刻循環的製程氣體及條件可類似於之前的沉積-回蝕刻循環中相應的製程氣體及條件。依據一些實施例,在第二沉積-回蝕刻循環中成長的磊晶區也是磊晶區56A,具有與第12圖中繪示的磊晶區56A相同的組成。依據替代實施例,第二沉積-回蝕刻循環中成長的磊晶區是磊晶區56B,將在後續段落中討論。
第15圖繪示之連續成長,或指成長及回蝕刻,以形成磊晶區56(以下稱為56B),造成離散的磊晶區56合併以形成連續的磊晶區56。可形成氣隙70並密封在磊晶區56中。依據本揭露的一些實施例,每一個氣隙70中包含圓形底部部分及三角形頂部部分。如圖所示,三角形頂部具有實質上直的邊緣。氣隙70也可具有其它形狀,形狀取決於磊晶製程及磊晶區56的材料。半導體鰭片36的位置亦顯示於圖中。由於半導體鰭片36不在所示的平面內,所以標示為虛線。
第12至16圖所示的沉積步驟可包含用於形成磊 晶區56A的層-1沉積及用於形成磊晶區56A上的磊晶區56B的層-2沉積步驟。磊晶區56A及56B的組合稱為磊晶區56。磊晶區56B具有與磊晶區56A不同的組成。舉例而言,磊晶區56B可具有比磊晶區56A更高的摻雜濃度。依據相應之各個元件是n型FinFET的一些實施例,磊晶區56B包含矽磷,矽磷當中的第二磷濃度高於磊晶區56A的第一磷濃度。舉例而言,第一磷濃度可在約1×1018/cm3至約1×1010/cm3的範圍之間,第二磷濃度可在約1×1019/cm3至約1×1021/cm3的範圍之間。第二磷濃度可比第一磷濃度高一個數量級、二個數量級以上。
依據相應之各個元件是p型FinFET的一些實施例,磊晶區56B包含矽鍺硼,矽鍺硼的硼具有第二硼濃度,高於磊晶區56A中的第一硼濃度。舉例而言,第一硼濃度可在約1×1018/cm3至約1×1010/cm3的範圍之間,第二硼濃度可在約1×1019/cm3至約1×1021/cm3的範圍之間。第二硼濃度可比第一硼濃度高一個數量級、二個數量級或更高。若SiGeB用於p型FinFET,則在磊晶區56B中的鍺原子百分比也可高於磊晶區56A中的鍺原子百分比。
依據一些實施例,自層-1沉積至層-2沉積的轉變發生在磊晶區56合併之前。所得到的結構類似於第15圖所示,其中磊晶區56B彼此合併,而磊晶區56A不合併。依據替代實施例,自層-1沉積至層-2沉積的轉變發生在磊晶區56合併之後。在所得到的結構中,磊晶區56A(而不是56B)將彼此合併。層1沉積及層-2沉積中的每一個可包含一個或多個沉積-回蝕刻循環。
離散磊晶區56的合併需要磊晶區56的橫向成長,當磊晶區56成長至高於STI區34的頂表面時發生橫向生長,因此無STI區34的區域會避免側向生長。依據本揭露的一些實施例,組內STI區34A具有如虛線53所示之頂表面,此頂表面低於組間STI區34B頂表面,因此最外部磊晶區56的外側壁比面向組間STI區34A的內側壁更晚開始橫向生長。這降低了磊晶區56橋接至相鄰FinFET的磊晶區的可能性,同時維持了用於合併相同FinFET的磊晶區56的橫向生長。
接著,執行回蝕刻,其中虛線區59表示在回蝕刻期間去除的部分磊晶區56。得到的結構如第16圖所示。應當理解地,除了轉角區之外的磊晶區56露出部分亦被回蝕刻。然而,磊晶區56的轉角部比其他區蝕刻得更快,因此磊晶區56平滑化且為圓角狀。
在磊晶區56的形成完成之後,磊晶區56的頂表面可類似於第16圖所示,存在輕微的上下拓撲。頂表面也可類似於第17圖所示,其中磊晶區56的頂表面具有直接在多個半導體條28上延伸的平坦部分,磊晶區56之頂表面的平坦部分在離散的磊晶區56彼此連接的位置上沒有可區分的凹陷。這是藉由例如在合併磊晶區56之後的至少一個沉積-回蝕刻或藉由在磊晶區56合併之後執行複數個沉積-回蝕刻循環而實現,其中每個沉積-回蝕刻循環皆造成頂部表面平坦化。
隨後,執行多個製程步驟以完成FinFET的形成。如第17圖所示,在磊晶區56和虛擬閘極堆疊38上形成接觸蝕刻停止層(Contact etch stop layer,CESL)72及層間介電 質(Inter-Layer Dielectric,ILD)74,可參見第9圖。相應的步驟在第21圖所示之製程流程的步驟220中說明。執行平面化,例如使用化學機械拋光(Chemical Mechanical Polish,CMP)或機械研磨的以除去CESL 72及ILD 74的多餘部分,直到露出如第9圖的虛擬閘極堆疊38。用替換閘極取代虛擬閘極堆疊38。未顯示形成替換閘極的步驟。然而,在第20圖中顯示所得到的替換閘極80。如第20圖所說明,替換閘極80包含位於相應半導體鰭片36的頂表面及側壁上的閘極介電質76以及閘極介電質76上的閘極電極78。閘極介電質76可包含經由熱氧化形成的界面層。閘極介電質76的形成還可包含一個或多個沉積步驟,且所得到的閘極介電質76的形成層可包含高k介電質材料。然後閘極電極78形成在閘極介電質76上,閘極電極78可由金屬層形成。
在形成替換閘極80之後,執行第18圖所示的製程步驟,蝕刻ILD 74及CESL 72以形成接觸開口82,使得磊晶區56露出。相應的步驟在第21圖所示之製程流程的步驟222中說明。接著,形成金屬層84及金屬氮化物層86。依據本揭露的一些實施例,金屬層84由鈦形成,金屬氮化物層86由氮化鈦形成。層84及86至少形成在磊晶區56的頂表面上,並可以是延伸至磊晶區56之側壁及面向下的小平面上的共形層。接著參考第19圖執行退火,並且在所得的鰭式場效電晶體90的源/汲區之磊晶區56的表面上形成源極/汲極矽化物區88。相應的步驟在第21圖所示之製程流程的步驟224中說明。然後源極/汲極接觸插塞92形成在ILD74中,並電性連接至相應的源極/ 汲極矽化物區88。鰭式場效電晶體90就此形成。
第20圖繪示鰭式場效電晶體90的剖面圖,第20圖是自第19圖中的平面交叉線20-20獲得剖面圖。圖20繪示複數個替換閘極80及複數個源極/汲極區56。複數個源極/汲極區56由複數個替換閘極80共享作為共用源極區或共用汲極區。
本揭露的實施例具有一些有利的特徵。組內STI區限制了磊晶區的生長,因而有助於形成氣隙。此外,磊晶源極/汲極區的沉積及蝕刻導致磊晶源極/汲極區的頂表面具有更平坦的頂表面,所得到的FinFET可實現更好的性能。
依據本揭露的一些實施例,一種鰭式場效電晶體的製造方法包含形成延伸進入半導體基板的複數個隔離區;凹陷這些隔離區,使得這些隔離區之間的複數個半導體條的部分突出高於這些隔離區以形成複數個半導體鰭片;凹陷這些半導體鰭片以形成複數個凹部;自這些凹部磊晶成長第一半導體材料;蝕刻第一半導體材料;以及自已回蝕刻的第一半導體材料磊晶成長第二半導體材料。
在一實施例中,蝕刻第一半導體材料是在磊晶成長第一半導體材料之後執行。
在一實施例中,第二半導體材料與第一半導體材料不同。
在一實施例中,第二半導體材料具有比第一半導體材料更高的n型摻雜濃度。
在一實施例中,第二半導體材料具有比第一半導體材料更高的p型摻雜濃度。
在一實施例中,自不同這些凹部開始成長的第二半導體材料彼此合併,自不同這些凹部開始成長的第一半導體材料彼此不合併。
在一實施例中,回蝕刻包含非等向性蝕刻。
在一實施例中,回蝕刻包含等向性蝕刻。
依據本揭露的一些實施例,一種鰭式場效電晶體的製造方法包含形成閘極堆疊在第一半導體鰭片及第二半導體鰭片上;蝕刻第一半導體鰭片該第二半導體鰭片以形成第一凹部及第二凹部;分別自第一凹部及第二凹部成長第一磊晶區及第二磊晶區;回蝕刻第一磊晶區及第二磊晶區;以及分別自第一磊晶區及第二磊晶區成長第三磊晶區及第四磊晶區。
在一實施例中,當第一磊晶區及第二磊晶區彼此間隔開時,執行回蝕刻第一磊晶區及第二磊晶區。
在一實施例中,當第一磊晶區及第二磊晶區彼此接合時,執行回蝕刻第一磊晶區及第二磊晶區。
在一實施例中,第三磊晶區及第四磊晶區彼此連接,且具有氣隙密封在第三磊晶區與第四磊晶區連接處的下方。
上述方法更包含形成第一隔離區在第一半導體鰭片及第二半導體鰭片之間該第一隔離區具有第一底面;以及形成第二隔離區在第一半導體鰭片的外側上,其中第一隔離區及第二隔離區位於第一半導體鰭片的相對側上,第二隔離區具有比該第一底面低的一第二底面。
在一實施例中,形成第一隔離區及形成第二隔離 區是在共同的製程中執行。
在一實施例中,在不同的處理製程中執行形成第一隔離區及形成第二隔離區,第一隔離區及第二隔離區是由不同材料所構成。
依據本揭露的一些實施例,一種鰭式場效電晶體的製造方法包含形成閘極堆疊在半導體鰭片上;自半導體鰭片成長磊晶區以形成源極/汲極區的第一部分;蝕刻磊晶區;再成長磊晶區;以及形成矽化物區在磊晶區的頂表面上。
在一實施例中,在蝕刻磊晶區時,回蝕刻磊晶區的轉角區。
在一實施例中,使用不含矽及鍺之製程氣體執行蝕刻該磊晶區。
在一實施例中,使用氯化氫作為製程氣體執行蝕刻磊晶區。
在一實施例中,使用包含矽或鍺的第一製程氣體及包含氯化氫的第二製程氣體來執行成長磊晶區。
依據本揭露的一些實施例,一種鰭式場效電晶體的製造方法包含形成第一隔離區及第二隔離區,在第一隔離區及第二隔離區之間具有半導體鰭片,其中第一隔離區相較於第二隔離區延伸至更深的半導體基板內;使半導體鰭片凹陷,以在第一隔離區及第二隔離區之間形成凹陷;執行第一磊晶自凹部成長半導體區;蝕刻半導體區;以及執行第二磊晶以擴大半導體區。在一實施例中,形成第一隔離區及第二隔離區在分開的製程中執行。在一實施例中,第一隔離區及第二隔離區由不 同的介電質材料形成。在一實施例中,形成第一隔離區及第二隔離區是在共同的製程中執行。
依據本揭露的一些實施例,一種鰭式場效電晶體的製造方法包含形成延伸至半導體基板中的第一隔離區及第二隔離區域;形成第一半導體鰭片及第二半導體鰭片,其中第一半導體鰭片在第一隔離區及第二隔離區之間,第二隔離區在第一半導體鰭片及第二半導體鰭片之間,其中第一隔離區相較於第二隔離區延伸進入更深的半導體基板;使第一半導體鰭片及第二半導體鰭片凹陷,分別形成第一凹部及第二凹部;以及自第一凹部及第二凹部成長半導體區,其中氣隙密封在半導體區下方,且氣隙與第二隔離區域重疊。此方法更包含蝕刻半導體區;以及執行第二磊晶以擴大半導體區。在一實施例中,執行生長半導體區以沉積第一半導體材料,並且在第二磊晶中沉積不同於第一半導體材料的第二半導體材料。
依據本揭露的一些實施例,一種鰭式場效電晶體的製造方法包含形成第一隔離區;形成第二隔離區,其中半導體條位於第一隔離區及第二隔離區之間,第一隔離區及第二隔離區由不同的材料形成;凹陷第一隔離區及第二隔離區,使得半導體條的一部分突出高於第一隔離區及第二隔離區以外形成半導體鰭片;形成閘極堆疊在半導體鰭片的第一部分上;蝕刻半導體鰭片的第二部分以形成凹部;自凹部成長第一半導體材料;蝕刻第一半導體材料;以及在第一半導體材料上成長第二半導體材料。在一實施例中,氣隙密封在第一及第二半導體材料之下。在一實施例中,第二半導體材料具有不同於第一 半導體材料的組成。
上述概述了幾個實施例的特徵,使得所屬領域具有通常知識者可更好地理解本揭露的各方面。所屬領域具有通常知識者應當理解,他們可輕易地以本揭露內容為基礎設計或修改以用於執行與本文介紹的實施例具有相同目的或實現相同優點的其它製程及結構。本領域技術人員還應當意識到,這種等同的結構不脫離本揭露的精神及範圍,並且在不脫離本揭露的精神及範圍的情況下,它們可以進行各種改變,替換及變更。
Claims (20)
- 一種鰭式場效電晶體的製造方法,包含:形成延伸進入一半導體基板的複數個隔離區;凹陷該些隔離區,使得該些隔離區之間的複數個半導體條的部分突出高於該些隔離區以形成複數個半導體鰭片;凹陷該些半導體鰭片以形成複數個凹部;自該些凹部磊晶成長一第一半導體材料;蝕刻該第一半導體材料;以及自已回蝕刻的該第一半導體材料磊晶成長一第二半導體材料。
- 如請求項1所述之鰭式場效電晶體的製造方法,其中蝕刻該第一半導體材料是在磊晶成長該第一半導體材料之後執行。
- 如請求項1所述之鰭式場效電晶體的製造方法,其中該第二半導體材料與該第一半導體材料不同。
- 如請求項3所述之鰭式場效電晶體的製造方法,其中該第二半導體材料具有比該第一半導體材料更高的n型摻雜濃度。
- 如請求項3所述之鰭式場效電晶體的製造方法,其中該第二半導體材料具有比該第一半導體材料更高的p型摻雜濃度。
- 如請求項1所述之鰭式場效電晶體的製造方法,其中自不同該些凹部開始成長的該第二半導體材料彼此合併,自不同該些凹部開始成長的該第一半導體材料彼此不合併。
- 如請求項1所述之鰭式場效電晶體的製造方法,其中該回蝕刻包含一非等向性蝕刻。
- 如請求項1所述之鰭式場效電晶體的製造方法,其中該回蝕刻包含一等向性蝕刻。
- 一種鰭式場效電晶體的製造方法,包含:形成一閘極堆疊在一第一半導體鰭片及一第二半導體鰭片上;蝕刻該第一半導體鰭片及該第二半導體鰭片以形成一第一凹部及一第二凹部;分別自該第一凹部及該第二凹部成長一第一磊晶區及一第二磊晶區;回蝕刻該第一磊晶區及該第二磊晶區;以及分別自該第一磊晶區及該第二磊晶區成長一第三磊晶區及一第四磊晶區。
- 如請求項9所述之鰭式場效電晶體的製造方法,其中當該第一磊晶區及該第二磊晶區彼此間隔開時,執 行回蝕刻該第一磊晶區及該第二磊晶區。
- 如請求項9所述之鰭式場效電晶體的製造方法,其中當該第一磊晶區及該第二磊晶區彼此接合時,執行回蝕刻該第一磊晶區及該第二磊晶區。
- 如請求項9所述之鰭式場效電晶體的製造方法,其中該第三磊晶區及該第四磊晶區彼此連接,且具有一氣隙密封在該第三磊晶區與該第四磊晶區連接處的下方。
- 如請求項9所述之鰭式場效電晶體的製造方法,更包含:形成一第一隔離區在該第一半導體鰭片及該第二半導體鰭片之間,該第一隔離區具有一第一底面;以及形成一第二隔離區在該第一半導體鰭片的外側上,其中該第一隔離區及該第二隔離區位於該第一半導體鰭片的相對側上,其中該第二隔離區具有比該第一底面低的一第二底面。
- 如請求項13所述之鰭式場效電晶體的製造方法,其中形成該第一隔離區及形成該第二隔離區是在共同的製程中執行。
- 如請求項13所述之鰭式場效電晶體的製造方法,其中在不同的處理製程中執行形成該第一隔離區及形成該第二隔離區,該第一隔離區及該第二隔離區是由不同材 料所構成。
- 一種鰭式場效電晶體的製造方法,包含:形成一閘極堆疊在一半導體鰭片上;自該半導體鰭片成長一磊晶區以形成一源極/汲極區的一第一部分;蝕刻該磊晶區;再成長該磊晶區;以及形成一矽化物區在該磊晶區的頂表面上。
- 如請求項16所述之鰭式場效電晶體的製造方法,其中在蝕刻該磊晶區時,回蝕刻該磊晶區的轉角區。
- 如請求項16所述之鰭式場效電晶體的製造方法,其中使用不含矽及鍺之製程氣體執行蝕刻該磊晶區。
- 如請求項16所述之鰭式場效電晶體的製造方法,其中使用氯化氫作為製程氣體執行蝕刻該磊晶區。
- 如請求項16所述之鰭式場效電晶體的製造方法,其中使用包含矽或鍺的一第一製程氣體及包含氯化氫的一第二製程氣體來執行成長該磊晶區。
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US11038058B2 (en) | 2019-04-26 | 2021-06-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US11038061B2 (en) | 2019-04-26 | 2021-06-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
TWI742607B (zh) * | 2019-04-26 | 2021-10-11 | 台灣積體電路製造股份有限公司 | 半導體裝置結構及其形成方法 |
US11664454B2 (en) | 2019-04-26 | 2023-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming semiconductor device structure |
US11961913B2 (en) | 2019-04-26 | 2024-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device structure and method for forming the same |
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US10777664B2 (en) | 2020-09-15 |
US10141431B1 (en) | 2018-11-27 |
TWI641031B (zh) | 2018-11-11 |
KR102117979B1 (ko) | 2020-06-03 |
CN109326561A (zh) | 2019-02-12 |
US20190097026A1 (en) | 2019-03-28 |
DE102017124145B4 (de) | 2023-04-06 |
CN109326561B (zh) | 2021-05-14 |
DE102017124145A1 (de) | 2019-01-31 |
KR20190013400A (ko) | 2019-02-11 |
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