TW201440439A - 電路裝置及電子機器 - Google Patents

電路裝置及電子機器 Download PDF

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TW201440439A
TW201440439A TW103106883A TW103106883A TW201440439A TW 201440439 A TW201440439 A TW 201440439A TW 103106883 A TW103106883 A TW 103106883A TW 103106883 A TW103106883 A TW 103106883A TW 201440439 A TW201440439 A TW 201440439A
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circuit
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transistor
buried layer
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TWI573400B (zh
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Isamu Moriya
Atsushi Yamada
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Seiko Epson Corp
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Abstract

本發明係一種電子電路，其包含因雜訊產生源與雜訊而受到不良影響之類比電路、邏輯電路，在與基板不同之導電性之埋入雜質層上構成有上述類比電路、邏輯電路之至少其中一部分，且其周圍之至少一部分由與基板不同之雜質層包圍，從而阻礙來自雜訊產生源之雜訊之傳播。

Description

電路裝置及電子機器
本發明係關於一種電路裝置及電子機器等。
作為驅動直流馬達之馬達驅動器，已知藉由控制截斷電流而控制馬達之轉數之方法。該方法中，藉由感測電阻而將流動於橋式電路中之電流進行電流/電壓轉換，且藉由比較該電壓與基準電壓而檢測截斷電流。然後，將該檢測結果反饋至控制電路，且藉由對橋式電路之驅動信號進行PWM(Pulse Width Modulation，脈衝寬度調變)控制而使馬達以固定之速度旋轉。
例如於專利文獻1中，揭示有於此種馬達驅動器中提高截斷電流之檢測精度之方法。該方法中，對H橋之每半橋設置感測電阻，藉由一電阻而檢測充電期間之電流已達到特定之電流，且藉由另一電阻而檢測衰減期間之電流已達到特定之電流。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2008-042975號公報
並不限於如上所述之馬達驅動器，於進行切換動作之電路中，藉由該切換動作而反覆地使電流導通、斷開，故而存在基板電位產生 變動之問題。該基板電位之變動有可能對該基板上所構成之電路之動作造成影響。
例如於如上所述之馬達驅動器中，為了驅動馬達而需要大電流，而且藉由截斷動作而反覆地使電流導通、斷開，故而馬達驅動器之基板電位產生變動。於基板上所構成之基準電壓產生電路或電壓檢測電路受到電位變動之影響，故而截斷電流之檢測值會產生偏差，使控制為固定之馬達之旋轉速度之精度降低。
根據本發明之若干態樣，可提供一種可降低由基板電位之變動所造成的對電路動作之影響之電路裝置及電子機器等。
本發明之一態樣係關於一種電路裝置，其包含：第1電路，其包括形成於P型基板上之第一N型埋入層上之DMOS(Double-Diffused Metal Oxide Semiconductor，雙擴散金屬氧化物半導體)構造之電晶體；及第2電路，其包括形成於與上述第一N型埋入層分離之第二N型埋入層上CMOS(Complementary Metal Oxide Semiconductor，互補金屬氧化物半導體)構造之電晶體。
根據本發明之一態樣，包含CMOS構造之電晶體之第2電路係形成於與第一N型埋入層分離之第二N型埋入層上，且第2電路藉由第二N型埋入層而與P型基板隔離。藉此，可降低由基板電位之變動所造成的對電路動作之影響。
又，於本發明之一態樣中，亦可為，上述第2電路之區域由設定上述第二N型埋入層之電位之N型插栓區域包圍。
如此一來，藉由第二N型埋入層與包圍其之N型插栓區域，而可將第2電路與P型基板隔離。又，由於藉由N型插栓而設定N型埋入層之電位，故而可將第2電路與P型基板電性隔離。
又，於本發明之一態樣中，亦可為，上述CMOS構造之電晶體在 形成於上述第二N型埋入層上之P型層上形成。
如此一來，可形成藉由第二N型埋入層而與P型基板隔離之P型層，且於該被隔離之P型層上，可構成包含CMOS構造之電晶體之第2電路。
又，於本發明之一態樣中，亦可為，上述P型層為磊晶層。
如此一來，藉由於第二N型埋入層上形成磊晶層，而可形成P型埋入層作為與P型基板隔離之P型層。
又，於本發明之一態樣中，亦可包含：墊，其供給上述P型基板之電位；第1配線，其用以自上述墊對上述P型層供給電位；及第2配線，其用以自上述墊對上述P型基板供給電位。
如此一來，可對與P型基板隔離之P型層，以與P型基板不同之配線(第1配線)而供給電位。藉此，可抑制電位變動經由配線而自P型基板向P型層傳遞。
又，於本發明之一態樣中，亦可為，上述CMOS構造之電晶體之P型電晶體包含：形成於上述P型層上之N型井、形成於上述N型井上之P型源極區域、及形成於上述N型井上之P型汲極區域，且上述CMOS構造之電晶體之N型電晶體包含：形成於上述P型層上之P型井、形成於上述P型井上之N型源極區域、及形成於上述P型井上之N型汲極區域。
如此一來，可在與第一N型埋入層分離之第二N型埋入層上，形成包含CMOS構造之N型電晶體及CMOS構造之P型電晶體之第2電路。
又，於本發明之一態樣中，亦可為，上述DMOS構造之電晶體之N型電晶體包含：形成於上述第一N型埋入層上之深N型井、形成於上述深N型井上之P型層、形成於上述P型層上之N型源極區域、及形成於上述深N型井上之N型汲極區域。
又，於本發明之一態樣中，亦可為，上述DMOS構造之電晶體之P型電晶體包含：形成於上述第一N型埋入層上之深N型井、形成於上述深N型井上之P型層、形成於上述深N型井上之P型源極區域、及形成於上述P型層上之P型汲極區域。
根據該等本發明之一態樣，可於第一N型埋入層上，形成包含DMOS構造之N型電晶體或DMOS構造之P型電晶體之第1電路。
又，於本發明之一態樣中，亦可為，上述第1電路包含輸出用以驅動馬達之截斷電流之橋式電路，且上述第2電路包含檢測流動於上述橋式電路中之電流之檢測電路。
如此一來，可由橋式電路與檢測電路形成藉由截斷電流而驅動馬達之馬達驅動電路。P型基板之電位會因橋式電路之切換動作而擺動，但由於可藉由第二N型埋入層而隔離檢測電路，故而可減輕截斷電流之檢測誤差。
又，於本發明之一態樣中，亦可為，上述檢測電路包含：基準電壓產生電路，其產生基準電壓；電壓檢測電路，其比較基於上述電流之電壓與上述基準電壓；及控制電路，其根據上述電壓檢測電路之比較結果而控制上述橋式電路。
如此一來，藉由比較基於截斷電流之電壓與基準電壓，而可將流動於馬達中之截斷電流控制為固定。
又，於本發明之一態樣中，亦可為，上述第2電路包含控制上述第1電路之電路、或檢測上述第1電路之電壓或電流之電路。
根據本發明之一態樣，可將控制第1電路之電路、或檢測第1電路之電壓或電流之電路與P型基板隔離，故而可準確地控制第1電路，或可準確地檢測第1電路之電壓或電流。
又，於本發明之一態樣中，亦可為，上述第1電路係進行反覆地切換輸出電流或輸出電壓之動作之電路。
根據本發明之一態樣，即便於藉由第1電路所進行之切換動作而使P型基板之電位產生變動之情形時，亦因第2電路與P型基板隔離而可抑制切換動作對第2電路造成之影響。
又，本發明之另一態樣係關於一種電子機器，其包含如上述任一項之電路裝置。
10‧‧‧第1區域
20‧‧‧第2區域
31~33‧‧‧邊界區域
41‧‧‧P型基板
51~53‧‧‧N型埋入層
61、62‧‧‧深N型井
71‧‧‧P型體
81~84、85a、85b‧‧‧N型插栓
91~98‧‧‧P型層
101、102‧‧‧P型埋入層
111‧‧‧P型井
112、113a、113b‧‧‧N型井
121~129、123a、123b‧‧‧N型層
131~136、137a、137b‧‧‧P型層
141~143、141a、141b、144a、144b‧‧‧閘極層
151、151a、151b、152a、152b‧‧‧絕緣層
161‧‧‧HPOF(P型雜質層)
171a、171b、172a、172b‧‧‧N型層
200‧‧‧電路裝置
210‧‧‧橋式電路
220‧‧‧電壓檢測電路
221‧‧‧比較器
230‧‧‧基準電壓產生電路
240‧‧‧控制電路
250‧‧‧檢測電路
280‧‧‧馬達
290‧‧‧感測電阻
300‧‧‧處理部
310‧‧‧記憶部
320‧‧‧操作部
330‧‧‧輸入輸出部
340‧‧‧匯流排
CP‧‧‧寄生電容
Deep NWEL‧‧‧深N型井
Ich‧‧‧截斷電流
LV NWEL‧‧‧低耐壓N型井
LV PWEL‧‧‧低耐壓P型井
NBL‧‧‧N型埋入層
Nplug‧‧‧N型插栓
NWEL‧‧‧N型井
OUT1、OUT2‧‧‧端子
PBL‧‧‧P型埋入層
Pbody‧‧‧P型體
P-Epi‧‧‧P型磊晶層
Psub‧‧‧P型基板
PWEL‧‧‧P型井
Q1~Q4‧‧‧DMOS電晶體
RNF、RNFS‧‧‧端子
t0~t5‧‧‧時間
TC1、TC2‧‧‧充電期間
TD1、TD2‧‧‧衰減期間
TVB‧‧‧端子
VBB‧‧‧電源電壓
VR‧‧‧基準電壓
VS‧‧‧電壓
圖1係本實施形態之比較例之基板構成。
圖2係本實施形態之基板構成例。
圖3係電路裝置之構成例。
圖4係電路裝置之動作說明圖。
圖5係電路裝置之動作說明圖。
圖6係電路裝置之動作說明圖。
圖7係DMOS構造之N型電晶體之詳細之構成例。
圖8係DMOS構造之P型電晶體之詳細之構成例。
圖9(A)~(E)係DMOS構造之電晶體之製造製程流程。
圖10(A)~(D)係DMOS構造之電晶體之製造製程流程。
圖11(A)~(C)係DMOS構造之電晶體之製造製程流程。
圖12(A)~(C)係DMOS構造之電晶體之製造製程流程。
圖13係電子機器之構成例。
以下，對本發明之較佳之實施形態詳細地進行說明。再者，以下說明之本實施形態並非不合理地限定申請專利範圍中記載之本發明之內容，未必本實施形態中說明之所有構成作為本發明之解決手段為必需。
1.比較例之基板構成
圖1中，表示本實施形態之比較例之基板構成。圖1係構成電路 裝置之積體電路裝置之基板之剖面圖。
再者，以下，以電路裝置為例如圖3中下文所敍述般之馬達驅動器之情形為例進行說明，但本實施形態並不限定於此，可應用於進行驅動電流或驅動電壓之切換動作之各種電路裝置。例如，亦可應用於藉由電晶體之切換而驅動LC(電感電容)諧振電路以產生所需之電壓之切換調節器等。
於基板上，配置有：配置有第1電路之第1區域10、配置有第2電路之第2區域20、設置於第1區域10之一端部之邊界區域31、及設置於第1區域10與第2區域20之間之邊界區域32。第1電路係包含DMOS(Double-diffused Metal Oxide Semiconductor，雙擴散金屬氧化物半導體)電晶體之橋式電路(例如圖3之橋式電路210)。再者，第1電路並不限定於橋式電路，只要係進行驅動電流之切換動作之電路即可。第2電路係包含CMOS(Complementary Metal Oxide Semiconductor，互補金屬氧化物半導體)電晶體之電路(例如圖3之檢測電路250)。
此處，將與基板之平面垂直之方向(厚度方向)中之相對於基板而形成有電路之側(藉由半導體製程而積層各層之側)之方向稱為「上」，將其相反方向稱為「下」。
於第1區域10，形成有DMOS構造之N型電晶體(以下稱為N型DMOS)。具體而言，於作為矽基板之P型基板41上形成有N型埋入層51(NBL：N+ Buried Layer)，於N型埋入層51上形成有N型DMOS之深N型井61。於深N型井61之源極側形成有P型體71(P型雜質層)，於P型體71上形成有P型層131(P型雜質層)與N型層122(N型雜質層)。該N型層122係與N型DMOS之源極區域對應。於深N型井61之汲極側，形成有與N型DMOS之汲極區域對應之N型層123。於深N型井61上，與N型層123接觸而形成有絕緣層151(例如LOCOS(local oxidation of silicon，矽局部氧化))，於P型體71、深N型井61、及絕緣層151上形成有閘極層141(例如多晶矽層)。
於邊界區域31，設置有用以對N型埋入層51供給電位之N型插栓81(N型雜質層)。具體而言，於N型埋入層51上形成有N型插栓81，於該N型插栓81之兩側形成有P型層91、92，於N型插栓81上形成有N型層121。而且，將賦予至N型層121之電位經由N型插栓81而供給至N型埋入層51。對於N型層121，供給例如接地電壓(廣義而言為低電位側電源電壓)。
於邊界區域32之第1區域10側，設置有用以對N型埋入層51供給電位之N型插栓82。N型插栓82之構成與N型插栓81相同。又，於邊界區域32之第2區域20側，設置有用以對P型基板41供給電位之P型埋入層101(PBL：P+ Buried Layer)。具體而言，於P型基板41上形成有P型埋入層101，於P型埋入層101上形成有P型井111，於P型井111上形成有P型層132。而且，將賦予至P型層132之電位經由P型井111與P型埋入層101而供給至P型基板41。對於P型層132，供給例如接地電壓(廣義而言為低電位側電源電壓)。
於第2區域20，形成有CMOS構造之N型電晶體(以下稱為NMOS)與P型電晶體(以下稱為PMOS)。具體而言，於P型基板41上形成有NMOS之P型井111(例如中耐壓P型井(MV PWELL))，於P型井111上形成有N型層125作為NMOS之N型源極區域，且形成有N型層126作為NMOS之N型汲極區域。於N型層125與N型層126之間之P型井111上形成有閘極層142。於P型井111上，進而形成有用以對P型井111供給電位之P型層133。對於P型層133，供給例如接地電壓(廣義而言為低電位側電源電壓)。
又，於P型基板41上形成有PMOS之N型井112(例如中耐壓N型井(MV NWELL))，於N型井112上形成有P型層135作為PMOS之P型源極 區域，且形成有P型層134作為PMOS之汲極區域。於P型層134與P型層135之間之N型井112上形成有閘極層143。於N型井112上，進而形成有用以對N型井112供給電位之N型層127。對於N型層127，供給例如電源電壓(高電位側電源電壓)。
再者，雖省略符號之圖示及說明，但於基板表層之雜質層(N型層、P型層)之間，設置有用以與相鄰之雜質層絕緣之絕緣層(LOCOS)。
且說，於包含DMOS電晶體之橋式電路藉由截斷電流而驅動馬達時，DMOS電晶體之汲極(N型層123)中流動有大電流。該大電流藉由截斷動作而導通/斷開(或流動之方向反轉)，故而汲極之電壓產生較大變動。該汲極之N型層123經由深N型井61而與N型埋入層51連接，而在N型埋入層51與P型基板41之間產生PN接面之寄生電容CP。因此，汲極之電壓變動經由寄生電容CP而傳遞至P型基板41，且經由P型基板41而傳遞至第2區域20。於第2區域20中，P型基板41與CMOS電晶體之P型井111或N型井112接觸，故而P型基板41之電壓變動會對包含CMOS電晶體之電路造成影響。
例如圖3之馬達驅動器中，電壓檢測電路220藉由將感測電阻290之一端側之電壓VS與基準電壓VR加以比較，而將流動於橋式電路210中之截斷電流保持為固定。此時，若電壓檢測電路220或基準電壓產生電路230受到P型基板41之電壓變動之影響，則基準電壓VR會產生變動，或電壓檢測電路220之比較精度會降低，故而截斷電流有可能產生偏差。
又，如圖5中下文所敍述般，於衰減期間，回充電流自接地電壓流向電源電壓VBB。因此，藉由感測電阻290之電壓降低而使DMOS電晶體Q3之汲極電壓低於接地電壓。藉此，於圖1之DMOS構造中，與汲極連接之N型埋入層51低於接地電壓，於與P型基板41之間產生 順向電壓，故而電流向P型基板41流入而使P型基板41之電壓擺動。如此，除介置寄生電容CP以外亦存在使P型基板41擺動之要因。
2.本實施形態之基板構成
圖2中，表示可解決如上所述之問題之本實施形態之基板構成例。圖2係構成電路裝置(例如圖3之電路裝置200)之積體電路裝置之基板之剖面圖。
於基板配置有：配置有第1電路之第1區域10；配置有第2電路之第2區域20；設置於第1區域10之一端部之邊界區域31；設置於第1區域10與第2區域20之間之邊界區域32；及設置於第2區域20之一端部之邊界區域33。再者，第1區域10及邊界區域31之構成與圖1相同，故而省略說明。
於第2區域20，形成有用以將CMOS電晶體與P型基板41隔離之N型埋入層52。具體而言，於P型基板41上形成有N型埋入層52，於該N型埋入層52上形成有P型埋入層102。而且，於該P型埋入層102上形成有NMOS電晶體及PMOS電晶體。該等電晶體之構成與圖1相同。
於邊界區域32之第1區域10側，與圖1同樣地設置有N型插栓82。於邊界區域32之第2區域20側，設置有用以對N型埋入層52供給電位之N型插栓83。具體而言，於N型埋入層51上形成有N型插栓83，於該N型插栓83之兩側形成有P型層95、96，於N型插栓83上形成有N型層128。而且，將賦予至N型層128之電位經由N型插栓83而供給至N型埋入層52。對於N型層128，供給例如電源電壓。
又，於邊界區域32，於N型插栓82與N型插栓83之間，設置有用以對P型基板41供給電位之P型埋入層101。P型埋入層101之構成與圖1相同，將賦予至P型層132之例如接地電壓經由P型井111與P型埋入層101而供給至P型基板41。
於邊界區域33，設置有用以對N型埋入層52供給電位之N型插栓 84。N型插栓84之構成與邊界區域32之N型插栓83相同，將賦予至N型層129之例如電源電壓經由N型插栓84而供給至N型埋入層52。
(以下為申請專利範圍支持之記載)
根據以上之實施形態，電路裝置200包含：第1電路(形成於第1區域10上之電路)，其形成於P型基板41上之第一N型埋入層51上，且包含DMOS構造之電晶體；及第2電路(形成於第2區域20上之電路)，其形成於與第一N型埋入層51分離之第二N型埋入層52上，且包含CMOS構造之電晶體。
如此一來，藉由與第一N型埋入層51分離之第二N型埋入層52，而可將包含CMOS構造之電晶體之第2電路與P型基板41隔離。如圖1之比較例中所說明，若DMOS構造之電晶體進行切換動作，則其汲極之電位之擺動會自第一N型埋入層51經由寄生電容CP等而傳遞至P型基板41。關於此點，根據本實施形態，由於第2電路與P型基板41隔離，故而即便於P型基板41之電位擺動之情形時，第2電路亦不易受到其影響，從而可進行誤差較少之動作。
此處，所謂埋入層係指形成於較基板表層之雜質層(例如圖2之P型體71或深N型井61)更靠下層之雜質層。具體而言，如圖9(A)~圖9(E)中下文所敍述般，對矽基板導入N型雜質或P型雜質，且使磊晶層(單晶矽層)成長於其上，藉此於磊晶層下形成埋入層。
又，於本實施形態中，第2電路之區域(第2區域20)係由設定第二N型埋入層52之電位之N型插栓區域(於俯視時設置有N型插栓83、84之區域)包圍。
如此一來，藉由第二N型埋入層52與包圍其之N型插栓區域而可形成浴缸形之N型區域，且藉由該N型區域而可將第2電路之區域與P型基板41隔離。又，即便P型基板之電位之擺動傳遞至第二N型埋入層52，亦因由N型插栓設定電位而可確實地隔離第2電路區域。又， 可將第二N型埋入層52設定為較P型基板41高之電位(例如電源電壓)，故而可藉由反向電壓之PN接面而隔離。
此處，所謂電路之區域係指對基板進行俯視時配置有電路之區域。即，於電路佈局中，在檢測電路250係由一個或複數個電路區塊構成之情形時為配置有該佈局區塊之區域。例如於第2電路為圖3之檢測電路250之情形時，該檢測電路250之配置區域成為第2電路之區域。
再者，所謂由N型插栓區域「包圍」，並不限於俯視時N型插栓區域完全包圍第2電路之區域(第2區域20)周圍之情形，亦包含例如於N型插栓區域之一部分存在缺損(例如斷續地包圍般)之情形。例如圖2所示，邊界區域32包含N型插栓83。於圖3之電路裝置200中，該邊界區域32例如係以包圍橋式電路210之周圍之方式設置。或者，以使至少橋式電路210與除其以外之電路(檢測電路250)分離之方式設置。於該情形時，邊界區域32無需於俯視時為連貫之區域，亦可一部分斷開。
又，於本實施形態中，CMOS構造之電晶體係在形成於第二N型埋入層52上之P型層上形成。例如P型層為P型埋入層102。
如此一來，可形成藉由第二N型埋入層52而與P型基板41隔離之P型層(P型埋入層102)。藉此，可將該P型層(P型埋入層102)作為新的P型基板，而構成與原來之P型基板41隔離之第2電路。
又，於本實施形態中，電路裝置包含：供給P型基板41之電位之墊(例如，與下述之圖3之端子TVB連接之墊)；用以自該墊對P型層(P型埋入層102)供給電位之第1配線(例如形成於半導體基板上之鋁配線)；及用以自該墊對P型基板41供給電位之第2配線。
如此一來，可對與P型基板41隔離之P型層(P型埋入層102)，利用與P型基板41不同之路徑(第1配線、P型層133、P型井111)而供給電 位。藉此，可抑制電位變動經由配線而自P型基板41向P型層(P型埋入層102)傳遞。
此處，所謂墊係形成於半導體基板上之接合墊。即，係藉由例如接合線等而與封裝之端子連接之晶片(積體電路裝置)側之端子，且係於晶片內部之電路與外部之電路之間用以進行信號或電壓之輸入輸出之端子。
3.馬達驅動器
圖3中，表示馬達驅動器之構成例作為可應用上述基板構成之電路裝置之構成例。電路裝置200包含橋式電路210、檢測電路250。而且，檢測電路250包含：電壓檢測電路220、基準電壓產生電路230、控制電路240。再者，以下，以電路裝置整體由一個積體電路裝置構成之情形為例進行說明，但本實施形態並不限定於此。即，亦可為，電路裝置之一部分(例如橋式電路210、電壓檢測電路220)由一個積體電路裝置構成，且於該積體電路裝置中應用圖2之基板構成。
橋式電路210根據來自控制電路240之PWM信號而驅動外部安裝之馬達280(直流馬達)。具體而言，橋式電路210包含構成為H橋之電晶體Q1~Q4(DMOS電晶體)。例如可使電晶體Q1~Q4為N型，或者亦可使電晶體Q1、Q2為P型，且電晶體Q3、Q4為N型。
電晶體Q1係設置於被供給電源電壓VBB之端子TVB、與連接有馬達280之一端之端子OUT1之間。電晶體Q2係設置於端子TVB、與連接有馬達280之另一端之端子OUT2之間。電晶體Q3係設置於端子OUT1、與和一端被供給接地電壓之感測電阻290之另一端連接之端子RNF之間。電晶體Q4係連接於端子OUT2與端子RNF之間。
基準電壓產生電路230包含例如電壓分割電路，產生用以檢測截斷電流之基準電壓VR。
電壓檢測電路220包含例如比較器，進行流動於橋式電路210中 之截斷電流之檢測。具體而言，電壓檢測電路220比較經由端子RNFS而輸入之感測電阻290之一端之電壓VS與基準電壓VR。然後，若檢測出電壓VS已達到基準電壓VR，則將該檢測信號輸出至控制電路240。
控制電路240控制橋式電路210之截斷動作。具體而言，控制電路240根據來自電壓檢測電路220之檢測信號，以使截斷電流成為固定之方式而控制PWM信號之脈衝寬度。然後，由該PWM信號產生電晶體Q1~Q4之導通/斷開控制信號，且將所產生之導通/斷開控制信號輸出至電晶體Q1~Q4之閘極。
使用圖4~圖6對電路裝置200之動作詳細地進行說明。再者，圖4所示之比較器221係與電壓檢測電路220對應。對比較器221之正極輸入端子輸入感測電阻290之另一端之電壓VS，對負極輸入端子輸入基準電壓VR。將比較器221之輸出信號輸出至控制電路240。
如圖6所示，於時間t0開始馬達280之驅動。一旦開始驅動，則如圖4所示成為充電期間，控制電路240使電晶體Q1、Q4導通，使電晶體Q2、Q3斷開。於充電期間，如圖4之實線箭頭所示，驅動電流自電源電壓VBB經由電晶體Q1、馬達280、電晶體Q4、及感測電阻290而流向接地電壓。
驅動電流隨時間之經過而變大，藉由感測電阻290而轉換後之電壓VS亦上升。若電壓VS變得大於基準電壓VR，則比較器221之輸出信號自L位準變化為H位準。如圖6所示，此時(時間t1)之驅動電流為截斷電流Ich，藉由電壓VS之檢測而檢測出截斷電流Ich。
控制電路240接收到比較器221之輸出信號已成為H位準，而進行至衰減期間TD1。如圖5所示，於衰減期間TD1，控制電路240使電晶體Q2、Q3導通，使電晶體Q1、Q4斷開。如圖5之虛線箭頭所示，驅動電流(回充電流)自接地電壓經由感測電阻290、電晶體Q3、馬達280、及電晶體Q2而流向電源電壓VBB。如圖6所示，於衰減期間 TD1，驅動電流隨時間之經過而降低。
控制電路240使用例如計時器(計數器電路)等，檢測出自衰減期間TD1之開始起已經過特定時間，而進行至充電期間TC1。於充電期間TC1，驅動電流上升，若達到截斷電流Ich，則再次進行至衰減期間TD2。以下，藉由反覆地進行該操作，而以使截斷電流Ich成為固定之方式進行控制，將馬達280之旋轉速度保持為固定。
再者，以上所述係以橋式電路210由H橋構成之情形為例進行了說明，但本實施形態並不限定於此，橋式電路210亦可由半橋構成。
4.DMOS電晶體
圖7中，表示DMOS構造之N型電晶體之詳細之構成例。圖7係基板之厚度方向上之剖面圖。再者，對於與圖2中說明之構成要素相同之構成要素標註相同之符號，適當省略說明。
該構成例係將圖2中說明之DMOS構造之N型電晶體左右對稱地構成者。即，以與源極區域對應之N型層122為中心，於其兩側形成有閘極層141a、141b、絕緣層151a、151b、及與汲極區域對應之N型層123a、123b。關於深N型井61與P型體71亦同樣地，以源極為中心而左右對稱地形成於N型埋入層51上。於深N型井61之兩側，形成有N型插栓81、82。
圖8中，表示DMOS構造之P型電晶體之詳細之構成例。圖8係基板之厚度方向上之剖面圖。
於該構成例中，以與汲極區域對應之P型層136為中心而左右對稱地構成各層。具體而言，於P型基板41上形成有N型埋入層53，於N型埋入層53上形成有深N型井62。於深N型井62之中央部上形成有HPOF161(P型雜質層)，於HPOF161上形成有與汲極區域對應之P型層136。於深N型井62之兩端部上形成有N型井113a、113b(例如低耐壓N型井(LV NWEL))，於N型井113a、113b上形成有N型層171a、171b及 與源極區域對應之P型層137a、137b。在與汲極區域對應之P型層136之兩側形成有絕緣層152a、152b(例如LOCOS)，於N型井113a、113b、HPOF161、絕緣層152a、152b上形成有閘極層144a、144b(例如多晶矽層)。
對於N型埋入層53，經由N型插栓85a、85b而供給電位(例如電源電壓)。N型插栓85a、85b係形成於深N型井62之兩側，且於N型插栓85a、85b上形成有N型層172a、172b。
再者，與N通道同樣地，亦可以左右對稱之構成中之一側之閘極及汲極而構成DMOS構造之P型電晶體。
5.製造製程
使用圖9(A)~圖12(C)，對DMOS構造之電晶體之製造製程流程進行說明。再者，於圖式左側表示N型電晶體，於圖式右側表示P型電晶體。
如圖9(A)所示，進行於P型基板(Psub)形成氧化膜(SiO2)之步驟。其次如圖9(B)所示，進行光微影步驟，進行對未被抗蝕劑覆蓋之區域之氧化膜(SiO2)進行蝕刻之步驟。其次如圖9(C)所示，藉由對P型基板(Psub)導入N型離子之步驟，而於未被氧化膜(SiO2)覆蓋之區域形成N型埋入層(NBL)。
其次如圖9(D)所示，藉由蝕刻步驟而去除氧化膜(SiO2)，並進行光微影步驟。其次，藉由對P型基板(Psub)導入P型離子之步驟，而於未被抗蝕劑覆蓋之區域形成P型埋入層(PBL)。其次如圖9(E)所示，進行於P型基板(Psub)及埋入層(NBL、PBL)上形成P型磊晶層(P-Epi)之步驟。以上述方式，於P型磊晶層(P-Epi)下形成有N型埋入層(NBL)及P型埋入層(PBL)。
其次如圖10(A)所示，藉由光微影步驟及對P型磊晶層(P-Epi)導入N型離子之步驟，而於未被抗蝕劑覆蓋之區域形成深N型井(Deep NWEL)。其次如圖10(B)所示，藉由光微影步驟及對P型磊晶層(P-Epi)導入N型離子之步驟，而於未被抗蝕劑覆蓋之區域形成N型插栓(Nplug)。
其次如圖10(C)所示，進行氮化矽膜之光微影步驟及蝕刻步驟，進行氧化膜形成步驟，藉此形成LOCOS(SiO2)。其次如圖10(D)所示，藉由光微影步驟及對深N型井(Deep NWEL)導入P型離子之步驟，而於未被抗蝕劑覆蓋之區域形成P型體(Pbody)。
其次如圖11(A)所示，藉由光微影步驟及對深N型井(Deep NWEL)導入P型離子之步驟，而於未被抗蝕劑覆蓋之區域形成HPOF層。其次如圖11(B)所示，藉由光微影步驟及對深N型井(Deep NWEL)導入N型離子之步驟，而於未被抗蝕劑覆蓋之區域形成低耐壓N型井(LV NWEL)。其次如圖11(C)所示，藉由光微影步驟及對P型磊晶層(P-Epi)導入P型離子之步驟，而於未被抗蝕劑覆蓋之區域形成低耐壓P型井(LV PWEL)。
其次如圖12(A)所示，進行形成多晶矽層之步驟，進行光微影步驟及蝕刻步驟，藉此形成閘極層(Poly)。其次如圖12(B)所示，藉由光微影步驟及導入N型離子之步驟，而於基板表層形成N型雜質層(N+)。該N型雜質層(N+)成為N型電晶體之源極區域或汲極區域等。其次如圖12(C)所示，藉由光微影步驟及導入P型離子之步驟，而於基板表層形成P型雜質層(P+)。該P型雜質層(P+)成為P型電晶體之源極區域或汲極區域等。以上述方式，形成DMOS構造之N型電晶體(紙面左側)及DMOS構造之P型電晶體(紙面右側)。
再者，關於CMOS構造之電晶體之製造製程雖省略說明，但關於與DMOS構造之電晶體共用之層，使步驟通用化，於一個製造流程中形成CMOS構造及DMOS構造混合存在之半導體基板即可。
6.電子機器
圖13中，表示應用有本實施形態之電路裝置200(馬達驅動器)之電子機器之構成例。電子機器包含：處理部300、記憶部310、操作部320、輸入輸出部330、電路裝置200、連接該等各部之匯流排340、及馬達280。以下，採用藉由馬達驅動而控制列印頭或進紙之印表機為例進行說明，但本實施形態並不限定於此，其可應用於各種電子機器。
輸入輸出部330係由例如USB(Universal Serial Bus，通用串列匯流排)連接器或無線LAN(Local Area Network，區域網路)等之介面構成，且被輸入圖像資料或文字資料。將所輸入之資料記憶於例如DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)等之作為內部記憶裝置之記憶部310。若藉由操作部320而受理印刷指示，則處理部300開始處理記憶於記憶部310中之資料之印刷動作。處理部300對照資料之印刷佈局而對電路裝置200(馬達驅動器)發送指示，電路裝置200根據該指示而使馬達280旋轉，進行列印頭之移動或進紙。
於本實施形態中，電路裝置200可將截斷電流高精度地保持為固定，故而可抑制列印頭之移動或進紙之誤差，從而可實現高品質之印刷。
再者，如上所述，詳細地對本實施形態進行了說明，但業者應當能夠容易地理解可進行實質上不脫離本發明之新穎事項及效果之多種變化。因此，如此之變化例係均為本發明之範圍中所包含者。例如，於說明書或圖式中，至少一次與更廣義或同義之不同之術語共同記載之術語可於說明書或圖式之任一處中，替換為該不同之術語。又，本實施形態及變化例之所有之組合亦包含於本發明之範圍。又，電路裝置、基板、電子機器之構成、動作或馬達驅動之控制方法、半導體基板之製造方法等亦並不限定於本實施形態中所說明者，而可進行各種變化實施。
10‧‧‧第1區域
20‧‧‧第2區域
31~33‧‧‧邊界區域
41‧‧‧P型基板
51、52‧‧‧N型埋入層
61‧‧‧深N型井
71‧‧‧P型體
81~84‧‧‧N型插栓
91~98‧‧‧P型層
101、102‧‧‧P型埋入層
111‧‧‧P型井
112‧‧‧N型井
121~129‧‧‧N型層
131~135‧‧‧P型層
141~143‧‧‧閘極層
151‧‧‧絕緣層
CP‧‧‧寄生電容
Deep NWEL‧‧‧深N型井
NBL‧‧‧N型埋入層
Nplug‧‧‧N型插栓
NWEL‧‧‧N型井
PBL‧‧‧P型埋入層
Pbody‧‧‧P型體
Psub‧‧‧P型基板
PWEL‧‧‧P型井

Claims (13)

  1. 一種電路裝置，其特徵在於包含：第1電路，其包括形成於P型基板上之第一N型埋入層上之DMOS構造之電晶體；及第2電路，其包括形成於與上述第一N型埋入層分離之第二N型埋入層上之CMOS構造之電晶體。
  2. 如請求項1之電路裝置，其中上述第2電路之區域係由設定上述第二N型埋入層之電位之N型插栓區域包圍。
  3. 如請求項1或2之電路裝置，其中上述CMOS構造之電晶體係在形成於上述第二N型埋入層上之P型層上形成。
  4. 如請求項3之電路裝置，其中上述P型層係P型埋入層。
  5. 如請求項3或4之電路裝置，其包含：墊，其供給上述P型基板之電位；第1配線，其用以自上述墊對上述P型層供給電位；及第2配線，其用以自上述墊對上述P型基板供給電位。
  6. 如請求項3至5中任一項之電路裝置，其中上述CMOS構造之電晶體之P型電晶體包含：形成於上述P型層上之N型井、形成於上述N型井上之P型源極區域、及形成於上述N型井上之P型汲極區域，且上述CMOS構造之電晶體之N型電晶體包含：形成於上述P型層上之P型井、形成於上述P型井上之N型源極區域、及形成於上述P型井上之N型汲極區域。
  7. 如請求項1至6中任一項之電路裝置，其中上述DMOS構造之電晶體之N型電晶體包含：形成於上述第一N型埋入層上之深N型井、 形成於上述深N型井上之P型層、形成於上述P型層上之N型源極區域、及形成於上述深N型井上之N型汲極區域。
  8. 如請求項1至7中任一項之電路裝置，其中上述DMOS構造之電晶體之P型電晶體包含：形成於上述第一N型埋入層上之深N型井、形成於上述深N型井上之P型層、形成於上述深N型井上之P型源極區域、及形成於上述P型層上之P型汲極區域。
  9. 如請求項1至8中任一項之電路裝置，其中上述第1電路包含：輸出用以驅動馬達之截斷電流之橋式電路，上述第2電路包含：檢測流動於上述橋式電路中之電流之檢測電路。
  10. 如請求項9之電路裝置，其中上述檢測電路包含：基準電壓產生電路，其產生基準電壓；電壓檢測電路，其比較基於上述電流之電壓與上述基準電壓；及控制電路，其根據上述電壓檢測電路之比較結果而控制上述橋式電路。
  11. 如請求項1至8中任一項之電路裝置，其中上述第2電路包含：控制上述第1電路之電路、或檢測上述第1電路之電壓或電流之電路。
  12. 如請求項1至8中任一項之電路裝置，其中上述第1電路係進行反覆地切換輸出電流或輸出電壓之動作之電路。
  13. 一種電子機器，其特徵在於包含如請求項1至12中任一項之電路裝置。
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