US20140247001A1 - Circuit device and electronic apparatus - Google Patents

Circuit device and electronic apparatus Download PDF

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Publication number
US20140247001A1
US20140247001A1 US14/191,893 US201414191893A US2014247001A1 US 20140247001 A1 US20140247001 A1 US 20140247001A1 US 201414191893 A US201414191893 A US 201414191893A US 2014247001 A1 US2014247001 A1 US 2014247001A1
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Prior art keywords
type
circuit
layer
transistor
substrate
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Isamu Moriya
Atsushi Yamada
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Seiko Epson Corp
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Seiko Epson Corp
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Assigned to SEIKO EPSON CORPORATION reassignment SEIKO EPSON CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MORIYA, ISAMU, YAMADA, ATSUSHI
Publication of US20140247001A1 publication Critical patent/US20140247001A1/en
Priority to US16/361,846 priority Critical patent/US11037927B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H02P6/001—
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
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    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
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    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
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    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
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    • H03K2217/0045—Full bridges, determining the direction of the current through the load

Definitions

  • the present invention relates to a circuit device and an electronic apparatus or the like.
  • a technique of controlling the number of revolutions of a motor by controlling a chopping current is known as a technique for a motor driver that drives a DC motor.
  • a current flowing to a bridge circuit is converted to a voltage by a sense resistor, and the resultant voltage is compared with a reference voltage, to detect a chopping current.
  • the detection result is fed back to a control circuit, to perform PWM control of a drive signal for the bridge circuit, thereby rotating a motor at a fixed rate.
  • JP-A-2008-042975 discloses a technique of improving the precision of detection of the chopping current in such a motor driver.
  • a sense resistor is provided for each half bridge of an H-bridge, where one resistor detects that the current in the charge period has reached a predetermined current, and the other resistor detects that the current in the decay period has reached a predetermined current.
  • a large current is required to drive the motor, and on/off of the current is repeated by chopping operation. Therefore, the potential of the substrate of the motor driver fluctuates.
  • a reference voltage generation circuit and a voltage detection circuit formed on the substrate are affected by the potential fluctuation, causing variations in the detection value of the chopping current. This then results in a decrease in the precision of the rotational speed of the motor that is controlled so as to be constant.
  • An advantage of some aspects of the invention is providing a circuit device and an electronic apparatus or the like where the effect of the potential fluctuation of a substrate on the operation of a circuit can be reduced.
  • a first aspect of the invention relates to a circuit device including a first circuit constituted by a transistor that has a DMOS structure and is formed on a first N-type buried layer on a P-type substrate, and a second circuit constituted by a transistor that has a CMOS structure and is formed on a second N-type buried layer isolated from the first N-type buried layer.
  • the second circuit constituted by the CMOS transistor is formed on the second N-type buried layer isolated from the first N-type buried layer, so that the second circuit is isolated from the P-type substrate by the second N-type buried layer.
  • the effect of the potential fluctuation of the substrate on the circuit operation can be reduced.
  • a region of the second circuit be surrounded by an N-type plug region that sets a potential of the second N-type buried layer.
  • the second circuit can be isolated from the P-type substrate by the second N-type buried layer and the N-type plug region surrounding the second N-type buried layer. Also, since the potential of the N-type buried layer is set by the N-type plug region, the second circuit can be electrically isolated from the P-type substrate.
  • the transistor having the CMOS structure be formed on a P-type layer that is formed on the second N-type buried layer.
  • the P-type layer that is isolated from the P-type substrate by the second N-type buried layer can be formed, and the second circuit constituted by the CMOS transistor can be formed on the isolated P-type layer.
  • the P-type layer be an epitaxial layer.
  • a P-type buried layer can be formed as the P-type layer isolated from the P-type substrate by farming an epitaxial layer on the second N-type buried layer.
  • the circuit device further include a pad through which a potential of the P-type substrate is supplied, a first interconnect for supplying a potential from the pad to the P-type layer, and a second interconnect for supplying a potential from the pad to the P-type substrate.
  • a P-type transistor of the transistor having the CMOS structure be constituted by an N-type well formed on the P-type layer, a P-type source region formed on the N-type well, and a P-type drain region formed on the N-type well
  • an N-type transistor of the transistor having the CMOS structure be constituted by a P-type well formed on the P-type layer, an N-type source region formed on the P-type well, and an N-type drain region formed on the P-type well.
  • the second circuit constituted by the N-type transistor of the CMOS structure and the P-type transistor of the CMOS structure can be formed on the second N-type buried layer isolated from the first N-type buried layer.
  • an N-type transistor of the transistor having the CMOS structure have a deep N-type well formed on the first N-type buried layer, a P-type layer formed on the deep N-type well, an N-type source region formed on the P-type layer, and an N-type drain region formed on the deep N-type well.
  • a P-type transistor of the transistor having the DMOS structure have a deep N-type well formed on the first N-type buried layer, a P-type layer formed on the deep N-type well, a P-type source region formed on the deep N-type well, and a P-type drain region formed on the P-type layer.
  • the first circuit constituted by the N-type transistor of the DMOS structure or the P-type transistor of the DMOS structure can be formed on the first N-type buried layer.
  • the first circuit have a bridge circuit that outputs a chopping current for driving a motor
  • the second circuit have a detection circuit that detects a current flowing to the bridge circuit
  • a motor drive circuit that drives the motor with the chopping current can be formed of the bridge circuit and the detection circuit. Even though the switching operation of the bridge circuit causes the potential of the P-type substrate to fluctuate, detection errors of the chopping current can be reduced because the detection circuit can be isolated by the second N-type buried layer.
  • the detection circuit have a reference voltage generation circuit that generates a reference voltage, a voltage detection circuit that compares a voltage based on the current with the reference voltage, and a control circuit that controls the bridge circuit based on a comparison result of the voltage detection circuit.
  • the chopping current flowing to the motor can be controlled so as to be constant by comparing the voltage based on the chopping current with the reference voltage.
  • the second circuit have a circuit that controls the first circuit or a circuit that detects a voltage or a current of the first circuit.
  • the circuit that controls the first circuit or the circuit that detects the voltage or current of the first circuit can be isolated from the P-type substrate.
  • the first circuit can be controlled precisely, or the voltage or current of the first circuit can be detected precisely.
  • the first circuit be a circuit that performs an operation of repeatedly switching an output current or an output voltage.
  • a second aspect of the invention relates to an electronic apparatus including the circuit device described above.
  • FIG. 1 shows the configuration of a substrate of a comparative example of an embodiment of the invention.
  • FIG. 2 shows an example configuration of a substrate according to the embodiment.
  • FIG. 3 shows an example configuration of a circuit device.
  • FIG. 4 is an explanatory diagram of the operation of the circuit device.
  • FIG. 5 is an explanatory diagram of the operation of the circuit device.
  • FIG. 6 is an explanatory diagram of the operation of the circuit device.
  • FIG. 7 shows a detailed example configuration of an N-type transistor having a DMOS structure.
  • FIG. 8 shows a detailed example configuration of a P-type transistor having a DMOS structure.
  • FIGS. 9A to 9E show a process flow for manufacturing a transistor having a DMOS structure.
  • FIGS. 10A to 10D show a process flow for manufacturing the transistor having the DMOS structure.
  • FIGS. 11A to 11C show a process flow for manufacturing the transistor having the DMOS structure.
  • FIGS. 12A to 12C show a process flow for manufacturing the transistor having the DMOS structure.
  • FIG. 13 shows an example configuration of an electronic apparatus.
  • FIG. 1 shows the configuration of a substrate of a comparative example of this embodiment.
  • FIG. 1 is a cross-sectional view of a substrate of an integrated circuit device constituting a circuit device.
  • this embodiment is not limited to this, but can be applied to various types of circuit devices that perform switching operation of a drive current or a drive voltage.
  • this embodiment may also be applied to a switching regulator or the like that generates a desired voltage by driving an LC resonant circuit by switching a transistor.
  • the first circuit is a bridge circuit (e.g., a bridge circuit 210 in FIG. 3 ) constituted by a double-diffused metal oxide semiconductor (DMOS) transistor. Note that the first circuit is not limited to a bridge circuit, but any circuit that performs the switching operation of a drive current can be used.
  • the second circuit is a circuit (e.g., a detection circuit 250 in FIG. 3 ) constituted by a complementary metal oxide semiconductor (CMOS) transistor.
  • CMOS complementary metal oxide semiconductor
  • a direction (thickness direction) perpendicular to the plane of the substrate and toward a side of the substrate on which a circuit is to be formed is referred to as “upward”, and the reverse direction is referred to as “downward”.
  • an N-type transistor having a DMOS structure (hereinafter referred to as an N-type DMOS) is formed. More specifically, an N-type (N+) buried layer (NBL) 51 is formed on a P-type substrate 41 that is a silicon substrate, and a deep N-type well 61 of the N-type DMOS is formed on the N-type buried layer 51 .
  • a P-type body 71 (P-type impurity layer) is formed on the source side of the deep N-type well 61 , and a P-type layer 131 (P-type impurity layer) and an N-type layer 122 (N-type impurity layer) are formed on the P-type body 71 .
  • the N-type layer 122 corresponds to the source region of the N-type DMOS.
  • An N-type layer 123 corresponding to the drain region of the N-type DMOS is formed on the drain side of the deep N-type well 61 .
  • An insulating layer 151 e.g., LOCOS
  • a gate layer 141 e.g., a polysilicon layer
  • an N-type plug 81 (N-type impurity layer) for supplying a potential to the N-type buried layer 51 is provided. More specifically, the N-type plug 81 is formed on the N-type buried layer 51 , P-type layers 91 and 92 are formed on both sides of the N-type plug 81 , and an N-type layer 121 is formed on the N-type plug 81 . The potential given to the N-type layer 121 is thus supplied to the N-type buried layer 51 via the N-type plug 81 . A ground voltage (low-potential side power supply voltage in a broad sense) is supplied to the N-type layer 121 .
  • an N-type plug 82 for supplying a potential to the N-type buried layer 51 is provided.
  • the configuration of the N-type plug 82 is similar to that of the N-type plug 81 .
  • a P-type (P+) buried layer (PBL) 101 for supplying a potential to the P-type substrate 41 is provided. More specifically, the P-type buried layer 101 is formed on the P-type substrate 41 , a P-type well 111 is formed on the P-type buried layer 101 , and a P-type layer 132 is formed on the P-type well 111 .
  • the potential given to the P-type layer 132 is supplied to the P-type substrate 41 via the P-type well 111 and the P-type buried layer 101 .
  • the ground voltage (low-potential side power supply voltage in a broad sense), for example, is supplied to the P-type layer 132 .
  • an N-type transistor hereinafter referred to as an NMOS
  • a P-type transistor hereinafter referred to as a PMOS
  • the P-type well 111 e.g., a medium-voltage P-type well (MV PWELL)
  • MV PWELL medium-voltage P-type well
  • a gate layer 142 is formed above the P-type well 111 between the N-type layers 125 and 126 .
  • a P-type layer 133 for supplying a potential to the P-type well 111 is further formed on the P-type well 111 .
  • the ground voltage (low-potential side power supply voltage in a broad sense), for example, is supplied to the P-type layer 133 .
  • An N-type well 112 (e.g., a medium-voltage N-type well (MV NWELL)) of the PMOS is formed on the P-type substrate 41 , and a P-type layer 135 and a P-type layer 134 are formed on the N-type well 112 as the P-type source region and the drain region, respectively, of the PMOS.
  • a gate layer 143 is formed above the N-type well 112 between the P-type layers 134 and 135 .
  • An N-type layer 127 for supplying a potential to the N-type well 112 is further formed on the N-type well 212 .
  • a power supply voltage (high-potential side power supply voltage), for example, is supplied to the N-type layer 127 .
  • insulating layers for insulation from an adjacent impurity layer are provided between the impurity layers (the N-type layers and the P-type layers) in a surface portion of the substrate, although reference numerals thereof in the drawings and a description thereof are omitted.
  • the bridge circuit constituted by the DMOS transistors drives the motor with a chopping current
  • a large current flows to the drain (N-type layer 123 ) of the DMOS transistor. Since the large current is turned on/off (or the direction of the flow is reversed) by the chopping operation, the voltage of the drain largely fluctuates.
  • the N-type layer 223 as the drain is connected to the N-type buried layer 51 via the deep N-type well 61 , and a parasitic capacitance CP is present between the N-type buried layer 51 and the P-type substrate 41 due to their PN junction.
  • the voltage fluctuation at the drain is conveyed to the P-type substrate 41 via the parasitic capacitance CP, and then to the second region 20 via the P-type substrate 41 .
  • the voltage fluctuation of the P-type substrate 41 affects the circuit constituted by the CMOS transistor.
  • a voltage detection circuit 220 compares a voltage VS at one terminal of a sense resistor 290 with a reference voltage VR, thereby keeping the chopping current flowing to the bridge circuit 210 constant. At this time, if the voltage detection circuit 220 and a reference voltage generation circuit 230 are affected by the voltage fluctuation of the P-type substrate 41 , the reference voltage VR will fluctuate and the comparison precision of the voltage detection circuit 220 will decrease, raising the possibility of occurrence of variations in the chopping current.
  • a regenerative current flows from the ground voltage toward a power supply voltage VBB during the decay period. For this reason, the drain voltage of a DMOS transistor Q 3 becomes lower than the ground voltage due to a voltage drop of the sense resistor 290 .
  • the N-type buried layer 51 connected to the drain becomes lower than the ground voltage, causing a forward voltage between the N-type buried layer 51 and the P-type substrate 41 .
  • the voltage of the P-type substrate 41 will therefore be swung with the current flowing into the P-type substrate 41 .
  • there is another cause of swinging of the voltage of the P-type substrate 41 in addition to the one occurring via the parasitic capacitance CP.
  • FIG. 2 shows an example configuration of a substrate according to this embodiment that can solve the problems as described above.
  • FIG. 2 is a cross-sectional view of a substrate of an integrated circuit device constituting a circuit device (e.g., a circuit device 200 in FIG. 3 ).
  • first region 10 where a first circuit is placed
  • second region 20 where a second circuit is placed
  • boundary region 31 provided at one end of the first region 10
  • boundary region 32 provided between the first region 10 and the second region 20
  • boundary region 33 provided at one end of the second region 20 . Since the configurations of the first region 10 and the boundary region 31 are similar to those in FIG. 1 , a description of these regions is omitted here.
  • an N-type buried layer 52 for isolating the CMOS transistor from the P-type substrate 41 is formed. More specifically, the N-type buried layer 52 is formed on the P-type substrate 41 , and a P-type buried layer 102 is formed on the N-type buried layer 52 . An NMOS transistor and a PMOS transistor are formed on the P-type buried layer 102 . The configurations of these transistors are similar to those in FIG. 1 .
  • an N-type plug 82 is provided as in FIG. 1 .
  • an N-type plug 83 for supplying a potential to the N-type buried layer 52 is provided. More specifically, the N-type plug 83 is formed on the N-type buried layer 52 , P-type layers 95 and 96 are formed on both sides of the N-type plug 83 , and an N-type layer 128 is formed on the N-type plug 83 . The potential given to the N-type layer 128 is thus supplied to the N-type buried layer 52 via the N-type plug 83 .
  • the power supply voltage for example, is supplied to the N-type layer 128 .
  • a P-type buried layer 101 for supplying a potential to the P-type substrate 41 is provided between the N-type plug 82 and the N-type plug 83 .
  • the configuration of the P-type buried layer 101 is similar to that in FIG. 1 , where the ground voltage, for example, given to a P-type layer 132 is supplied to the P-type substrate 41 via a P-type well 111 and the P-type buried layer 101 .
  • an N-type plug 84 for supplying a potential to the N-type buried layer 52 is provided in the boundary region 33 .
  • the configuration of the N-type plug 84 is similar to that of the N-type plug 83 in the boundary region 32 , where the power supply voltage, for example, given to an N-type layer 129 is supplied to the N-type buried layer 52 via the N-type plug 84 .
  • the circuit device 200 includes the first circuit (circuit that is formed in the first region 10 ) constituted by the transistor that has the DMOS structure and is formed on the first N-type buried layer 51 on the P-type substrate 41 and the second circuit (circuit that is formed in the second region 20 ) constituted by the transistor that has the CMOS structure and is formed on the second N-type buried layer 52 isolated from the first N-type buried layer 51 .
  • the second circuit constituted by the CMOS transistor can be isolated from the P-type substrate 41 .
  • the swing of the drain potential is conveyed from the first N-type buried layer 51 to the P-type substrate 41 via the parasitic capacitance CP, etc., as described in the comparative example shown in FIG. 1 .
  • the second circuit is isolated from the P-type substrate 41 , even when the potential of the P-type substrate 41 swings, the second circuit is less likely to be affected by this swing, permitting operation with reduced errors.
  • the buried layer as used herein refers to an impurity layer formed below the impurity layers (e.g., the P-type body 71 and the deep N-type well 61 in FIG. 2 ) in the surface portion of the substrate. More specifically, as described later with reference to FIGS. 9A to 9E , an N-type impurity or a P-type impurity is implanted in the silicon substrate, and an epitaxial layer (silicon single-crystal layer) is grown on the impurity-implanted layer, to form a buried layer under the epitaxial layer.
  • an impurity layer formed below the impurity layers (e.g., the P-type body 71 and the deep N-type well 61 in FIG. 2 ) in the surface portion of the substrate. More specifically, as described later with reference to FIGS. 9A to 9E , an N-type impurity or a P-type impurity is implanted in the silicon substrate, and an epitaxial layer (silicon single-crystal
  • the region of the second circuit (second region 20 ) is surrounded by an N-type plug region (region where the N-type plugs 83 and 84 are provided as viewed from top) that sets the potential of the second N-type buried layer 52 .
  • a bathtub-shaped N-type region can be formed by the second N-type buried layer 52 and the N-type plug region surrounding the buried layer 52 .
  • the region of the second circuit can be isolated from the P-type substrate 41 .
  • the second circuit region can be isolated without fail because the potential of the buried layer 52 has been set via the N-type plugs.
  • the second N-type buried layer 52 can be set to a potential (e.g., a power supply voltage) higher than the P-type substrate 41 , isolation can be ensured by reverse-voltage PN junction.
  • the region of a circuit as used herein refers to a region in which the circuit is placed when the substrate is viewed from top. That is to say, in a circuit layout, if the detection circuit 250 is constituted by one or more circuit blocks, the region of the detection circuit 250 refers to the region in which the layout block(s) is placed. For example, if the second circuit is the detection circuit 250 in FIG. 3 , the region in which the detection circuit 250 is placed constitutes the region of the second circuit.
  • the boundary region 32 includes the N-type plug 83 .
  • the boundary region 32 may be provided so as to surround the periphery of the bridge circuit 210 , for example.
  • the boundary region 32 may be provided so as to isolate at least the bridge circuit 210 from the other circuits (detection circuit 250 ).
  • the boundary region 32 is not necessarily required to be a continuous region when viewed from top, but may be partly discontinuous.
  • the transistor having the CMOS structure is formed on a P-type layer that is formed on the second N-type buried layer 52 .
  • the P-type layer may be the P-type buried layer 102 .
  • the P-type layer (P-type buried layer 102 ) that is isolated from the P-type substrate 41 by the second N-type buried layer 52 can be formed.
  • the second circuit that is isolated from the primary P-type substrate 41 can be formed using that P-type layer (P-type buried layer 102 ) as a new P-type substrate.
  • the circuit device includes a pad (e.g., a pad connected to a terminal TVB in FIG. 3 described later) for supplying a potential of the P-type substrate 41 , a first interconnect (e.g., aluminum interconnect formed on the semiconductor substrate) for supplying a potential from the pad to the P-type layer (P-type buried layer 102 ), and a second interconnect for supplying a potential from the pad to the P-type substrate 41 .
  • a pad e.g., a pad connected to a terminal TVB in FIG. 3 described later
  • a first interconnect e.g., aluminum interconnect formed on the semiconductor substrate
  • P-type layer P-type buried layer 102
  • second interconnect for supplying a potential from the pad to the P-type substrate 41 .
  • the potential can be supplied to the P-type layer (P-type buried layer 102 ), which is isolated from the P-type substrate 41 , via a different route (the first interconnect, the P-type layer 133 , and the P-type well 111 ) than that to the P-type substrate 41 .
  • conveyance of the potential fluctuation from the P-type substrate 41 to the P-type layer (P-type buried layer 102 ) via the interconnect can be prevented or reduced.
  • the pad as used herein refers to a bonding pad formed on a semiconductor substrate. That is, the pad refers to a terminal that is included in the chip (integrated circuit device) and connected to a terminal of a package by, for example, a bonding wire or the like and that is for inputting/outputting a signal or a voltage between a circuit in the chip and an external circuit.
  • FIG. 3 shows an example configuration of a motor driver as an example configuration of a circuit device to which the above-described substrate configuration is applicable.
  • the circuit device 200 includes the bridge circuit 210 and the detection circuit 250 .
  • the detection circuit 250 includes the voltage detection circuit 220 , the reference voltage generation circuit 230 , and a control circuit 240 .
  • the embodiment is not limited to this. In other words, it is also possible that a portion (e.g., the bridge circuit 210 and the voltage detection circuit 220 ) of the circuit device is constituted by a single integrated circuit device, and the substrate configuration in FIG. 2 is applied to this integrated circuit device.
  • the bridge circuit 210 drives an external motor 280 (DC motor) based on a PWM signal from the control circuit 240 .
  • the bridge circuit 210 includes transistors Q 1 to Q 4 (DMOS transistors) arranged in an H-bridge.
  • the transistors Q 1 to Q 4 may be of N-type, or the transistors Q 1 and Q 2 may be of P-type and the transistors Q 3 and Q 4 be of N-type.
  • the transistor Q 1 is provided between the terminal TVB to which the power supply voltage VBB is supplied and a terminal OUT 1 to which one end of the motor 280 is connected.
  • the transistor Q 2 is provided between the terminal TVB and a terminal OUT 2 to which the other end of the motor 280 is connected.
  • the transistor Q 3 is provided between the terminal OUT 1 and a terminal RNF that is connected to one end of the sense resistor 290 that receives a ground voltage at the other end.
  • the transistor Q 4 is connected between the terminal OUT 2 and the terminal RNF.
  • the reference voltage generation circuit 230 is constituted by, for example, a voltage divider circuit and generates a reference voltage VR for detecting a chopping current.
  • the voltage detection circuit 220 is constituted by, for example, a comparator and performs detection of the chopping current flowing through the bridge circuit 210 . More specifically, the voltage detection circuit 220 compares a voltage VS at one end of the sense resistor 290 that is input via a terminal RNFS with the reference voltage VR. If the voltage detection circuit 220 detects that the voltage VS has reached the reference voltage VR, the voltage detection circuit 220 outputs a detection signal to the control circuit 240 .
  • the control circuit 240 controls the chopping operation of the bridge circuit 210 . More specifically, the control circuit 240 controls the pulse width of the PWM signal based on the detection signal from the voltage detection circuit 220 so as to keep the chopping current constant. Then, the control circuit 240 generates on/off control signals for the transistors Q 1 to Q 4 from the PWM signal and outputs the generated on/off control signals to the gates of the transistors Q 1 to Q 4 .
  • a comparator 221 shown in FIG. 4 corresponds to the voltage detection circuit 220 .
  • the voltage VS at one end of the sense resistor 290 and the reference voltage VR are input to the positive input terminal and the negative input terminal, respectively, of the comparator 221 .
  • An output signal of the comparator 221 is output to the control circuit 240 .
  • driving of the motor 280 is started at time t0.
  • a charge period starts as shown in FIG. 4 , and the control circuit 240 turns on the transistors Q 1 and Q 4 and turns off the transistors Q 2 and Q 3 .
  • a drive current flows from the power supply voltage VBB to the ground voltage via the transistor Q 1 , the motor 280 , the transistor Q 4 , and the sense resistor 290 , as indicated by the solid arrow in FIG. 4 .
  • the drive current increases with time, and the voltage VS converted by the sense resistor 290 also increases. Once the voltage VS exceeds the reference voltage VR, the output signal of the comparator 221 changes from the L level to the H level. As shown in FIG. 6 , a drive current at this point in time (time t1) is the chopping current Ich. The chopping current Ich is thus detected by detection of the voltage VS.
  • the control circuit 240 shifts to a decay period TD 1 .
  • the control circuit 240 turns on the transistors Q 2 and Q 3 and turns off the transistors Q 1 and Q 4 .
  • a drive current (regenerative current) flows from the ground voltage to the power supply voltage VBB via the sense resistor 290 , the transistor Q 3 , the motor 280 , and the transistor Q 2 , as indicated by the dashed arrow in FIG. 5 .
  • the drive current decreases with time.
  • the control circuit 240 shifts to a charge period TC 1 .
  • the drive current increases, and when the drive current reaches the chopping current Ich, the control circuit 240 shifts to a decay period TD 2 .
  • the control circuit 240 performs control so as to keep the chopping current Ich constant, thereby keeping the rotational speed of the motor 280 constant.
  • the bridge circuit 210 is constituted by an H-bridge was described as an example above, the embodiment is not limited to this, and the bridge circuit 210 may also be constituted by a half bridge.
  • FIG. 7 shows a detailed example configuration of an N-type transistor having a DMOS structure.
  • FIG. 7 is a cross-sectional view of the substrate in the thickness direction thereof. It should be noted that like components as those described with reference to FIG. 2 are denoted by like reference numerals, and a description thereof is omitted as appropriate.
  • the N-type transistor having the DMOS structure described with reference to FIG. 2 is configured symmetrically. That is, the N-type layer 122 corresponding to the source region is the center of symmetry, and gate layers 141 a and 141 b , insulating layers 151 a and 151 b , and N-type layers 123 a and 123 b corresponding to the drain regions are formed on both sides of the N-type layer 122 .
  • the deep N-type well 61 and the P-type body 71 are each formed on the N-type buried layer 51 so as to be symmetrical, where the source is the center of symmetry.
  • the N-type plugs 81 and 82 are formed on both sides of the deep N-type well 61 .
  • FIG. 8 shows a detailed example configuration of a P-type transistor having a DMOS structure.
  • FIG. 8 is a cross-sectional view of the substrate in the thickness direction thereof.
  • each layer is configured symmetrically, where a P-type layer 136 corresponding to the drain region is the center of symmetry. More specifically, an N-type buried layer 53 is formed on the P-type substrate 41 , and a deep N-type well 62 is formed on the N-type buried layer 53 . An HPOF 161 (P-type impurity layer) is formed on a center portion of the deep N-type well 62 , and the P-type layer 136 corresponding to the drain region is formed on the HPOF 161 .
  • P-type impurity layer P-type impurity layer
  • N-type wells 113 a and 113 b are formed on bath end portions of the deep N-type well 62 , and N-type layers 171 a and 171 b as well as P-type layers 137 a and 137 b corresponding to the source regions are formed on the N-type wells 113 a and 113 h .
  • LV NWEL low-voltage N-type wells
  • Insulating layers 152 a and 152 b are formed on both sides of the P-type layer 136 corresponding to the drain region, and gate layers 144 a and 144 b (e.g., polysilicon layers) are formed above the N-type wells 113 a and 113 b , the HPOF 161 , and the insulating layers 152 a and 152 b.
  • gate layers 144 a and 144 b e.g., polysilicon layers
  • a potential (e.g., power supply voltage) is supplied to the N-type buried layer 53 via N-type plugs 85 a and 85 b .
  • the N-type plugs 85 a and 85 b are formed on both sides of the deep N-type well 62 , and N-type layers 172 a and 172 b are formed on the N-type plugs 85 a and 85 b , respectively.
  • the P-type transistor having the DMOS structure may also be constituted by one gate of the two gates of the above symmetrical configuration and the drain.
  • FIGS. 9A to 12C A process flow for manufacturing a transistor having a DMOS structure will be described using FIGS. 9A to 12C . Note that an N-type transistor is shown on the left side of the drawings, and a P-type transistor is shown on the right side of the drawings.
  • a step of forming an oxide film (SiO 2 ) on a P-type substrate (Psub) is performed.
  • a photolithography step is performed, and a step of etching the oxide film (SiO 2 ) in regions that are not covered by the resist is performed.
  • a step of implanting N-type ions into the P-type substrate (Psub) is performed, whereby N-type buried layers (NEL) are formed in the regions that are not covered by the oxide film (SiO 2 ).
  • an etching step is performed to remove the oxide film (SiO 2 ), and a photolithography step is performed.
  • a step of implanting P-type ions into the P-type substrate (Psub) is performed to form P-type buried layers (PBL) in regions that are not covered by the resist.
  • a step of forming a P-type epitaxial layer (P-Epi) on the P-type substrate (Psub) and the buried layers (NEL, PBL) is performed.
  • the N-type buried layers (NEL) and the P-type buried layers (PBL) are formed under the P-type epitaxial layer (P-Epi).
  • a photolithography step and a step of implanting N-type ions into the P-type epitaxial layer (P-Epi) are performed, whereby deep N-type wells (Deep NWEL) are formed in regions that are not covered by the resist.
  • a photolithography step and a step of implanting N-type ions into the P-type epitaxial layer (P-Epi) are performed, whereby N-type plugs (Nplug) are formed in regions that are not covered by the resist.
  • a photolithography step and an etching step of a silicon nitride film are performed, and an oxide film forming step is performed, whereby LOCOS is performed where SiO 2 is formed.
  • a photolithography step and a step of implanting P-type ions into the deep N-type well are performed, whereby a P-type body (Pbody) is formed in a region that is not covered by the resist.
  • a photolithography step and a step of implanting P-type ions into the deep N-type well are performed, whereby an HPOF layer is formed in a region that is not covered by the resist.
  • a photolithography step and a step of implanting N-type ions into the deep N-type well are performed, whereby low-voltage N-type wells (LV NWEL) are formed in regions that are not covered by the resist.
  • LV NWEL low-voltage N-type wells
  • a photolithography step and a step of implanting P-type ions into the P-type epitaxial layer (P-Epi) are performed, whereby a low-voltage P-type well (LV PWEL) is formed in a region that is not covered by the resist.
  • LV PWEL low-voltage P-type well
  • a step of forming polysilicon layers is performed, and a photolithography step and an etching step are performed, whereby gate layers (Poly) are formed.
  • a photolithography step and a step of implanting N-type ions are performed, whereby N-type impurity layers (N+) are formed in a surface portion of the substrate.
  • the N-type impurity layers (N+) constitute the source region, the drain region, and the like of the N-type transistor.
  • a photolithography step and a step of implanting P-type ions are performed, whereby P-type impurity layers (P+) are formed in the surface portion of the substrate.
  • the P-type impurity layers (P+) constitute the source region, the drain region, and the like of the P-type transistor.
  • CMOS complementary metal-oxide-semiconductor
  • DMOS complementary metal-oxide-semiconductor
  • FIG. 13 shows an example configuration of an electronic apparatus to which the circuit device 200 (motor driver) of this embodiment is applied.
  • the electronic apparatus includes a processing unit 300 , a storage unit 310 , an operation unit 320 , an input/output unit 330 , the circuit device 200 , a bus 340 that connects these units to one another, and a motor 280 .
  • a printer where a head and a paper feeder are controlled by motor drive is to be described as an example, this embodiment is not limited to this, but can be applied to various types of electronic apparatuses.
  • the input/output unit 330 is constituted by interfaces such as a USE connector and wireless LAN, to which image data and document data are input.
  • the input data is stored in the storage unit 310 which is an internal storage such as a DRAM, for example.
  • the processing unit 300 starts printing of data stored in the storage unit 310 .
  • the processing unit 300 issues an instruction to the circuit device 200 (motor driver) in accordance with the print layout of the data, and the circuit device 200 rotates the motor 280 based on the instruction to execute movement of the head or paper feeding.
  • circuit device 200 can keep the chopping current constant with high precision, errors in the movement of the head or the paper feeding can be prevented or reduced, permitting high-quality printing.

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KR101589144B1 (ko) 2016-01-27
CN104038120B (zh) 2018-04-27
US20190221566A1 (en) 2019-07-18
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JP2014170831A (ja) 2014-09-18
TW201440439A (zh) 2014-10-16

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