1352428 01-2005-004 19509twf.doc/006 九、發明說明： ‘ 【發明所屬之技術領域】 ‘ 本發明是有關於一種半導體元件，且特別是有關於一 . 種防止閂鎖現象的半導體元件。 ' 【先前技術】 半導體元件的設計，必須隨著日趨提高的積集度 (integration)及曰益複雜的需求而不斷改進。舉例而言， ® 高壓元件的設計必須使元件能夠容忍高電壓操作而且不 會影響其他元件的操作。以下利用圖丨來說明一種高壓元 件的問題及限制。 圖1是習知的一種高壓元件的剖面示意圖。此高壓元 件是一互補式金氧半場效電晶體（c〇mplementary metal 〇jddesemiconductor’ CM0S)，其是由兩個橫向雙擴散金 氧半場效電晶體（lateral double-diffused metal oxide semiconductor，LDMOS)所構成。 • 請參照圖卜此高壓元件包括P型基底（P-sub) 100、 閘極102及1〇4、閘介電層106及1〇8、p井（p_WELL) 112p、P 槽（p_TUB) 114p、摻雜區 ιΐ6ρ、ιΐ8ρ 及 120p、 N 槽（N-TUB) 122η 及 124η、摻雜區 126η、128η 及 130η、 隔離結構134、介電層ι36、内連線（inte_nect) 138及 介電層140。其中，ρ型基底1〇〇可分為區域HVNM〇s及 HVPMOS ’分別包含高壓N型金氧半場效電晶體及高壓p 型金氧半場效電晶體。摻雜區i26n、i28n及閘極102分別 1352428 01-2005-004 19509twfdoc/006 疋同壓N型金氧半場效電晶體源極、祕及閘極，換雜區 12〇P、U8p及閘極104分別是高壓p型金氧半場效電晶體 的源極、沒極及閘極。摻雜區116p、U8p及i2〇p是 的傳導類型（conductivity type)，且摻雜區 126n、i28n 及130η是n+的傳導類型。 圖1的高壓元件會有以下缺點：1352428 01-2005-004 19509twf.doc/006 IX. Description of the invention: ‘Technical field to which the invention pertains 』 The present invention relates to a semiconductor element, and more particularly to a semiconductor element that prevents latch-up. [Prior Art] The design of semiconductor components must be continuously improved with increasing integration and complexity. For example, ® high voltage components must be designed so that they can tolerate high voltage operation without affecting the operation of other components. The following is a diagram to illustrate the problems and limitations of a high voltage component. 1 is a schematic cross-sectional view of a conventional high voltage component. The high voltage component is a complementary metal oxide half field effect transistor (c〇mplementary metal 〇jddesemiconductor' CM0S), which is composed of two lateral double-diffused metal oxide semiconductors (LDMOS). Composition. • Please refer to the figure. This high voltage component includes P-substrate (P-sub) 100, gate 102 and 1〇4, gate dielectric layer 106 and 1〇8, p-well (p_WELL) 112p, P-slot (p_TUB) 114p. Doped regions ιΐ6ρ, ιΐ8ρ and 120p, N-channels (N-TUB) 122η and 124η, doped regions 126η, 128η and 130η, isolation structure 134, dielectric layer ι36, interconnect (inte_nect) 138 and dielectric layer 140. Among them, the p-type substrate 1〇〇 can be divided into regions HVNM〇s and HVPMOS', respectively, including a high-voltage N-type gold-oxygen half-field effect transistor and a high-voltage p-type gold-oxygen half-field effect transistor. Doped regions i26n, i28n and gate 102 respectively 1352428 01-2005-004 19509twfdoc/006 疋N-type gold-oxygen half-field effect transistor source, secret and gate, change region 12〇P, U8p and gate 104 is the source, the pole and the gate of the high voltage p-type gold oxide half field effect transistor, respectively. The doped regions 116p, U8p, and i2〇p are of a conductivity type, and the doped regions 126n, i28n, and 130n are n+ conduction types. The high voltage component of Figure 1 has the following disadvantages:
1，此高壓元时有_縣（丨磁_up)。更詳細而言，推 雜區120P、N槽124n及P型基底则構成一個寄生的 雙載子電晶體的射極、基極及集極，換雜區126n、p型 基底100及N；ff 124η構成另一個寄生的雙載子電晶體 的射極、基極及集極。當兩個雙載子電晶體的電流增益 乘積大於1時’此高壓元件將無法正常操作。 2.上述之ΜΡ型金氧半場效電晶體及高壓Ν型金 效電晶體是配置在Ρ型基底削上。由於施加在摻雜區 120ρ上的輸人電壓會直接施加於Ρ型基底⑽，因此輪1, this high-pressure element has _ county (丨磁_up). In more detail, the dummy region 120P, the N-channel 124n and the P-type substrate constitute an emitter, a base and a collector of a parasitic bipolar transistor, a replacement region 126n, a p-type substrate 100 and N; ff 124η constitutes the emitter, base and collector of another parasitic bipolar transistor. When the current gain product of the two bipolar transistors is greater than 1, the high voltage component will not operate properly. 2. The above-mentioned bismuth type gold oxide half field effect transistor and high voltage Ν type gold effect transistor are arranged on the 基底 type substrate. Since the input voltage applied to the doped region 120p is directly applied to the 基底-type substrate (10), the wheel
公電壓將受到很大的限制’進而減縮此高壓元件的操作 圍。 -般而言’Ρ型基底1〇〇上更配置有其他的半導體元件。 然而此高壓元件兩側沒有足夠的隔離結構 (isolation) ’因此缝元件會與這些半導體元件互相 1352428 01-2005-004 19509twf.doc/006 【發明内容】 有鑑於此，本發明之目的是提供一種半導體元件以 改善輸入電壓受限的問題，並避免與其他的半導體元件互 - 相干擾。 本發明之另一目的是提供一種互補式金氧半場效電 晶體，以改善閂鎖現象。 為達上述或是其他目的，本發明提出一種半導體元 • 件，包括基底、磊晶層、下沈層、主動元件、第一埋入層 及第二埋入層。基底具有第一傳導類型（c〇nductivity type)。磊晶層具有第二傳導類型，且配置於基底上。下 沈層（sinker)，具有第二傳導類型，且配置於磊晶層中。 下沈層自基底延伸至磊晶層上表面，且將磊晶層分隔出一 個Q域。主動元件配置於此區域内。第一埋入層（burie(j layer)具有第一傳導類型，且配置於上述區域及基底之 間。第二埋入層具有第二傳導類型，且配置於第一埋入層 及基底之間。第二埋入層連接下沈層。 • 在本發明之一實施例中，上述之半導體元件更包括第 二埋入層。第二埋入層具有第一傳導類型，且配置於第二 埋入層及基底之間。第三埋入層的摻質濃度例如是大於基 底的摻質濃度。 在本發明之一實施例中，上述之第一埋入層的摻質濃 度例如是大於基底的摻質濃度。 在本發明之一實施例中’上述之主動元件為高壓金氧 半場效電晶體（high voltage metal oxide semiconductor， 01-2005-004 19509twf.doc/006 HVMOS)。 在本發明之一實施例中’上述之第一傳導類型是p 型’且第二傳導類型是N型。在本發明另一實施例中，上 述之第一傳導類型是N型，且第二傳導類型是p型。 為達上述或是其他目的，本發明再提供一種互補式金 氧半場效電晶體’包括基底、蟲晶層、第一下沈層、第二 下沈層、井區、第一電晶體、第二電晶體、第一埋入層及 第二埋入層。基底具有第一傳導類型。磊晶層具有第二傳 導類型，且配置於基底上。第一下沈層具有第二傳導類型， 且配置於磊晶層中。第一下沈層自基底延伸至磊晶層上表 面，且將磊晶層分隔出第一區域。第二下沈層具有第二傳 導類型，且配置於磊晶層中。第二下沈層自基底延伸至磊 晶層上表面，且將第一區域以外的磊晶層分隔出第二區 域。井區具有第一傳導類型，且配置於第一區域内。第一 電晶體配置於井區内，且第二電晶體配置於第二區域内。 第一埋入層具有第一傳導類型，且配置於第一區域及基底 之間。第二埋入層具有第二傳導類型，且配置於第一埋入 層及基底之間。第二埋入層配置於第二區域及基底之間。 j中，配置於第一埋入層及基底之間的第二埋入層連接第 一y沈層，且配置於第二區域及基底之間的第二埋入層連 接第—下沈層。 ，本發明之一實施例中，上述之互補式金氧半場效電 曰曰-包括第三埋入層。第三埋入層具有第一傳導類型， 且配置於該第-埋人層下方的第二埋人層及基底之間。此 1352428 01-2005-004 19509twf.doc/006 外，第二埋入層的摻質濃度例如是大於基底的摻質渡戶。 在本發明之一實施例中，上述之第一埋入層的摻質濃 度例如是大於基底的摻質濃度。 / ' 在本發明之一實施例中，上述之第一電晶體及第二電 晶體例如是高壓金氧半場效電晶體。 在本發明之一實施例中，上述之第一傳導類型是p 型，且第二傳導類型是N型。此外，在本發明之另一實施 例中，第一傳導類型是\型，且第二傳導類型是p型二 本發明可以避免互補式金氧半場效電晶體的閂鎖現 象、增加輸入電壓的容許範圍，並與基底上其他的半導體 元件被有效地隔離。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 一為了改善習知半導體元件的缺點，本發明是將半導體 疋件置於基底上的县晶層中。更詳細而言，蠢晶層及基底 ，有相反的傳導_ ’因此能夠提供二極體的整流功能， 從而防止多餘的載子注入（inject)基底。此外，在遙晶層 與基底之間置有兩個埋人層’且可以經由下沈層來將埋 ^層與外界電性連接。藉由埋人層的^置，可以改變寄生 -極體或寄生電晶體的結構。再者，由於^置有埋入層， 且調整埋人層的電位可以避免半導體元件的輸人電壓全部 1352428 01-2005-004 19509twf.doc/006 施加於基底，因此可以增加半導體元件的操作範圍。此外， 上述的結構可以有效地防止閂鎖現象。以下利用第一及第 二實施例來詳細說明上述的結構。 【第一實施例】 圖2是本發明第-實施例的一種半導體元件的剖面示 意圖。 請參照圖2，本發明的半導體元件包括基底2〇〇、磊 晶層202η、下沈層204η、主動元件A卜第一埋入層2〇6p 及第二埋入層208η。在本實施例中，此半導體件 隔離結構21〇、介電層212、井區214ρ、1層 區218ρ、内連線234、236、238及240,然而本發明並不 限定於此。主動元件Α1可以是任何一種主動元件。主動 元件Α1例如是高壓金氧半場效電晶體，包括橫向雙擴散 金氧半場效電晶體。在本實施例中，主動元件A1是以另 一種高壓金氧半場效電晶體為例，主動元件A1包括閘極 220、閘介電層 222、摻雜區 226ρ、228η、230η 及 232η。 此外，如圖2所示，上述各構件的傳導類型是以p_sub、 N-epi、N、PBL、NBL、p_WELL、n+、p+、N-drift 等名 稱來表示，以使於本領域具有通常知識者易於瞭解，然而 並非用以限定本發明。換言之，在另一實施例中，上述各 構件例如具有相反的傳導類型。另外，在本實施例中，第 一傳導類型是P型，而第二傳導類型是N型。然而在另— 實施例中，第一傳導類型是，而第二傳導類型是p型。 基底200具有第一傳導類型。磊晶層2〇2n具有第二 01-2005-004 19509twf.doc/006 傳導類型，且磊晶層202n配置於基底200上。磊晶層202η 及基底200構成一個二極體。在操作主動元件Α1時，此 二極體的整流功能可以防止載子注入基底20(^下沈層 204η具有第二傳導類型。下沈層2〇4η配置於磊晶層202η 中’且自基底200延伸至磊晶層202η上表面。下沈層204η 將磊晶層202η分隔出一區域R1，且井區214ρ配置於區域 R1内。此外’内連線240配置於介電層212中，且電性連 接下沈層204η。主動元件Α1配置於井區214ρ内。主動元 件Α1的摻雜區226ρ具有第一傳導類型，且主動元件A1 的摻雜區228η、230η及232η具有第二傳導類型。其中， 摻雜區228η、230η及232η分別是主動元件A1的源極、 汲極及漂移區（drift region)。摻雜區228η及230η分別 配置於閘極220兩侧的井區214ρ中，且摻雜區230η配置 於摻雜區232η中。另外，内連線234、238及236配置於 介電層212中，且分別電性連接摻雜區23〇η、閘極22〇、 摻雜區228η及226ρ。 第一埋入層206ρ具有第一傳導類型，且配置於區域 R1及基底200之間。第一埋入層2〇6ρ例如與井區214ρ 相連。第二埋入層208η具有第二傳導類型，且配置於第一 埋入層206ρ及基底200之間。第二埋入層2〇811連接下沈 層204η。第一埋入層206ρ及第二埋入層2〇8η例如是重摻 雜（heavilydoped)的摻雜區。其中第一埋入層2〇6ρ的摻 質濃度例如是大於基底2〇〇的摻質濃度，且第二埋入層 208η的摻質濃度例如大於蟲晶| 2〇2η的摻質濃度。由於 1352428 01-2005-004 19509twf.doc/006 設置有第一埋入層206p及第二埋入層208n，主動元件A1 的輸入電壓不會全部施加於基底200,因此可以增加此輸 入電壓的容許範圍。舉例而言，若在内連線234上施加高 電壓，則第一埋入層206p及第二埋入層208η可以避免磊 晶層202η及基底200的介面發生電崩潰（breakdown)。 再者，當在内連線234上施加高電壓時，内連線240的電 位例如低於内連線234的電位，且高於内連線236的電位。 因此’上述的高電壓得以直接施加於内連線240，以進一 步避免磊晶層202η及基底200的介面發生電崩潰。因此， 施加於内連線234的電壓可以有更大的容許範圍。顯而易 見的是，施加於内連線236的電壓也可以有更大的容許範 圍。如此，下沈層204η、第一埋入層206ρ及第二埋入層 208η可以避免施加於主動元件Α1的電壓干擾基底200上 其他的半導體元件。下沈層204η、第一埋入層206ρ及第 二埋入層208η也可以避免主動元件A1被基底2〇〇上其他 的半導體元件干擾。因此，主動元件A1不會造成其他半 導體元件發生閂鎖現象。 另外’上述之半導體元件可以包括第三埋入層2l5p， 具有第一傳導類型。第三埋入層215p配置於第二埋入層 208η及基底200之間。第三埋入層2i5p例如是重摻雜的 摻雜區，其摻質濃度例如是大於基底2〇〇的摻質濃度。在 此半導體元件的製程中，第三埋入層2i5p例如是與第一埋 入層206p同時形成。 另一方面，上述之半導體元件還可以包括一個接合隔 12 1352428 01-2005-004 19509twf.doc/006 離結構（junction isolation)。此接合隔離結構具有第一傳 導類型，並將上述半導體元件與基底200上其他的半導體 元件隔離。在本實施例中，此接合隔離結構例如是由另一 埋入層216p及另一井區218p所構成。埋入層216p自基底 200延伸至磊晶層2〇2n，而井區218p自埋入層216p延伸 至磊晶層202η上表面。在此半導體元件的製程中，埋入層 216ρ例如是與第一埋入層2〇6ρ同時形成，且井區2ΐ8ρ例 如是與井區214ρ同時形成。 以下利用一種互補式金氧半場效電晶體來說明此半 導體元件防止閂鎖現象的功能。 【第二實施例】 圖3疋本發明第二實施例的一種互補式金氧半場效電 晶體的剖面示意圖。為簡化說明内容，以下僅說明與第一 實施例的不同處。 請參照圖3，此互補式金氧半場效電晶體包括第一電 a曰體及第一電晶體A2。在本實施例中，第一電晶體即是上 述之主動元件A1，其例如是高壓金氧半場效電晶體。第二 電晶體A2例如也是高壓金氧半場效電晶體。然而本發明 ，不限於此，換言之，第一電晶體及第二電晶體A2可以 疋，彳可—種金氧半場效電晶體。在本實施例中，此互補式 金氧半場效電晶體還包括内連線318、32〇、322及324， 配置於介電層212内。然而本發明並不限定於此。 此互補式金氧半場效電晶體更包括下沈層302η。下沈 印302η具有第—傳導類型，且配置於蠢晶層中。下 13 1352428 01-2005-004 19509nvf.doc/006 沈層302n自基底200延伸至磊晶層202n上表面，且將區 域R1以外的磊晶層202η分隔出區域R2。内連線324電 性連接下沈層302η。第二電晶體Α2配置於區域R2内。 第二電晶體Α2包括閘極306、閘介電層308、摻雜區31〇η、 312ρ、314ρ及316ρ。其中摻雜區312ρ、314ρ及316ρ分別 是第二電晶體Α2的源極、沒極及漂移區。捧雜區3ΐ〇η具 有第二傳導類型，且摻雜區312ρ、314ρ及316ρ具有第一 傳導類型。摻雜區312ρ及摻雜區314ρ位於閘極306兩侧 的蟲晶層202η内，且摻雜區314ρ位於摻雜區316ρ内。在 本實施例中，摻雜區316ρ更以P-drift來表示。此外，内 連線318、322及320分別電性連接摻雜區314p、閘極3〇6、 換雜區31 On及312p。 第二埋入層208η更配置於區域R2及基底200之間。 配置於區域R2及基底200之間的第二埋入層2〇8η連接下 沈層302η。因為設置了下沈層204η、302η、第一埋入層 206ρ及第二埋入層208η，所以改變了由摻雜區312ρ、磊 晶層202η、基底200及摻雜區228η所構成的寄生二極體 的結構，從而防止閂鎖現象。此外，摻雜區312ρ、磊晶層 202η及基底200分別構成一個寄生的雙載子電晶體的射 極、基極及集極，且摻雜區228η、基底200及磊晶層202η 分別構成另一個寄生的雙載子電晶體的射極、基極及集 極。另外，由上述可知，第一埋入層2〇6ρ及第二埋入層 =8η可以是重摻雜的摻雜區，因此增加了上述基極的摻雜 濃度，從而降低上述的雙載子電晶體的電流增益。再者， 1352428 01-2005-004 19509twf,doc/006The male voltage will be greatly limited', which in turn reduces the operating envelope of the high voltage component. In general, other semiconductor elements are disposed on the Ρ-type substrate 1 〇〇. However, there is not enough isolation on both sides of the high-voltage element. Therefore, the slit element and the semiconductor element are mutually opposed. 1352428 01-2005-004 19509twf.doc/006 [Invention] In view of the above, it is an object of the present invention to provide a Semiconductor components improve the problem of limited input voltage and avoid mutual-interference with other semiconductor components. Another object of the present invention is to provide a complementary MOS field effect transistor to improve the latch-up phenomenon. To achieve the above or other objects, the present invention provides a semiconductor device including a substrate, an epitaxial layer, a sinker layer, an active device, a first buried layer, and a second buried layer. The substrate has a first conductivity type (c〇nductivity type). The epitaxial layer has a second conductivity type and is disposed on the substrate. A sinker having a second conductivity type and disposed in the epitaxial layer. The sinking layer extends from the substrate to the upper surface of the epitaxial layer and separates the epitaxial layer from a Q domain. Active components are configured in this area. The first buried layer (bye) has a first conductivity type and is disposed between the region and the substrate. The second buried layer has a second conductivity type and is disposed between the first buried layer and the substrate The second buried layer is connected to the sink layer. In an embodiment of the invention, the semiconductor element further includes a second buried layer. The second buried layer has a first conductivity type and is disposed in the second buried layer. The concentration of the dopant of the third buried layer is, for example, greater than the dopant concentration of the substrate. In one embodiment of the present invention, the dopant concentration of the first buried layer is, for example, greater than the substrate. In one embodiment of the present invention, the active element is a high voltage metal oxide semiconductor (01-2005-004 19509 twf. doc/006 HVMOS). In the embodiment, 'the first conductivity type is p-type' and the second conductivity type is N. In another embodiment of the invention, the first conductivity type is N-type and the second conductivity type is p-type For the above or other purposes, this Further providing a complementary MOS field effect transistor 'including a substrate, a worm layer, a first sink layer, a second sink layer, a well region, a first transistor, a second transistor, a first buried layer And a second buried layer. The substrate has a first conductivity type. The epitaxial layer has a second conductivity type and is disposed on the substrate. The first sink layer has a second conductivity type and is disposed in the epitaxial layer. The sink layer extends from the substrate to the upper surface of the epitaxial layer, and separates the epitaxial layer from the first region. The second sink layer has a second conductivity type and is disposed in the epitaxial layer. The second sink layer is from the substrate Extending to an upper surface of the epitaxial layer, and separating the epitaxial layer outside the first region from the second region. The well region has a first conductivity type and is disposed in the first region. The first transistor is disposed in the well region. And the second transistor is disposed in the second region. The first buried layer has a first conductivity type and is disposed between the first region and the substrate. The second buried layer has a second conductivity type and is disposed at the first Buried between the layer and the substrate. The second buried layer is disposed in the second region And a second buried layer disposed between the first buried layer and the substrate is connected to the first y-thick layer, and the second buried layer is disposed between the second region and the substrate. a sinking layer. In one embodiment of the present invention, the complementary MOS field device includes a third buried layer. The third buried layer has a first conductivity type and is disposed in the first Between the second buried layer and the substrate below the buried layer. In addition to the 1352428 01-2005-004 19509twf.doc/006, the dopant concentration of the second buried layer is, for example, greater than the dopant of the substrate. In one embodiment of the invention, the doping concentration of the first buried layer is, for example, greater than the dopant concentration of the substrate. / ' In one embodiment of the invention, the first transistor and the second transistor are, for example, It is a high voltage gold oxide half field effect transistor. In an embodiment of the invention, the first conductivity type is a p-type and the second conductivity type is an N-type. In addition, in another embodiment of the present invention, the first conductivity type is a type, and the second conductivity type is a p-type. The invention can avoid the latch-up phenomenon of the complementary MOS field-effect transistor and increase the input voltage. The allowable range is effectively isolated from other semiconductor components on the substrate. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. [Embodiment] In order to improve the disadvantages of the conventional semiconductor device, the present invention places a semiconductor element in a crystal layer on a substrate. In more detail, the stray layer and the substrate, with opposite conduction _', can provide a rectifying function of the diode, thereby preventing unwanted carriers from injecting into the substrate. In addition, two buried layers are placed between the crystal layer and the substrate, and the buried layer can be electrically connected to the outside through the sinking layer. The structure of the parasitic-pole or parasitic transistor can be changed by the buried layer. Furthermore, since the buried layer is provided and the potential of the buried layer is adjusted, the input voltage of the semiconductor element can be prevented from being applied to the substrate, so that the operating range of the semiconductor element can be increased. . Further, the above structure can effectively prevent the latch-up phenomenon. The above structure will be described in detail below using the first and second embodiments. [First Embodiment] Fig. 2 is a cross-sectional view showing a semiconductor device of a first embodiment of the present invention. Referring to Fig. 2, the semiconductor device of the present invention comprises a substrate 2?, an epitaxial layer 202?, a sinker layer 204?, an active device A, a first buried layer 2?6p, and a second buried layer 208n. In the present embodiment, the semiconductor device isolation structure 21, the dielectric layer 212, the well region 214p, the first layer region 218p, the interconnect lines 234, 236, 238, and 240, but the present invention is not limited thereto. The active component Α1 can be any active component. The active element Α1 is, for example, a high voltage MOS half field effect transistor, including a lateral double diffused MOS field effect transistor. In the present embodiment, the active device A1 is exemplified by another high-voltage gold-oxygen half field effect transistor. The active device A1 includes a gate 220, a gate dielectric layer 222, and doped regions 226ρ, 228η, 230η, and 232n. In addition, as shown in FIG. 2, the conduction types of the above components are represented by names such as p_sub, N-epi, N, PBL, NBL, p_WELL, n+, p+, N-drift, etc., so as to have common knowledge in the field. It is easy to understand, but is not intended to limit the invention. In other words, in another embodiment, each of the above-described members has, for example, an opposite conductivity type. Further, in the present embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. In another embodiment, however, the first conductivity type is, and the second conductivity type is p-type. Substrate 200 has a first conductivity type. The epitaxial layer 2〇2n has a second 01-2005-004 19509 twf.doc/006 conductivity type, and the epitaxial layer 202n is disposed on the substrate 200. The epitaxial layer 202n and the substrate 200 constitute a diode. When the active device Α1 is operated, the rectifying function of the diode can prevent the carrier from being injected into the substrate 20 (the sinking layer 204n has the second conductivity type. The sinking layer 2〇4η is disposed in the epitaxial layer 202n' and from the substrate 200 extends to the upper surface of the epitaxial layer 202n. The sinker layer 204n separates the epitaxial layer 202n from a region R1, and the well region 214p is disposed in the region R1. Further, the 'interconnect 240' is disposed in the dielectric layer 212, and The sink layer 204n is electrically connected. The active device Α1 is disposed in the well region 214p. The doped region 226p of the active device Α1 has a first conductivity type, and the doped regions 228n, 230n, and 232n of the active device A1 have a second conductivity type. The doped regions 228η, 230η, and 232η are respectively the source, the drain, and the drift region of the active device A1. The doped regions 228n and 230η are respectively disposed in the well region 214p on both sides of the gate 220, The doping region 230n is disposed in the doping region 232n. In addition, the interconnecting wires 234, 238, and 236 are disposed in the dielectric layer 212, and are electrically connected to the doping region 23〇n, the gate electrode 22〇, and doped, respectively. Regions 228η and 226ρ. The first buried layer 206p has a first conduction class And disposed between the region R1 and the substrate 200. The first buried layer 2〇6ρ is connected to the well region 214p, for example. The second buried layer 208n has a second conductivity type and is disposed on the first buried layer 206p and the substrate. The second buried layer 2 811 is connected to the sink layer 204n. The first buried layer 206p and the second buried layer 2〇8n are, for example, heavily doped doped regions. The doping concentration of the intrusion layer 2〇6ρ is, for example, greater than the dopant concentration of the substrate 2〇〇, and the dopant concentration of the second buried layer 208n is, for example, greater than the dopant concentration of the insect crystal | 2〇2η. Since 1352428 01-2005 -004 19509twf.doc/006 The first buried layer 206p and the second buried layer 208n are provided, and the input voltage of the active device A1 is not all applied to the substrate 200, so the allowable range of the input voltage can be increased. If a high voltage is applied to the interconnect 234, the first buried layer 206p and the second buried layer 208n can prevent electrical breakdown of the interface between the epitaxial layer 202n and the substrate 200. When a high voltage is applied to the line 234, the potential of the interconnect 240 is, for example, lower than the interconnect 2 The potential of 34 is higher than the potential of the interconnect 236. Therefore, the above-mentioned high voltage can be directly applied to the interconnect 240 to further prevent electrical breakdown of the interface between the epitaxial layer 202n and the substrate 200. Therefore, it is applied thereto. The voltage across line 234 can have a larger tolerance range. It will be apparent that the voltage applied to interconnect 236 can have a greater tolerance. As such, the sinker layer 204n, the first buried layer 206p, and the second buried layer 208n can prevent the voltage applied to the active device Α1 from interfering with other semiconductor components on the substrate 200. The sinker layer 204n, the first buried layer 206p, and the second buried layer 208n can also prevent the active device A1 from being disturbed by other semiconductor elements on the substrate 2. Therefore, the active element A1 does not cause latching of other semiconductor elements. Further, the above-mentioned semiconductor element may include a third buried layer 2l5p having a first conductivity type. The third buried layer 215p is disposed between the second buried layer 208n and the substrate 200. The third buried layer 2i5p is, for example, a heavily doped doped region whose dopant concentration is, for example, greater than the dopant concentration of the substrate. In the process of the semiconductor device, the third buried layer 2i5p is formed, for example, simultaneously with the first buried layer 206p. Alternatively, the semiconductor device described above may further comprise a junction isolation 12 1352428 01-2005-004 19509 twf.doc/006 junction isolation. The bonded isolation structure has a first conductivity type and isolates the semiconductor component from other semiconductor components on the substrate 200. In the present embodiment, the joint isolation structure is constituted by, for example, another buried layer 216p and another well region 218p. The buried layer 216p extends from the substrate 200 to the epitaxial layer 2〇2n, and the well region 218p extends from the buried layer 216p to the upper surface of the epitaxial layer 202n. In the process of the semiconductor device, the buried layer 216p is formed, for example, simultaneously with the first buried layer 2?6?, and the well region 2?8? is formed at the same time as the well region 214p. The following uses a complementary MOS field effect transistor to illustrate the function of the semiconductor element to prevent latch-up. [Second Embodiment] Fig. 3 is a cross-sectional view showing a complementary MOS field effect transistor of a second embodiment of the present invention. In order to simplify the description, only differences from the first embodiment will be described below. Referring to FIG. 3, the complementary MOS field effect transistor includes a first electric a body and a first transistor A2. In the present embodiment, the first transistor is the above-described active device A1, which is, for example, a high voltage MOS field effect transistor. The second transistor A2 is, for example, also a high voltage gold oxide half field effect transistor. However, the present invention is not limited thereto, in other words, the first transistor and the second transistor A2 may be a metal oxide half field effect transistor. In this embodiment, the complementary MOS field-effect transistor further includes interconnects 318, 32A, 322, and 324 disposed in the dielectric layer 212. However, the invention is not limited thereto. The complementary MOS field effect transistor further includes a sink layer 302n. The sinker 302n has a first conductivity type and is disposed in the stray layer. Next 13 1352428 01-2005-004 19509nvf.doc/006 The sink layer 302n extends from the substrate 200 to the upper surface of the epitaxial layer 202n, and separates the epitaxial layer 202n outside the region R1 out of the region R2. The interconnect 324 is electrically connected to the sinker layer 302n. The second transistor Α2 is disposed in the region R2. The second transistor Α2 includes a gate 306, a gate dielectric layer 308, doped regions 31〇η, 312ρ, 314ρ, and 316ρ. The doped regions 312ρ, 314ρ, and 316ρ are the source, the immersion, and the drift region of the second transistor 分别2, respectively. The doped region 3 ΐ〇 has a second conductivity type, and the doped regions 312ρ, 314ρ, and 316ρ have a first conductivity type. The doped region 312p and the doped region 314p are located in the crystal layer 202n on both sides of the gate 306, and the doped region 314p is located in the doped region 316p. In the present embodiment, the doping region 316p is further represented by P-drift. In addition, the interconnects 318, 322, and 320 are electrically connected to the doped region 314p, the gate 3〇6, and the swap regions 31 On and 312p, respectively. The second buried layer 208n is disposed between the region R2 and the substrate 200. The second buried layer 2〇8η disposed between the region R2 and the substrate 200 is connected to the sinker layer 302n. Since the sinker layers 204n, 302n, the first buried layer 206p, and the second buried layer 208n are disposed, the parasitic two formed by the doped region 312p, the epitaxial layer 202n, the substrate 200, and the doped region 228n are changed. The structure of the pole body to prevent latch-up. In addition, the doped region 312p, the epitaxial layer 202n, and the substrate 200 respectively constitute an emitter, a base, and a collector of a parasitic bipolar transistor, and the doped region 228n, the substrate 200, and the epitaxial layer 202n respectively constitute another The emitter, base and collector of a parasitic bipolar transistor. In addition, as can be seen from the above, the first buried layer 2〇6ρ and the second buried layer=8η may be heavily doped doped regions, thereby increasing the doping concentration of the base, thereby reducing the above-described double carrier. The current gain of the transistor. Furthermore, 1352428 01-2005-004 19509twf, doc/006
第二電晶體Α2與基底200上其他的半導體元件得以被有 效地隔離。The second transistor Α2 is effectively isolated from other semiconductor components on the substrate 200.
經由調整内連線240及324的電位，可以改變上述的電流 增益，以進一步避免閂鎖現象。另一方面，施加於第二電 晶體A2的電壓可以具有更大的範圍。舉例而言，若在内 連線320上施加高輸入電壓，由於可以調整内連線324的 電位’因此上述的輸入電壓得以直接施加於内連線324， 月b夠避免此輸入電壓直接施加於基底2〇〇，以進一步避免 磊晶層202η及基底200的介面發生電崩潰。因此，施加於 ，連線320的電壓可以有更大的容許範圍。顯而易見的 是，施加於内連線318的電壓也可以有更大的容許範圍。 除此之外，因為設置了下沈層302η及第二埋入層2〇8η， 細上所述，本發明可以避免互補式金氧半場效電晶體 的閂鎖現象、增加輸入電壓的容許範圍，並與基底上其他 的半導體元件被有效地隔離。另外，因為 的可用面積的極小部分，且埋人層是位於;底 所以能夠壯S積缝的要求。 “件之下 雖然本㈣已以難實關揭露如上，财並非用以 H發'任何熟f此技藝者’在不脫離本發明之精神 2圍内’ t可作些許之更動與潤飾，因此本發明之保護 轨圍當視後附之申請專利範圍所界定者為準。 ’、 【圖式簡單說明】 圖1是習知的一種高壓元件的剖面示意圖。 15 1352428 01-2005-004 19509twf.doc/006 圖2是本發明第一實施例的一種半導體元件的叫面示 • 意圖。 -· 圖3是本發明第二實施例的一種互補式金氧半場效電 晶體的剖面示意圖。 【主要元件符號說明】 100 :P型基底 102、104、220、306 :閘極 106、108、222、308 :閘介電層 • 112p:P井 114P : P槽 116ρ、118ρ、120ρ、126η、128η、130η、226ρ、228η、 230η、232η、310η、312ρ、314ρ、316ρ :摻雜區 122η、124η : Ν 槽 134、210 :隔離結構 136、140、212 :介電層 138、234、236、238、240、318、320、322、324 : φ 内連線 200 :基底 202η :遙晶層 204η、302η :下沈層 206ρ:第一埋入層 208η :第二埋入層 214ρ、218ρ :井區 215ρ :第三埋入層 1352428 01-2005-004 19509twf.doc/006 216p :埋入層 A1 :主動元件 A2 :第二電晶體 HVNMOS、HVPMOS、IU、R2 :區域By adjusting the potentials of the interconnects 240 and 324, the current gain described above can be varied to further avoid latch-up. On the other hand, the voltage applied to the second transistor A2 can have a larger range. For example, if a high input voltage is applied to the interconnect 320, the potential of the interconnect 324 can be adjusted. Therefore, the above input voltage can be directly applied to the interconnect 324. The monthly b is sufficient to prevent the input voltage from being directly applied to the input voltage. The substrate 2 is further configured to further prevent electrical breakdown of the interface between the epitaxial layer 202n and the substrate 200. Therefore, the voltage applied to the line 320 can have a larger allowable range. It will be apparent that the voltage applied to interconnect 318 may also have a greater tolerance. In addition, since the sinking layer 302n and the second buried layer 2〇8η are provided, as described above, the present invention can avoid the latch-up phenomenon of the complementary metal oxide half field effect transistor and increase the allowable range of the input voltage. And is effectively isolated from other semiconductor components on the substrate. In addition, because of the very small portion of the available area, and the buried layer is located; "Under the article, although this (4) has been exposed in such a difficult manner as above, the money is not used to make a 'change of the skill of the artist', and can make some changes and refinements without departing from the spirit of the present invention. The protective rail of the present invention is defined by the scope of the appended claims. ', BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view of a conventional high voltage component. 15 1352428 01-2005-004 19509twf. Doc/006 Fig. 2 is a schematic illustration of a semiconductor device according to a first embodiment of the present invention. Fig. 3 is a cross-sectional view showing a complementary MOS field effect transistor according to a second embodiment of the present invention. Element Symbol Description] 100: P-type substrate 102, 104, 220, 306: gate 106, 108, 222, 308: gate dielectric layer • 112p: P well 114P: P-channel 116ρ, 118ρ, 120ρ, 126η, 128η, 130η, 226ρ, 228η, 230η, 232η, 310η, 312ρ, 314ρ, 316ρ: doped regions 122n, 124n: 槽 grooves 134, 210: isolation structures 136, 140, 212: dielectric layers 138, 234, 236, 238, 240, 318, 320, 322, 324: φ interconnect 200: substrate 202η: remote crystal Layers 204n, 302n: sink layer 206p: first buried layer 208n: second buried layer 214p, 218p: well region 215p: third buried layer 1352428 01-2005-004 19509twf.doc/006 216p: buried Layer A1: Active component A2: Second transistor HVNMOS, HVPMOS, IU, R2: Region
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