CN101431102B - Semiconductor device with high-breakdown-voltage transistor - Google Patents

Semiconductor device with high-breakdown-voltage transistor Download PDF

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Publication number
CN101431102B
CN101431102B CN 200810170454 CN200810170454A CN101431102B CN 101431102 B CN101431102 B CN 101431102B CN 200810170454 CN200810170454 CN 200810170454 CN 200810170454 A CN200810170454 A CN 200810170454A CN 101431102 B CN101431102 B CN 101431102B
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China
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semiconductor layer
wiring
layer
circuit part
semiconductor device
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CN101431102A (en
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山田明
赤木望
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring.

Description

Semiconductor device with high breakdown transistor
The present invention relates to a kind of semiconductor device with high breakdown transistor, the height that particularly is used for level shift punctures mos field effect transistor.
Usually, the someone has proposed high voltage integrated circuit (HVIC), and it has realized not using the level shift circuit of photoelectrical coupler.For example, this HVIC comprises the metal oxide semiconductor transistor (LDMOS) of the high-breakdown-voltage horizontal proliferation that is used for level shift.As disclosed, for example, in the US2006/0249807 of corresponding JP-A-2006-313828, in high-breakdown-voltage LDMOS, the drain region is positioned at the center, and the source region be positioned at the drain region periphery around.Like this, the source region is with respect to drain region (concentrically) setting with one heart, so that eliminate a single point.In this scheme, electric current flows almost evenly, thereby LDMOS can have high-breakdown-voltage.
Figure 16 is the cross-sectional view that this LDMOS is shown.N type well region J2 and n +Type contact zone J3 is formed on n -Among the type drift layer J1.N type well region J2 and n +Type contact zone J3 constitutes the drain region.P type channel region J4 and n +Type source region J5 be formed on the drain region around.Drain electrode wiring J6 is formed on n +On the surface of type contact zone J3.Source wiring J7 is formed on n +On the surface of type source region J5.Because the drain region is by n +Type source region J5 surrounds, and in the time of therefore outside being pulled to source wiring J7, drain electrode wiring J6 passes the top of source wiring J7.
Interlayer dielectric J8 places between drain electrode wiring J6 and the source wiring J7, is used for the electric insulation between drain electrode wiring J6 and the source wiring J7.Generally, be used for the high-breakdown-voltage LDMOS of level shift, the current potential of 0V put on source wiring J7, and the current potential from about 600V to about 1200V is put on drain electrode wiring J6.That is, will voltage put on the interlayer dielectric J8 drain electrode wiring J6 and source wiring J7 from about 600V to about 1200V.Therefore, the thickness of interlayer dielectric J8 must be enough big so that prevent the puncture of interlayer dielectric J8.Yet forming the interlayer dielectric with big thickness needs long time.
Figure 17 is the schematic diagram that the Potential distribution among the LDMOS is shown.As can be seen from Figure 17, at n -Among the type drift layer J1, Potential distribution is uniform around n type well region J2.Yet, interlayer dielectric J8 below being arranged in drain electrode wiring J6 and LOCOS oxidation film J9, Potential distribution is heterogeneous.Potential distribution heterogeneous shows because the high potential of drain electrode wiring J6 has produced electric field concentrates.This electric field is concentrated the puncture that may cause interlayer dielectric J8 and LOCOS oxidation film J9.
The problems referred to above also may appear in the high breakdown transistor of other types, for example igbt (IGBT) and bipolar transistor.
In view of the above problems, the purpose of this invention is to provide the semiconductor device that a kind of thickness that does not increase dielectric film has just been realized high breakdown transistor.
According to first scheme of the present invention, semiconductor device comprises the high breakdown transistor of the semiconductor layer with predetermined conductivity type.Semiconductor layer has by groove componentry and wiring portion electrically isolated from one.Componentry has in first wiring part on the front of semiconductor layer and the backplate on the back side at semiconductor layer.Componentry constitutes vertical transistor, and this vertical transistor is flowing electric current on the thickness direction of this semiconductor layer, between first wiring part and backplate.Backplate is elongated to wiring portion from componentry.Wiring portion has in second wiring part on the front of semiconductor layer and the backplate on the back side at semiconductor layer.Wiring portion constitutes the backguy (pulling wire) that allows electric current to flow between electrode and second wiring part overleaf.
According to alternative plan of the present invention, semiconductor device comprises high breakdown transistor, dielectric film and backplate.High breakdown transistor has the semiconductor layer of first conduction type.This semiconductor layer has by first groove componentry and wiring portion electrically isolated from one.Dielectric film is formed on the front of semiconductor layer, and has first and second contact holes.Backplate is formed on the back side of semiconductor layer.The componentry of high breakdown transistor comprises the drain contact district of semiconductor region, gate insulating film, gate electrode, first wiring part and first conduction type of channel layer, first conduction type of second conduction type.Channel layer is formed into semiconductor layer and is exposed to first of semiconductor layer.Semiconductor region is formed in the channel layer, and has the impurity concentration that is higher than semiconductor layer.Gate insulating film is formed on the exposing surface of channel layer between semiconductor region and the semiconductor layer.Gate electrode is formed on the gate insulating film.First wiring part is electrically coupled on each of contact zone of semiconductor region and channel layer.The drain contact district is formed on the back side of semiconductor layer and has the impurity concentration that is higher than semiconductor layer.The wiring portion of high breakdown transistor comprises first contact zone, second contact zone and second wiring part.First contact zone is formed on the front of semiconductor layer.Second contact zone is formed on the back side of semiconductor layer.Second wiring part is electrically coupled to first contact zone.The drain contact district of componentry is electrically coupled to second contact zone of wiring portion by backplate.First contact hole of first wiring part by first dielectric film is electrically coupled on each of channel region of semiconductor region and channel layer.Second wiring part is electrically coupled to first contact zone of wiring portion by second contact hole of first dielectric film.
According to third party's case of the present invention, semiconductor device comprises low voltage circuit part, high voltage circuit part, high breakdown transistor and power-supply wiring.High breakdown transistor constitutes between low voltage circuit part and high voltage circuit part and carries out power transfer.High breakdown transistor has the semiconductor layer of predetermined conductivity type.This semiconductor layer has the componentry of being isolated by the groove electricity.Power-supply wiring is formed on first of semiconductor layer and goes up and constitute to high voltage circuit and partly apply voltage.Componentry has the lead frame on the wiring part on the front of semiconductor layer and the back side at semiconductor layer.Componentry constitutes vertical transistor, and this vertical transistor is flowing electric current between wiring part and lead frame on the thickness direction of semiconductor layer.Lead frame has from the outstanding projection in the edge at the back side of semiconductor layer.The projection of lead frame is electrically coupled to power-supply wiring by bonding line.
According to cubic case of the present invention, semiconductor device comprises low voltage circuit part, high voltage circuit part, high breakdown transistor and power-supply wiring.High breakdown transistor constitutes between low voltage circuit part and high voltage circuit part and carries out power transfer.High breakdown transistor has the semiconductor layer of first conduction type.This semiconductor layer has the componentry of being isolated by the groove electricity.Power-supply wiring is formed on first of semiconductor layer and goes up and constitute to high voltage circuit and partly apply voltage.The componentry of high breakdown transistor comprises semiconductor region, gate insulating film, gate electrode, the wiring part of channel layer, first conduction type of second conduction type, the drain contact district and the lead frame of first conduction type.Channel layer is formed on the semiconductor layer and is exposed to first of semiconductor layer.Semiconductor region is formed in the channel layer and has the impurity concentration that is higher than semiconductor layer.Gate insulating film is formed on the exposing surface of channel layer between semiconductor region and the semiconductor layer.Gate electrode is formed on the gate insulating film.Wiring part is electrically coupled on each of contact zone of semiconductor region and channel layer.The drain contact district is formed on the back side of semiconductor layer and has the impurity concentration that is higher than semiconductor layer.Lead frame is formed on the back side of semiconductor layer and is electrically coupled to the drain contact district.Componentry constitutes vertical transistor, and this vertical transistor is flowing electric current between wiring part and lead frame on the thickness direction of semiconductor layer.Lead frame has from the outstanding projection in the edge at the back side of semiconductor layer.The projection of lead frame is electrically coupled to power-supply wiring by bonding line.
Above-mentioned and other purposes, feature and advantage of the present invention will more obviously from detailed description with reference to the accompanying drawings be found out.In the accompanying drawing:
Fig. 1 is the profile that illustrates according to the semiconductor device of first embodiment of the invention;
Fig. 2 is the front view that the semiconductor device of Fig. 1 is shown;
Fig. 3 is the schematic diagram that the Potential distribution in the semiconductor device of Fig. 1 is shown;
Fig. 4 A is the schematic diagram of first technology that the semiconductor device of shop drawings 1 is shown, and Fig. 4 B is the schematic diagram of second technology that the semiconductor device of shop drawings 1 is shown, and Fig. 4 C is the schematic diagram of the 3rd technology that the semiconductor device of shop drawings 1 is shown;
Fig. 5 A is the schematic diagram of the 4th technology that the semiconductor device of shop drawings 1 is shown, and Fig. 5 B is the schematic diagram of the 5th technology that the semiconductor device of shop drawings 1 is shown, and Fig. 5 C is the schematic diagram of the 6th technology that the semiconductor device of shop drawings 1 is shown;
Fig. 6 A is the schematic diagram of the 7th technology that the semiconductor device of shop drawings 1 is shown, and Fig. 6 B is the schematic diagram of the 8th technology that the semiconductor device of shop drawings 1 is shown, and Fig. 6 C is the schematic diagram of the 9th technology that the semiconductor device of shop drawings 1 is shown;
Fig. 7 is the profile that illustrates according to the semiconductor device of second embodiment of the invention;
Fig. 8 is the profile that illustrates according to the semiconductor device of third embodiment of the invention;
Fig. 9 is the front view that the semiconductor device of Fig. 8 is shown;
Figure 10 is the profile that illustrates according to the semiconductor device of fourth embodiment of the invention;
Figure 11 is the front view that the semiconductor device of Figure 10 is shown;
Figure 12 is the profile that illustrates according to the semiconductor device of fifth embodiment of the invention;
Figure 13 is the profile that illustrates according to the semiconductor device of sixth embodiment of the invention;
Figure 14 is the profile that illustrates according to the semiconductor device of seventh embodiment of the invention;
Figure 15 is the profile that illustrates according to the semiconductor device of eighth embodiment of the invention;
Figure 16 is the profile that conventional semiconductor device is shown; And
Figure 17 is the figure that the Potential distribution in the semiconductor device of Figure 16 is shown.
(first embodiment)
Below with reference to the semiconductor device of Fig. 1 and 2 introduction according to first embodiment of the invention.Fig. 1 is the profile that semiconductor chip is shown, and this semiconductor device is formed into this semiconductor chip.This semiconductor chip have front (Fig. 1's is top) and with positive opposing backside surface (Fig. 1's is following).Fig. 2 is the front view that semiconductor chip is shown.
This semiconductor device comprises low-voltage (LV) circuit part 1 and high voltage (HV) circuit part 2.LV circuit part 1 provides zero volt reference circuit.HV circuit part 2 provides for example 600 to 1200 volts of reference circuits.This semiconductor device can be used to drive for example igbt (IGBT), and it is not shown in the drawings.
This semiconductor device has the high-breakdown-voltage laterally diffused MOS FET3 that is used for level shift (being power transfer).MOSFET3 is arranged to stride across the border between LV circuit part 1 and the HV circuit part 2, thereby carries out level shift betwixt.This semiconductor device has the drive circuit part (not shown) that is used to drive IGBT.For example, this drive circuit part can comprise power MOSFET, bipolar transistor, complementary metal oxide semiconductors (CMOS) (CMOS) and/or analog.
N at this semiconductor device -Form groove 5-7 in the type drift layer 4 (as first conductive type layer).n - Type drift layer 4 have front (Fig. 1's is top) and with positive opposing backside surface (Fig. 1's is following).Each groove 5-7 is from n -N is passed to the back side in the front of type drift layer 4 -Type drift layer 4.Each groove 5-7 fills with insulating barrier, and this insulating barrier is for example made by heat oxide film and polysilicon film.Groove 5 surrounds LV circuit part 1 and HV circuit part 2.Groove 6 surrounds HV circuit part 2.Like this, realized trench isolations, thereby can make LV circuit part 1 and HV circuit part 2 electrically isolated from one and physical isolation by groove 6.
Groove 7 surrounds the part of LV circuit part 1 and the part of HV circuit part 2.MOSFET3 is formed on by in groove 7 area surrounded.The groove 6 of being isolated LV circuit part 1 and HV circuit part 2 by groove 7 area surrounded is divided into two.Correspondingly, MOSFET3 is divided into two by groove 6, and one is defined as componentry, and another is defined as wiring portion 9.
In the componentry 8 of MOSFET3, at n -Form p type channel region 10 on the surface portion in the front of type drift layer 4.n +Type source region 11 (as the first conductive type semiconductor district) and p + Type contact zone 12 is formed in the p type channel region 10.n + Type source region 11 has the n of being higher than -The n type impurity concentration of type drift layer 4.p + Type contact zone 12 has the p type impurity concentration that is higher than p type channel region 10.In addition, n +Type drain contact district 13 is formed into n -The surface portion at the back side of type drift layer 4.n +Type drain contact district 13 has the n of being higher than -The n type impurity concentration of type drift layer 4.
LOCOS (local oxidation of silicon) oxidation film 14 is formed into n -On the surface in the front of type drift layer 4.LOCOS film 14 has opening, exposes p type channel region 10, n at this opening part + Type source region 11 and p +Type contact zone 12.At n - Type drift layer 4 and n + Form gate electrode 16 by gate insulating film 15 on the exposing surface of the p type channel region 10 between the type source region 11.In addition, interlayer dielectric 17 is formed on n -On the surface in the front of type drift layer 4.Gate electrode 16, gate insulating film 15 and LOCOS oxidation film 14 usefulness interlayer dielectrics 17 cover.Interlayer dielectric 17 has contact hole.Source wiring 18 is formed on n -On the surface in the front of type drift layer 4.Source wiring 18 is passed the contact hole and and the n of interlayer dielectric 17 + Type source region 11 and p +Each ohmic contact of type contact zone 12.Source wiring 18 for example can be made of aluminium.Source wiring 18 is extended to LV circuit part 1 one sides along the surface of interlayer dielectric 17.That is, source wiring 18 is extended on the direction away from HV circuit part 2.
In addition, backplate 19 is formed into n -On the surface at the back side of type drift layer 4.Backplate 19 and n +Type drain contact district 13 ohmic contact.For example, backplate 19 can be made of aluminum and be had the thickness of about 1 micron (μ m).Backplate 19 in by groove 7 area surrounded to prevent backplate 19 and by short circuit between the part of the LV circuit part 1 of groove 7 area surrounded outsides.
In the wiring portion 9 of MOSFET3, n type well region 20 is formed into n -On the surface portion in the front of type drift layer 4.n + Type contact zone 21 is formed on the surface portion of n type well region 20.n + Type contact zone 22 is formed into n -On the surface portion at the back side of type drift layer 4.In addition, interlayer dielectric 17 is formed on n -On the surface in the front of type drift layer 4.Interlayer dielectric 17 has contact hole.Drain electrode wiring 23 is formed on n -On the surface in the front of type drift layer 4.Drain electrode wiring 23 passes the contact zone and and the n of interlayer dielectric 17 + Type contact zone 21 ohmic contact.Drain electrode wiring 23 for example can be made of aluminum.Drain electrode wiring 23 extends to HV circuit part 2 one sides along the surface of interlayer dielectric 17.That is, drain electrode wiring 23 extends on the direction away from LV circuit part 1.In this way, source wiring 18 and drain electrode wiring 23 extend in the opposite direction.
The backplate 19 that is formed in the componentry 8 extends to wiring portion 9 and and n + Type contact zone 22 ohmic contact.As previously mentioned, backplate 19 is arranged in by groove 7 area surrounded.Therefore, can prevent backplate 19 and being short-circuited between the part of the HV circuit part 1 beyond groove 7 area surrounded.
If necessary, form interlayer dielectric 24, to cover the whole front of semiconductor device.This semiconductor device can also increase other wiring layer (not shown).On the front and back of semiconductor device, form diaphragm 25,26 respectively.Semiconductor device according to first embodiment constitutes by the way.
This semiconductor device is operated in the following manner.When predetermined voltage puts on gate electrode 16, produce raceway groove in the surface portion of the p type channel region 10 below being located immediately at gate insulating film 15.As a result, electric current passes through n +The raceway groove that produces in type source region 11, the p type channel region 10, the n of componentry 8 - Type drift layer 4, n +Type drain contact district 13, backplate 19, n +The n of type contact zone 22, wiring portion 9 - Type drift layer 4, n type well region 20 and n + Type contact zone 21 flows between source wiring 18 and drain electrode wiring 23.When electric current flowed, the current potential of each part of semiconductor device changed according to the operating condition of the IGBT that is driven by this semiconductor device.For example, in first embodiment, the current potential that 0 volt current potential puts on 18,600 to 1200 volts of source wiring puts on drain electrode wiring 23.As a result, from 600 to 1200 volts high voltage puts on source wiring 18 and the drain electrode wiring 23.
According to the semiconductor device of first embodiment because following former thereby can bear high voltage.In the componentry 8 of MOSFET3, backplate 19 is formed on n -On the back side of type drift layer 4.Electric current is from being formed on n -Source wiring 18 on the front of type drift layer 4 flows to backplate 19.That is, electric current is at n -On the thickness direction of type drift layer 4 from n -The front of type drift layer 4 flows to the back side.
Backplate 19 extends to wiring portion 9 and through n from componentry 8 +The n of type contact zone 22, wiring portion 9 - Type drift layer 4, n type well region 20 and n + Type contact zone 21 is coupled to drain electrode wiring 23.That is, use backplate 19 and wiring portion 9 drain electrode wiring 23 to be pulled out to the outside of componentry 8.In this way, backplate 19 and wiring portion 9 provide and allow electric current to flow to the backguy of drain electrode wiring 23.
In this scheme, drain electrode wiring 23 does not pass above source wiring 18, and interlayer dielectric 17 is not between source wiring 18 and drain electrode wiring 23.Therefore, even the voltage between source wiring 18 and the drain electrode wiring 23 (being potential difference) is very big, also can prevent because this voltage causes the puncture of interlayer dielectric 17.
In addition, electric current is at n -Between source wiring 18 and backplate 19, flow on the thickness direction of type drift layer 4.Therefore, can prevent owing to the concentrated LOCOS oxidation film 14 that causes of electric field and the puncture of interlayer dielectric 17, thereby this semiconductor device can have high-breakdown-voltage.Specifically, as shown in Figure 3, the Potential distribution in the componentry 8 of MOSFET3 is uniformly basically and is parallel to n -The surface of type drift layer 4.Therefore, prevented that electric field is concentrated, thereby this semiconductor device can have high-breakdown-voltage.
Introduce the method for making this semiconductor device (particularly MOSFET3) below with reference to Fig. 4 A-6C.
At first, shown in Fig. 4 A, preparation is used for n -The silicon substrate 30 of type drift layer 4.Silicon substrate 30 has the thickness greater than the degree of depth of each groove 5-7.
Then, shown in Fig. 4 B, silicon substrate 30, form groove 31 from the front of silicon substrate 30 by photoetching process and etching technics.Then, on the inner surface of groove 31, form oxidation film by thermal oxidation technology.Then, on this oxidation film, form polysilicon (poly-Si) layer.Like this, use insulating barrier 32 filling grooves 31 that constitute by oxidation film and polysilicon layer.Then, remove oxidation film and polysilicon layer on the front of staying silicon substrate, thereby insulating barrier 32 can only be retained in groove 31 inside.
Then, shown in Fig. 4 C, on the front of silicon substrate 30, form LOCOS oxidation film 14.Specifically, on the front of silicon substrate 30, form the basic unit's (not shown) that for example constitutes, form opening for this basic unit by composition technology then by oxidation film and nitride film.Subsequently, apply LOCOS technology, thereby in this opening, can form LOCOS oxidation film 14 to this basic unit.Then, remove basic unit, thereby LOCOS oxidation film 14 can be stayed on first front of silicon substrate 30.
Then, shown in Fig. 5 A, p type channel region 10 and n type well region 20 are formed into the surface portion in the front of silicon substrate 30.Specifically, place first mask on the front of silicon substrate 30 and LOCOS oxidation film 14, this first mask has the opening of corresponding p type channel region 10.Then, utilize ion implantation technology p type impurity to be injected in the silicon substrate 30 by first mask.Then, remove first mask, and on the front of silicon substrate 30 and LOCOS oxidation film 14, place second mask of opening with corresponding n type well region 20.Then, utilize ion implantation technology n type impurity to be injected in the silicon substrate 30 by second mask.Then, make the diffusion of impurities of injection, thereby p type channel region 10 and n type well region 20 can be formed into the surface portion in the front of silicon substrate 30 by Technology for Heating Processing.
In addition, on the front of silicon substrate 30 and LOCOS oxidation film 14, place and have corresponding to n + Type source region 11 and n +The 3rd mask of the opening of type contact zone 21.Then, utilize ion implantation technology n type impurity to be injected in the silicon substrate 30 by the 3rd mask.Then, remove the 3rd mask, and on the front of silicon substrate 30 and LOCOS oxidation film 14, be provided with and have corresponding p +The 4th mask of the opening of type contact zone 12.Then, utilize ion implantation technology p type impurity to be injected in the silicon substrate 30 by the 4th mask.Then, make the diffusion of impurities of injection by Technology for Heating Processing, thus can be with n + Type source region 11, n + Type contact zone 21 and p + Type contact zone 12 is formed into the surface portion in the front of silicon substrate 30.
Then, shown in Fig. 5 B, form gate insulating film 15 by thermal oxidation technology.Then, on dielectric film 15, form the polysilicon layer that has been doped impurity.Then, by this polysilicon layer is carried out composition, form gate electrode 16.
Then, shown in Fig. 5 C, interlayer dielectric 17 is set on the front of silicon substrate 30, thereby can covers the front and the gate electrode 16 of silicon substrate 30 fully with interlayer dielectric 17.Interlayer dielectric 17 is carried out composition, expose n thereby form + Type source region 11 and p +First contact hole of type contact zone 12 and expose n +Second contact hole of type contact zone 21.
Then, as shown in Figure 6A, form source wiring 18 and drain electrode wiring 23.Specifically, on interlayer dielectric 17, form the wiring layer that for example constitutes, thereby can fill the contact hole of interlayer dielectric 17 with this wiring layer by aluminium.Then, form source wiring 18 and drain electrode wiring 23 by this wiring layer being carried out composition.If necessary, on source wiring 18 and drain electrode wiring 23, form interlayer dielectric 24 and additional wiring layer.
Then, shown in Fig. 6 B, for example utilize chemico-mechanical polishing (CMP) technology,, silicon substrate 30 is thinned to predetermined thickness by the back side of polished silicon substrate 30.Therefore, finished n - Type drift layer 4, and groove 5-7 penetrates n - Type drift layer 4, thus can realize trench isolations.
Then, shown in Fig. 6 C, at n -The 5th mask is set on the back side of type drift layer 4, and the 5th mask has corresponding n +Type drain contact district 13 and n +The opening of type contact zone 22.Then, utilize ion implantation technology n type impurity to be injected into n by the 5th mask -Type drift layer 4.Then, make the diffusion of impurities of injection by Technology for Heating Processing, thus can be with n +Type drain contact district 13 and n + Type contact zone 22 is formed into n -The surface portion at the back side of type drift layer 4.Then, at n -The back side of type drift layer 4, n +Type drain contact district 13 and n +Form the electrode layer that for example constitutes on the type contact zone 22 by aluminium.Then, form backplate 19 by electrode layer being carried out composition.
At last, on interlayer dielectric 24, form diaphragm 25, and at n -Form diaphragm 26 on the back side of type drift layer 4 and the backplate 19.In this way, can make semiconductor device according to first embodiment.
As mentioned above, according to the semiconductor device of first embodiment, owing to drain electrode wiring 23 does not pass above source wiring 18, so interlayer dielectric 17 is not between source wiring 18 and drain electrode wiring 23.Therefore, even the potential difference between source wiring 18 and the drain electrode wiring 23 is very big, also can not cause the puncture of interlayer dielectric 17 owing to potential difference.
(second embodiment)
Below with reference to the semiconductor device of Fig. 7 introduction according to second embodiment of the invention.The difference of first and second embodiment is as follows.
Fig. 7 is the profile that the semiconductor chip that wherein is formed with this semiconductor device is shown.In a second embodiment, at n -The surface at the back side of type drift layer 4 forms the interlayer dielectric 40 with contact hole.Backplate 19 is coupled to n by each contact hole +Type drain contact district 13 and n + Type contact zone 22.
As mentioned above, according to second embodiment, at n -Form interlayer dielectric 40 on the back side of type drift layer 4.Through interlayer dielectric 40 at n -Form backplate 19 on the back side of type drift layer 4.In this scheme,, also can prevent because backplate 19 causes the short circuit between LV circuit part 1 and the HV circuit part 2 by interlayer dielectric 40 even make backplate 19 spread to the outside of groove 7 owing to making change.
(the 3rd embodiment)
Below with reference to Fig. 8 and 9 semiconductor device of introducing according to third embodiment of the invention.Difference between the first and the 3rd embodiment is as follows.
Fig. 8 is the profile that the semiconductor chip that has formed this semiconductor device is shown.Fig. 9 is the schematic diagram of front view that the semiconductor chip of Fig. 8 is shown.
In the 3rd embodiment, surround HV circuit part 2 by a plurality of (promptly four) groove 6.A plurality of grooves 6 provide the improved isolation between LV circuit part 1 and the HV circuit part 2, thereby this semiconductor device can have high-breakdown-voltage.
In addition, MOSFET3 is surrounded by a plurality of (promptly four) groove 7.As seen from Figure 9, groove 7 is not formed in the zone between the adjacent trenches 6.Perhaps, also can in the zone between the adjacent trenches 6, form groove 7.
(the 4th embodiment)
Introduce the semiconductor device of a fourth embodiment in accordance with the invention below with reference to Figure 10 and 11.Difference between the first and the 4th embodiment is as follows.
Figure 10 is the profile that the semiconductor chip that has formed this semiconductor device is shown.Figure 11 is the schematic diagram of front view that the semiconductor chip of Figure 10 is shown.
In the 4th embodiment, use lead frame 50 to replace backplate 19.Lead frame 50 is positioned at n -On the back side of type drift layer 4.Specifically, lead frame 50 is bonded to n +Type drain contact district 13 and be formed on n -On the lip-deep dielectric film 51 at the back side of type drift layer 4.
In the 4th embodiment, there is not wiring portion 9.The edge that lead frame 50 has from semiconductor chip (is n -The edge of type drift layer 4) outstanding projection.The projection of lead frame 50 is coupled on the pad portion of power-supply wiring 52 by bonding line 53.Power-supply wiring 52 is used for voltage is put on HV circuit part 2.The pad portion of power-supply wiring 52 is exposed to the outside of interlayer dielectric 24 and diaphragm 25, thus by bonding line 53 can with power-supply wiring 52 with lead frame 50 electric coupling be in the same place.That is, use lead frame 50 and bonding line 53 outside with power-supply wiring 52 pull-out elements districts 8.In this way, lead frame 50 and bonding line 53 provide backguy, and it allows electric current to flow to power-supply wiring 52.
Dielectric film 51 provides the n of lead frame 50 with LV circuit part 1 and HV circuit part 2 -Electricity between the type drift layer 4 is isolated.In other words, dielectric film 51 prevents n +Type drain contact district 13 is by the n of lead frame 50 to LV circuit part 1 and HV circuit part 2 - Type drift layer 4 is short-circuited.
For example, lead frame 50 can be arranged on n in such a way -The back side of type drift layer 4.At first, remove the n of LV circuit part 1 and HV circuit part 2 -The predetermined thickness at the back side of type drift layer 4 is arranged on n with dielectric film 51 then -On the back side of type drift layer 4.Then, for example by cmp method polishing dielectric film 51, up to exposing n +Till the type drain contact district 13.Then, lead frame 50 is bonded to n +Type drain contact district 13 and dielectric film 51.Like this, just lead frame 50 is arranged on n -On the back side of type drift layer 4.
In addition, as the 3rd embodiment, surround HV circuit part 2, and surround MOSFET3 (that is, componentry 8) with a plurality of (that is, three) groove 7 with a plurality of (that is, three) groove 6.
As mentioned above, according to the 4th embodiment, lead frame 50 is arranged on n -On the back side of type drift layer 4.The front of using bonding line 53 lead frame 50 to be moved to semiconductor chip.Like this, lead frame 50 and bonding line 53 are used as wiring portion 9.
(the 5th embodiment)
Below with reference to the semiconductor device of Figure 12 introduction according to fifth embodiment of the invention.Difference between the first and the 5th embodiment is as follows.
Figure 12 is the profile that the semiconductor chip that has formed this semiconductor device is shown.
In the 5th embodiment, this semiconductor chip has through hole 61a, 61b in its front.Through hole 61a arrives backplate 19.Through hole 61b arrives the n of HV circuit part 2 -Type drift layer 4.Backplate 19 and n -Bonding line 60 electric coupling of type drift layer 4 through passing through hole 61a, 61b together.
As mentioned above, according to the 5th embodiment, this semiconductor chip has through hole 61a, 61b, and bonding line 60 passes through hole 61a, 61b.The n of backplate 19 and HV circuit part 2 - Type drift layer 4 by bonding line 60 electric coupling together.Like this, bonding line 60 is constituted as the part of wiring portion 9.
(the 6th embodiment)
Below with reference to the semiconductor device of Figure 13 introduction according to sixth embodiment of the invention.Difference between the first and the 6th embodiment is as follows.
Figure 13 is the profile that the semiconductor chip that has formed this semiconductor device is shown.
In the 6th embodiment, conductive component 70 is formed on n -Penetrate this n to the back side in the type drift layer 4 and from first -Type drift layer 4.Conductive component 70 at one end is exposed to n -First surface of type drift layer 4, and be electrically coupled to drain electrode wiring 23.In addition, conductive component 70 is exposed to n at the other end -The surface at the back side of type drift layer 4, and be electrically coupled to backplate 19.For example, conductive component 70 can be formed on n by filling with low electrical resistant material such as metal, doped polycrystalline silicon and/or other analog -Via hole 71 in the type drift layer 4 forms.
As mentioned above, according to the 6th embodiment, be formed on n -Conductive component 70 in the type drift layer 4 is constituted as the part of wiring portion 9.
(the 7th embodiment)
Below with reference to the semiconductor device of Figure 14 introduction according to seventh embodiment of the invention.Difference between the first and the 7th embodiment is as follows.
Figure 14 is the profile that the semiconductor chip that has formed this semiconductor device is shown.
In the 7th embodiment, with the n of n type impurity (or p type impurity) high doped wiring portion 9 - Type drift layer 4, thus doped silicon layer 80 formed.Backplate 19 is in the same place by doped silicon layer 80 electric coupling with drain electrode wiring 23.
As mentioned above, according to the 7th embodiment, doped silicon layer 80 is constituted as the part of wiring portion 9.
(the 8th embodiment)
Below with reference to the semiconductor device of Figure 15 introduction according to eighth embodiment of the invention.Difference between the first and the 8th embodiment is as follows.
Figure 15 is the profile that the semiconductor chip that has formed this semiconductor device is shown.
In the 8th embodiment, conductive component 91 passes through n -Dielectric film 90 in the type drift layer 4 forms and penetrates n from first to the back side -Type drift layer 4.Conductive component 70 at one end is exposed to n -First surface of type drift layer 4, and be electrically coupled to drain electrode wiring 23.In addition, conductive component 70 is exposed to n at the other end -The surface at the back side of type drift layer 4, and be electrically coupled to backplate 19.For example, this structure can be made in such a way.At first, at n -Form via hole 92 in the type drift layer 4, on the inwall of via hole 92, form dielectric film 90 then.At last, with low electrical resistant material such as metal, doped polycrystalline silicon and/or analog filling vias hole 92.
As mentioned above, according to the 8th embodiment, be constituted as the part of wiring portion 9 by the conductive component 91 of 90 formation of the dielectric film in the n-type drift layer 4.
(modification)
Can make amendment to the foregoing description in various manners.For example, groove 5 can only surround LV circuit part 1, thereby LV circuit part 1 and HV circuit part 2 can be surrounded by groove 5,6 respectively.
In third and fourth embodiment, the quantity of a plurality of grooves 6,7 can change according to required puncture voltage.
In first, second and the 3rd embodiment, can eliminate and reduce n -The n type well region 20 of the internal resistance of type drift layer 4.
Although the MOSFET3 among these embodiment is the n channel-type, MOSFET3 also can be the p channel mosfet.
MOSFET3 can replace with vertical MOSFET such as planar MOSFET (for example disclosed in JP-A-H11-238742), trench gate mosfet (for example disclosed in the US2004/0173845 of corresponding JP-A-2004-266140) or matrix (concave) MOSFET (for example disclosed in the US5877527 of corresponding JP-A-H09-293861) of other types.
MOSFET3 can replace with the transistor of other types such as bipolar transistor or IGBT (igbt).In this case, the emitter of bipolar transistor or the IGBT corresponding source wiring 18 that connects up, the collector electrode of bipolar transistor or the IGBT corresponding drain electrode wiring 23 that connects up.
These change and modification should be understood that to belong in the scope of the present invention that is limited by appended claims.

Claims (15)

1. semiconductor device comprises:
High breakdown transistor (3), it comprises the semiconductor layer (4) of predetermined conductivity type, and this semiconductor layer (4) has reciprocal front and back, and this semiconductor layer (4) comprises by groove componentry electrically isolated from one (8) and wiring portion (9),
Wherein this componentry (8) has in first wiring part (18) on the front of this semiconductor layer (4) and the backplate on the back side of this semiconductor layer (4) (19), this componentry (8) constitutes vertical transistor, it makes electric current flow between this first wiring part (18) and this backplate (19) on the thickness direction of this semiconductor layer (4)
Wherein this backplate (19) extends to this wiring portion (9) from this componentry (8), and
Wherein this wiring portion (9) has in second wiring part (23) on the front of this semiconductor layer (4) and this backplate (19) on the back side of this semiconductor layer (4), and this wiring portion (9) constitutes the backguy that allows electric current to flow between this backplate (19) and this second wiring part (23).
2. semiconductor device according to claim 1,
Wherein said wiring portion (9) also has the bonding line (60) that described semiconductor layer (4) is electrically coupled to described backplate (19).
3. semiconductor device according to claim 1,
Wherein said wiring portion (9) also has the conductive component (70) that is arranged in the via hole (71) that is formed in the described semiconductor layer (4), and
Wherein said conductive component (70) is electrically coupled to described second wiring part (23) with described backplate (19).
4. semiconductor device according to claim 1,
Wherein said wiring portion (9) also has doped layer (80), and the impurity concentration of this doped layer (80) is higher than the impurity concentration of described semiconductor layer (4), and
Wherein said doped layer (80) is electrically coupled to described second wiring part (23) with described backplate (19).
5. semiconductor device according to claim 1,
Wherein said wiring portion (9) also has the conductive component (91) that is provided with by the dielectric film (90) that is formed in the via hole (92) in the described semiconductor layer (4), and
Wherein this conductive component (91) is electrically coupled to described second wiring part (23) with described backplate (19).
6. according to each described semiconductor device in the claim 1-5, also comprise:
Low voltage circuit part (1); With
High voltage circuit part (2),
Wherein said high breakdown transistor (3) is constituted as between described low voltage circuit part (1) and described high voltage circuit part (2) and carries out power transfer.
7. semiconductor device comprises:
High breakdown transistor (3), it comprises the semiconductor layer (4) of first conduction type, this semiconductor layer (4) has reciprocal front and back, and this semiconductor layer (4) comprises by first groove (6) componentry (8) and wiring portion (9) electrically isolated from one
Be positioned at first dielectric film (17) on the front of described semiconductor layer (4), this first dielectric film (17) has first and second contact holes; With
Be positioned at the backplate (19) on the back side of described semiconductor layer (4),
Wherein said componentry (8) comprising:
The channel layer of second conduction type (10), this channel layer (10) are formed into described semiconductor layer (4) and are exposed to first of described semiconductor layer (4);
The semiconductor region of first conduction type (11), this semiconductor region (11) are formed in the described channel layer (10) and have the impurity concentration that is higher than described semiconductor layer (4);
Be formed on the gate insulating film (15) on the exposing surface of the described channel layer (10) between described semiconductor region (11) and the described semiconductor layer (4);
Be formed on the gate electrode (16) on the described gate insulating film (15);
Be electrically coupled to the described semiconductor region (11) of described channel layer (10) and each first wiring part (18) in contact zone (12); With
The drain contact district (13) of first conduction type, described drain contact district (13) are formed on the back side of described semiconductor layer (4) and have the impurity concentration that is higher than described semiconductor layer (4),
Wherein said wiring portion (9) comprising:
Be formed on first contact zone (21) on the front of described semiconductor layer (4);
Be formed on second contact zone (22) on the back side of described semiconductor layer (4); With
Be electrically coupled to second wiring part (23) of described first contact zone (21),
The described drain contact district (13) of wherein said componentry (8) is electrically coupled to described second contact zone (22) of described wiring portion (9) by described backplate (19),
Wherein said first wiring part (18) is electrically coupled to the described semiconductor region (11) of described channel layer (10) and each in described contact zone (12) by described first contact hole of described first dielectric film (17), and
Wherein said second wiring part (23) is electrically coupled to described first contact zone (21) of described wiring portion (9) by described second contact hole of described first dielectric film (17).
8. semiconductor device according to claim 7,
Described first wiring part (18) of wherein said componentry (8) is formed on described first dielectric film (17) and goes up and extend upward in first party, and
Described second wiring part (23) of wherein said wiring portion (9) is formed on described first dielectric film (17) and goes up and extend upward in the second party opposite with described first direction.
9. semiconductor device according to claim 7 also comprises:
Low voltage circuit part (1); With
By the high voltage circuit part (2) of described first groove (6) encirclement,
Wherein said low voltage circuit part (1) and described high voltage circuit part (2) are jointly surrounded by second groove (5), and
Wherein said high breakdown transistor (3) is constituted as between described low voltage circuit part (1) and described high voltage circuit part (2) and carries out power transfer.
10. semiconductor device according to claim 9,
Wherein said first groove (6) comprises a plurality of grooves.
11. semiconductor device according to claim 7,
Wherein said componentry (8) and described wiring portion (9) are jointly surrounded by the 3rd groove (7), and
Wherein said backplate (19) only is arranged in by described the 3rd groove (7) area surrounded.
12., also comprise according to each described semiconductor device in the claim 9-11:
Be positioned at second dielectric film (40) on the back side of described semiconductor layer (4), this second dielectric film (40) has first and second contact holes,
Wherein said backplate (19) is electrically coupled to the described drain contact district (13) of described componentry (8) by described first contact hole of described second dielectric film (40), and
Wherein said backplate (19) is electrically coupled to described second contact zone (22) of described wiring portion (9) by described second contact hole of described second dielectric film (40).
13. a semiconductor device comprises:
Low voltage circuit part (1);
High voltage circuit part (2);
High breakdown transistor (3), it is constituted as between described low voltage circuit part (1) and described high voltage circuit part (2) and carries out power transfer, described high breakdown transistor (3) comprises the semiconductor layer (4) of predetermined conductivity type, this semiconductor layer (4) has reciprocal front and back, and this semiconductor layer (4) comprises the componentry (8) of being isolated by groove (6) electricity; With
Power-supply wiring (52), its first of being formed on described semiconductor layer (4) goes up and is constituted as to described high voltage circuit part (2) and applies voltage,
Wherein said componentry (8) has at wiring part on the front of described semiconductor layer (4) (18) and the lead frame on the back side of described semiconductor layer (4) (50), described componentry (8) is constituted as vertical transistor, it is flowing electric current between described wiring part (18) and described lead frame (50) on thickness direction of described semiconductor layer (4)
Wherein said lead frame (50) has from the outstanding projection in the edge at the back side of described semiconductor layer (4), and
The described projection of wherein said lead frame (50) is electrically coupled to described power-supply wiring (52) by bonding line (53).
14. a semiconductor device comprises:
Low voltage circuit part (1);
High voltage circuit part (2);
High breakdown transistor (3), it is constituted as between described low voltage circuit part (1) and described high voltage circuit part (2) and carries out power transfer, described high breakdown transistor (3) comprises the semiconductor layer (4) of first conduction type, this semiconductor layer (4) has reciprocal front and back, and this semiconductor layer (4) comprises the componentry (8) of being isolated by groove (6) electricity; With
Power-supply wiring (52), its first of being formed on described semiconductor layer (4) goes up and is constituted as to described high voltage circuit and partly applies voltage,
Wherein said componentry (8) comprising:
The channel layer of second conduction type (10), this channel layer (10) are formed into described semiconductor layer (4) and are exposed to first of described semiconductor layer (4);
The semiconductor region of first conduction type (11), this semiconductor region (11) are formed in the described channel layer (10) and have the impurity concentration that is higher than described semiconductor layer (4);
Be formed on the gate insulating film (15) on the exposing surface of the described channel layer (10) between described semiconductor region (11) and the described semiconductor layer (4);
Be formed on the gate electrode (16) on the described gate insulating film (15);
Be electrically coupled to the described semiconductor region (11) of described channel layer (10) and each the wiring part (18) in contact zone (12);
The drain contact district (13) of first conduction type, this drain contact district (13) are formed on the back side of described semiconductor layer (4) and have the impurity concentration that is higher than described semiconductor layer (4); With
Be formed on the back side of described semiconductor layer (4) and be electrically coupled to the lead frame (50) in described drain contact district (13),
Wherein said componentry (8) is constituted as vertical transistor, and it is flowing electric current between described wiring part (18) and described lead frame (50) on thickness direction of described semiconductor layer (4),
Wherein said lead frame (50) has from the outstanding projection in the edge at the back side of described semiconductor layer (4), and
The described projection of wherein said lead frame (50) is electrically coupled to described power-supply wiring (52) by bonding line (53).
15. the semiconductor device according to claim 14 also comprises:
Be formed on the dielectric film (51) on the back side of described semiconductor layer (4), this dielectric film (51) has the opening that exposes described componentry (8),
Wherein said lead frame (50) is bonded to this dielectric film (51).
CN 200810170454 2007-11-09 2008-11-06 Semiconductor device with high-breakdown-voltage transistor Expired - Fee Related CN101431102B (en)

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