TWI422007B - An esd tolerant i/o pad circuit including a surrounding well - Google Patents

Description

An input/output pad circuit having an electrostatic discharge tolerance surrounding a well

Embodiments of the present invention relate to an electrostatic discharge protection circuit in an integrated circuit.

The integrated circuit often includes an electrostatic discharge protection circuit coupled to the input/output pad. A representative electrostatic discharge protection circuit is described in U.S. Patent No. 6,585,902 to Saling et al., entitled "EFFICIENT ESD PROTECTION WITH APPLICATION FOR LOW CAPACITANCE I/O PADS".

As shown in Figure 4 of the U.S. Patent Specification, to Salling et al., a prior art ESD protection circuit includes a diode between the contact pad and the supply potential VDD, which will have a high positive voltage to VDD. Leakage during discharge events to limit high voltage operation. The ESD protection circuit also includes a field effect transistor between the contact pad and the ground, and has a parasitic bipolar transistor or a gated rectifier (SCR) structure. This field effect transistor and parasitic bipolar transistor/sigma controlled rectifier (SCR) structure has a trigger voltage that turns on and discharges during an electrostatic event.

It is desirable to have an ESD protection circuit with a consistent trigger voltage that can quickly respond to ESD events and can handle high voltage operation as well as input/output pads for integrated circuits.

Embodiments of the present invention relate to an electrostatic discharge tolerant device comprising a semiconductor body having a first conductivity type, typically p-type, coupled to a reference voltage, typically the ground of a p-type substrate. A contact pad is formed on the semiconductor body, which can serve as an end point for one of the circuits connected to the outside of the device. A well, referred to herein as a surrounding well, has a second conductivity type (e.g., n-type for a p-type substrate) and is arranged in a loop to surround a region of the semiconductor body that acts as an electrostatic discharge circuit. The surrounding well system is relatively deep and, in addition to defining a region that acts as an electrostatic discharge circuit, provides a first end of a diode formed in the semiconductor body. In a region surrounded by the surrounding well, a diode is coupled to the contact pad, and a transistor is coupled to the reference voltage, the two are connected in series to form a parasitic device in the semiconductor body and provide a The discharge current path is confined within a discharge region formed by the deep surrounding well in the semiconductor body.

A deep internal well is in the region of the semiconductor body and has the second conductivity type located in a region surrounded by the surrounding well. A first end of the diode of the ESD circuit is coupled to the contact pad and includes a doped region in the internal well having the first conductivity type. A second end of the diode of the ESD circuit includes a doped region in the internal well having the second conductivity type. A source and a drain of the transistor are in the body, and have a second conductivity type in a region surrounded by the well. A body is disposed in the body, having the first conductivity type in the region, and having a collection region contact formed within the region and coupled to the reference voltage and the source of the transistor. A latch prevents the bias terminal from coupling to a voltage source and is also provided in the body between the inner well and the transistor. An inner portion is coupled to the body and coupled to the second end of the diode and the drain of the transistor.

The surrounding well is coupled to the contact pad such that it can reach a high voltage substantially the same as the contact pad during a high positive voltage discharge event. Also because it is deep enough, it tends to limit the flow of current in the discharge event to within one volume of the semiconductor body. Thus, the carrier implanted into the semiconductor body assists in opening the parasitic device in an efficient and consistent manner. In addition, when the voltage of the pad and the surrounding well is high, since the diode formed between the surrounding well and the semiconductor body is reversely biased, and the diode formed between the deep inner well and the semiconductor body is also reversed. The bias is biased so that positive charges do not flow to the deep internal well. This limits the positive charge to within the discharge area surrounding the well.

Furthermore, the structures described herein may also be suitable for high voltage applications because there is no forward diode path from the contact pad to the supply voltage source VDD. This enables the operation of the contact pad when the voltage is higher than VDD.

The trench insulator is used in the apparatus described herein, including a surrounding well trench insulator within the body between the surrounding well and its surrounding area. In addition, an internal trench insulator is interposed between the inner well and the transistor drain. The inner trench insulator has a depth system that is greater than a depth of the transistor drain. By limiting the current in the discharge event to this discharge region, the parasitic bipolar transistor will turn more evenly.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

The following description of the embodiments of the present invention should be combined with reference to FIGS. 1 through 5.

1 is a schematic diagram showing the connection of an input/output pad 10 to an electrostatic discharge circuit including an n-type surrounding well 11 in a p-type semiconductor body in accordance with an embodiment of the present invention. A more detailed structure of this n-type surrounding well 11 can be seen in Figure 2. The n-type surrounding well 11 provides a cathode of a diode 12, and an anode of the diode 12 is a semiconductor body. The semiconductor body is coupled to the ground 13 by a substrate resistor 21. The n-type surrounding well 11 defines an area in which a second diode 15 is arranged in series with the source drain of the field effect transistor 16 between the input/output pad 10 and the ground 13. This diode 15 is formed within a deep n-type internal well 14. A latch prevents the n-type terminal 17 from being coupled to a voltage source 18 to provide a voltage, such as a supply potential VDD, formed between the inner well 14 and the transistor 16. A p+ type collection region end point 20 is formed between the transistor 16 and the surrounding well 11 and coupled to the ground 13. The gate 19 of the transistor 16 is coupled to ground in this illustrative embodiment. In other embodiments, it may be floating or coupled to other reference voltages.

Fig. 2 is a cross-sectional view showing the application of the circuit shown in Fig. 1 in an integrated circuit including the semiconductor body 100. The semiconductor body can be a bulk wafer, a body formed over the insulator, or other structure. In the cross section, the surrounding well 50 in the semiconductor body 100 is a deep well coupled to an input/output pad having an n-type doping, with a portion of which is shown on the left and right sides of the cross-sectional illustration, respectively. Ditch insulators, such as shallow trench isolation structures 70 and 71, are on either side of the surrounding well 50. The trench insulator 71 (surrounding insulator) is located between the surrounding well and an internal region forming a diode/transistor discharge circuit. The surrounding well 50 has a depth system that is greater than the depth of the trench insulator 71. End points 50a, 50b of the N+ pattern are provided on the surface surrounding the well 50 to provide ohmic contact with the contact pads.

A deep internal well 51 having an n-type doping is formed on the right side of this region. A p+ type end point 52 is formed in the deep inner well 51 and coupled to the input/output pad. A p+ type end point 53 is formed in the deep inner well 51 and serves as an anode formed in the inner body 51 of the diode. A trench isolation structure 72 separates the inner well 51 from the structure on the right side of the drawing. The n+ type terminals 54 and 55 are in the semiconductor body 100 and are separated by a trench insulator 73 as a latching prevention end point. A trench insulator 74 separates the latching prevention end 55 from the drain terminal 56 and the source drain 57 of the field effect transistor. This 汲 extreme point 56 is an n+ type region in the semiconductor body 100. Similarly, this source extremity 57 is formed in the semiconductor body 100 and includes an n+ type region and a 汲 extreme point 56 separated by a channel. In the illustrated embodiment, the lightly doped n-type regions 58, 59 are formed between the drain terminal 56 and the source terminal 57, respectively, and the channel of the transistor. The gate 63 of the transistor is over the via and is separated from the via by a gate insulating layer. The sloped area next to the gate is the sidewall element of the transistor gate. A trench insulator 75 separates the source terminal 57 of the field effect transistor from the p+ type collection region 60 formed in the semiconductor body 100 adjacent to the trench insulator 71 and the surrounding well 50 formed on the right side of the layout. The surrounding well 50 has a depth system that is much larger than, for example, 2 to 10 times deep, the depth of the n+ type and p+ type regions, including the end points 52, 53, 54, 55, 56, 57, and 60, and constitutes the discharge. The circuit, and thus as a current limiting structure. The wraparound well 50 is considered to be deeper than one of the bias lockout prevention terminals 54 and 55 and the 汲 extreme point 56 and the source extremity 57, which have sufficient depth to affect the charge flow restriction in this parasitic device.

As shown in the figure, the terminal 53 acts as the anode of the diode and is connected to the 汲 extreme point 56 of the transistor by a connector located over the semiconductor body. In addition, the source terminal 57 of the transistor is coupled to ground and is coupled to the p+ type collection region terminal 60 by a line 64 located above the semiconductor body, wherein the line 64 is a connector on the semiconductor body 100. The latching prevention terminals 54 and 55 are coupled to a voltage source, such as a supply potential VDD, by a connector 62 on the semiconductor body.

As shown in Figure 2, parasitic bipolar transistors 80 and 81 (also forming a controlled rectifier (SCR)) are formed as a result of this layout. The bipolar transistor 80 is a PNP device in which the p+ type terminal 52 is used as an emitter, the n-type deep internal well 51 is used as a base, and the p-type semiconductor main system is used as a collector. The bipolar transistor 81 is an NPN device in which the 汲 extreme point 56 serves as an emitter, the semiconductor body 100 serves as a base, and the source terminal 57 serves as a collector. In operation, during a positive electrostatic discharge event, the current free junctions 52 and 53 form a diode to the transistor comprising drain 56 and source 57 to ground. In addition, the current free junction 52, the n-type deep internal well 51, and the parasitic bipolar transistor formed by the semiconductor body 100 flow, and positive charges are injected into the base of the bipolar transistor 81 to the p+ type collection region end 60. In addition, the charge flows into the channel of the field effect transistor to raise the substrate bias and assist in turning on both the field effect transistor and the bipolar transistor 81. The surrounding well 50 tends to limit the flow of current in this region to the end point 60 of the p+ type collection region from the PNP device 80 to ground, improving the current density of the field effect transistor and the base of the parasitic NPN device 81, resulting in a more uniform device. And fast opening. Moreover, because the surrounding well 50 and the deep internal well 51 are coupled to the contact pad, they can reach a high voltage substantially the same as the contact pad during a high positive voltage discharge event. This causes the formation of the diode between the surrounding well 50 and the semiconductor body 100 to be reverse biased, and the formation of the diode between the deep internal well 51 and the semiconductor body is reverse biased. This limits the positive charge within the surrounding well 50.

The surrounding well 50 and the internal well 51 are relatively deep wells and have a well depth, for example, on the order of 1 to 1.5 microns. Thus, other n+ type end points in the area surrounding the well have a well depth in the order of 0.13 to 0.18 microns in their respective systems. Thus, the surrounding well is deeper than the end of the second collection zone and one of the drain and source extremes. Other p+-type endpoints in this region have a well depth on the order of 0.17 to 0.23 microns. The trench insulation system is arranged deeper than the n+ type end point and the p+ type end point, for example, on the order of 0.28 to 0.35 micron.

The doping concentration of the surrounding well 50 and the inner well 51 may be on the order of 10E13/cm ² . Similarly, the doping concentrations of the endpoints 52, 53, 54, 55, 56, 57, and 60 can be on the order of 10E15/cm ² .

In this case, the deep surrounding well and the internal well tend to limit the flow of current in the discharge event to a volume of the semiconductor body, which provides a consistent and rapid discharge while preventing charge emission to the main current during discharge. Outside the path.

Figure 3 shows a layout similar to the electrostatic discharge circuit shown in Figure 2. As previously described, the trench insulator 210 separates many different components. This layout shows that the n-type surrounding well 200 has a rectangular shape. A deeper n-well 201 is located within the area surrounded by the surrounding well 200. An n+ type end point 201a is formed within the deeper n-well 201 and has a trapezoidal pattern. The p+ type end points 202-1 to 202-7 are located between the horizontal lines of the ladder pattern n+ type end point 201a. In this arrangement, the edge of the deeper n-type well 201 is aligned with the edge of the n+ type end point 201a. The end of the collection zone (the small square labeled "x" in the figure) is aligned with the surface of the n+ type end point 201a. Similarly, the collection zone endpoints are aligned with the surfaces of the p+ type endpoints 202-1 through 202-7.

The latching prevents the n+ type end points 203 and 204 from extending vertically through the area surrounded by the surrounding well 200.

The n+ type active region 205 of the transistor includes five source regions S and four drain regions D placed on opposite sides of the deep n-well 201 with latching prevention n+ type terminals 203 and 204 therebetween. The gate structures 211-1 to 211-8 are formed of doped polysilicon or metal lines over the active region 205. (only 211-1 and 211-8 are shown in the illustration to prevent being too crowded).

A p+ type collection zone 206 is formed between the active zone 205 and the right side of the surrounding well 200 and extends through the zone defined by the surrounding well 200. Although not shown in the illustration, the end of the collection area (shown as a small "x" square) is on many different endpoints where the endpoints can be used with the reference voltages, voltage sources, or Is the connector connection above.

The size and number of gates of the digitized diode structures located within the n-type internal well 201, as well as the size and number of gates of the digitized transistor structures above the active region 205, may vary depending on the needs of the particular application. Similarly, the number of latching prevention endpoints 203 and 204 can also vary depending on the needs of a particular application. Similarly, the distance between the deep n-type internal well 201 and the active region 205 can also be adjusted as needed to prevent latch-up and improve the performance of the electrostatic discharge circuit.

In a representative system, there are a total of 14 p+-type endpoints with an area of 1.5 by 24 square microns in a deep n-type well instead of the seven endpoints 202-1 to 202- as shown in the layout of Figure 3. 7. Moreover, in a representative system, the transistor in the active region 205 in the layout has six source extremes and five germanium extremes, and ten gates, and the gates have a size of about 0.6 by 30 square microns. .

Figures 4 and 5 show block diagrams of an alternative electrostatic discharge circuit that can be used with the surrounding wells described herein in combination with the alternative n-channel MOS transistors 16 that differ from Figure 1. Other alternative embodiments may be used, using a parasitic NPN bipolar transistor 81 as in Figure 2.

In Fig. 4, the transistor 16 of Fig. 1 is replaced by a field transistor 406 having a thicker oxide layer over the channel. Thus, the circuit of FIG. 4 includes an input/output pad 400 coupled to an electrostatic discharge circuit that includes an n-type surrounding well 401 in a p-type semiconductor body. The n-type surrounding well 401 provides a cathode of a diode 402, and an anode of the diode 402 is a semiconductor body. The semiconductor body is coupled to the ground 403 by a substrate resistor 411. The n-type surround well 401 defines an area in which a second diode 405 is arranged in series with the source drain of a field transistor 406 between the input/output pad 400 and the ground 403. A latch prevents the n+ terminal 407 from being coupled to a voltage source 408 to provide a voltage, such as a supply potential VDD, formed between the internal well 404 and the field transistor 406. A p+ type collection region end point 410 is formed between field transistor 406 and surrounding well 401 and coupled to ground 403.

In Fig. 5, the transistor 16 of Fig. 1 is replaced by series connected transistors 506a and 506b, at least one of which is biased to be turned off during normal operation of the integrated circuit. Thus, the circuit of Figure 5 includes an input/output pad 500 coupled to an electrostatic discharge circuit that includes an n-type surrounding well 501 in a p-type semiconductor body. The n-type surrounding well 501 provides a cathode of a diode 502, and an anode of the diode 502 is a semiconductor body. The semiconductor body is coupled to the ground 503 by a substrate resistor 511. The n-type surround well 501 defines an area in which a second diode 505 is arranged in series with the source drain of the transistors 506a and 506b between the input/output pad 500 and the ground 503. A latch prevents the n+ terminal 507 from being coupled to a voltage source 508 to provide a voltage, such as a supply potential VDD, formed between the internal well 504 and the transistors 506a and 506b. One or both of the gates 509a and 509b can be coupled to ground to ensure that the current path is turned off during normal operation. A p+ type collection region end 510 is formed between field transistor 506b and surrounding well 501 and coupled to ground 503.

Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 400, 500. . . Input/output pad

11, 401, 501. . . Surrounding well

12, 402, 502. . . Dipole

13, 403, 503. . . Ground

14, 404, 504. . . Internal well

15, 405, 505. . . Second diode

16. . . Field effect transistor

17,407,507. . . N-type endpoint

18, 408, 508. . . power source

19, 509a, 509b. . . Gate

20, 410, 510. . . Collection area

21, 411, 511. . . Substrate resistance

50. . . Surrounding well

51. . . Deep internal well

52. . . p+ type endpoint

53, 54, 55. . . n+ type endpoint

56. . . Extreme point

57. . . Source extreme

58, 59. . . Lightly doped n-type region

60. . . Collection area

61, 62, 64. . . Connector

63. . . Gate

70, 71, 72, 73, 74, 75. . . Ditch insulator

80. . . PNP parasitic bipolar transistor

81. . . NPN parasitic bipolar transistor

100. . . Semiconductor body

200. . . Surrounding well

201. . . Type n well

202-1 to 202-7. . . p+ type endpoint

203, 204. . . n+ type endpoint

205. . . Active area

206. . . Collection area

210. . . Ditch insulator

211-1 to 211-8. . . Gate

406. . . Field transistor

506a, 506b. . . Transistor

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of an electrostatic discharge circuit including a surrounding well in accordance with the present invention.

Figure 2 shows a schematic cross-sectional view of an electrostatic discharge circuit including a surrounding well in a semiconductor body.

Figure 3 shows a schematic layout of an electrostatic discharge circuit including a surrounding well.

Figure 4 and a block diagram showing a first alternative electrostatic discharge circuit including a surrounding well.

Figure 5 and a block diagram showing a second alternative electrostatic discharge circuit including a surrounding well.

10. . . Input/output pad

11. . . Surrounding well

12. . . Dipole

13. . . Ground

14. . . Internal well

15. . . Second diode

16. . . Field effect transistor

17. . . N-type endpoint

18. . . power source

19. . . Gate

20. . . Collection area

twenty one. . . Substrate resistance

Claims (14)

An electrostatic discharge tolerating device comprising: a semiconductor body having a first conductivity type; a contact pad on the semiconductor body; a surrounding well in the semiconductor body, the surrounding well having a contact end coupled to the contact pad And having a second conductivity type, the surrounding well surrounding a region of the semiconductor body; an electrostatic discharge circuit in the region of the semiconductor body, the electrostatic discharge circuit comprising a diode, the diode having a first end of the first conductivity type and a second end of the second conductivity type, the first end of the diode having a contact end coupled to the contact pad, and a transistor The electro-optic system is connected in series between the second end of the diode and a reference voltage connector, the reference voltage connector is not connected to the surrounding well, and the diode and the transistor are used for A discharge current path between the contact pad and the reference voltage connector is provided in a discharge region of the semiconductor body. The electrostatic discharge tolerant device of claim 1, comprising: an internal well in the region of the semiconductor body, and having the second conductivity type; the first end of the diode includes a first doped region in the inner well; the second end of the diode includes a second doped region in the inner well, the second doped region having the second conductivity type and having a contact The end point is coupled to a connector; a source terminal and a terminal of the transistor are at the semiconductor main In the region of the body, the second conductivity type has a contact end coupled to the connector, the source terminal having a contact end coupled to the reference voltage connector; In the region of the semiconductor body, having the first conductivity type, the body end point having a contact end coupled to the reference voltage connector; a bias end point in the region of the semiconductor body having the second conductivity Between the internal well and the 汲 extreme point, the bias terminal has a contact terminal connected to a voltage source different from the reference voltage. The electrostatic discharge tolerant device of claim 2, wherein the body end point, the source extremity point, and the crucible extreme point each have a relative depth, and the surrounding well has a surrounding well depth that is far beyond the The relative depth of at least one of the body endpoint, the source, and the drain. The electrostatic discharge tolerant device of claim 2, wherein the body end point, the source extremity point and the crucible extreme point each have a relative depth, and the surrounding well has a surrounding well depth which is The relative depth of at least one of the body end point, the source, and the drain is between two and ten times. The electrostatic discharge tolerant device of claim 1, comprising: a surrounding well trench insulator between the surrounding well and the region in the body, and having a surrounding trench depth in the body There is a depth system greater than the depth of the surrounding trench. An electrostatic discharge tolerant device as described in claim 2, An internal trench insulator is interposed between the inner well and the drain in the body and has an internal trench depth, the drain having a depth in the body that is less than the inner trench depth. The electrostatic discharge tolerant device of claim 1, wherein the region comprises a first portion and a second portion, and the electrostatic discharge tolerant device comprises: an internal trench insulator interposed in the semiconductor body in the region Between the first portion and the second portion; a surrounding well trench insulator between the surrounding well and the region in the semiconductor body and having a surrounding trench depth, the surrounding well having a depth system greater than the Surrounding the trench depth; an internal well in the first portion of the region in the semiconductor body and having the second conductivity type, the inner well having a depth in the body greater than the surrounding trench depth; the diode a first end point includes a first doped region in the inner well, the first doped region has the first conductivity type; a second end of the diode includes a second doped region In the internal well, the second doped region has the second conductivity type; a source extreme point of the transistor and a terminal extreme point in the second portion of the region of the body Having the second conductivity type, the 汲 extreme point having a contact end coupled to the reference voltage connector; a body end point in the second portion of the region in the semiconductor body having the first conductivity type The body end has a contact end coupled to the reference voltage connector; a bias end is between the first portion and the second portion of the region in the semiconductor body, the bias terminal has the second conductive Type, the bias terminal has a contact terminal connected to a voltage different from the reference voltage a source coupling; and the second end of the diode is coupled to the drain of the transistor. The electrostatic discharge tolerant device of claim 7, wherein the 汲 extreme point is coupled to the second end of the diode through a second field effect transistor. The electrostatic discharge tolerant device of claim 1, wherein the transistor has a gate having a contact end coupled to the reference voltage connector. The electrostatic discharge tolerant device of claim 1, wherein the transistor comprises a field of transistors. An electrostatic discharge tolerant device comprising: a semiconductor body having a first conductivity type; a contact pad on the semiconductor body; a surrounding well in the semiconductor body coupled to the contact pad and having a second conductivity type Surrounding a region of the semiconductor body; a latching preventing biasing end point in the semiconductor body, having the second conductivity type, and dividing the region into a first portion and a second portion, the latching Preventing the bias terminal having an end point for coupling to a voltage source coupling; an internal well in the first portion of the region in the semiconductor body, the internal well having the second conductivity type; a first doping An area in the inner well having the first conductivity type as a first end point of a diode and having an end point and the contact a pad is coupled; a second end of the diode includes a second doped region in the inner well, having the second conductivity type, and having a terminal coupled to a connector; a transistor a source extremity and an extremity point in the second portion of the region of the semiconductor body having the second conductivity type, the 汲 extreme point having a contact end coupled to the connector, the source terminal having contact An end point coupled to a reference voltage connector not connected to the surrounding well; and a body end point in the semiconductor body having the first conductivity type in the second portion of the region, the body end point having The contact terminal is coupled to the reference voltage connector. The electrostatic discharge tolerant device of claim 11, comprising: a plurality of trench insulators interposed between the surrounding well and the inner well, and a plurality of trench insulators interposed between the first end of the diode Between the second end point, a plurality of trench insulators between the inner well and the latching prevention bias end point, a plurality of trench insulators interposed between the latching prevention bias terminal and the source terminal point and the 汲Between the extreme points, a plurality of trench insulators are interposed between the source extreme point and the anode extreme point and the body end point. The electrostatic discharge tolerant device of claim 11, wherein the body end point, the source extremity point, and the crucible extreme point each have a relative depth, and the surrounding well has a surrounding well depth which is far beyond the The relative depth of at least one of the body endpoint, the source, and the drain. The electrostatic discharge tolerant device of claim 11, wherein the body end point, the source extremity point and the crucible extreme point each have a relative depth, and the surrounding well has a surrounding well depth which is The relative depth of at least one of the body end point, the source, and the drain is between two and ten times.