JPH0230187A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To solve a problem of an ON resistance and an isolation in a semiconductor integrated circuit where a vertical-type DMOSFET of one conductivity type having a drain region inside an isolation region has been arranged by a method wherein a diffusion layer of an opposite conductivity type is arranged inside the isolation region so as to be adjacent to the drain region. CONSTITUTION:In a semiconductor integrated circuit where a vertical-type DMOSFET of one conductivity type having a drain region 6 inside an isolation region limited by isolation layers 5, a diffusion layer 10b, of an opposite conductivity type, is arranged inside said isolation region so as to be adjacent to said drain region 6. For example, a p-type substrate region 10a is formed; at the same time, a p-type diffusion layer 10b as an anode region 10b of a diode D1 arranged inside an identical isolation region is formed to be adjacent to a drain wall layer 6. Then, a p<+> type substrate contact region 11a and an anode contact region 11b are formed individually in individual contact parts of the p<+> type substrate contact region 10a and the anode region 10b by a diffusion operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor integrated circuit using a vertical FET.

(Prior Art) Conventionally, a diffused self-aligned gate type MO5FET, that is, a DMOSFET, has been used as a semiconductor element for high-speed control of high voltage and large current.
There is. FIG. 6 shows a cross-sectional view of an example of a general enhancement type vertical n-channel DMOSFET.

In FIG. 6, 1 is a high resistance p-type substrate, 2 and 3 are
Highly doped n+ type and p+ type buried layers are formed in the substrate 1, respectively. An n-type epitaxial layer 4 is formed thereon, and a p1 type isolation layer 5 is formed by diffusion in the epitaxial layer 4 corresponding to the p1 type buried layer 3, and a p1 type isolation layer 5 corresponding to the buried layer 2 is formed on the epitaxial layer 4. The n3 type drain wall layer 6 is also formed by diffusion. Next, a p-swelling diffusion layer 7 for improving the drain breakdown voltage is formed around the p-type substrate region 10a.

8a is a gate oxide film, 8b is a LOCOS (LOCO5: Lo
Calized Oxidation of 5ili
This is the 5i02 layer by Con). Reference numeral 9 denotes a gate made of polysilicon arranged in the gate portion. lla is a p0 type contact diffusion region formed by diffusion in the contact portion of the p type breast plate region 10a, 12a is a source region, and 12b is an n0 type diffusion layer formed in the contact portion of the drain wall layer 6 by diffusion. I3 is 5i
(12 films. 14a is a source substrate electrode,
14b is a gate electrode, and 14c is a drain electrode.

In this type of integrated circuit, when a plurality of devices are formed in one chip, it is necessary to separate each DMOSFET device by an isolation layer 5, and the drain electrode 14c is taken out from the semiconductor surface.

Here, in order to design a high breakdown voltage, the concentration and thickness of the epitaxial layer 4 are set to, for example, 1 (if the IOV voltage is rated,
3~5Ω"cm and 15~204m, , 200
For V-pressure, approximately 10Ω・Cff1 and 20-30
Since it is a μ country, it is necessary to form a J layer at a low concentration.

On the other hand, the on-resistance of an n-channel DMOSFET is Rwall+Rburlad+Re
It becomes a series resistance of pl and Rch. As described above, the epitaxial layer 4 is thick with a low concentration, and there is no conductivity modulation due to injection of minority carriers as in a bipolar element, so Repl accounts for a large proportion of the on-resistance. Therefore, in order to lower the on-resistance, it is effective to increase the gate area and lower Repi.
If this is done, the device area will increase. Furthermore, the drain wall layer 6 and the isolation diffusion layer 5 need to be separated by about 40 μm if the voltage withstand voltage is 200V, for example, which is necessary for the normal N-channel DMOS
In the FET, the area required between the drain wall layer 6 and the isolation layer 5 occupies about half of the entire device.

[Problem to be solved by the invention]

In this way, in the structure of a conventional vertical DMOSFET, the resistance of the epitaxial layer 4 is large, so in order to lower the on-resistance, the device area must be increased, and the more you try to increase the withstand voltage, the more Since it is necessary to increase the distance between the drain wall layer 6 and the isolation layer 5 to ensure sufficient isolation, when aiming for a high voltage and large current device,
The device became very large, leading to increased costs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit that is appropriately configured and arranged so as to solve the above-mentioned problems of on-resistance and isolation in conventional vertical DMOSFETs.

(Means for Solving the Problems) In order to achieve such an object, the present invention provides a vertical DMOS FET of one conductivity type having a drain region within an isolation region limited by an isolation layer.
The semiconductor integrated circuit is characterized in that a diffusion layer of an opposite conductivity type is disposed in the isolation region adjacent to the drain region.

Here, a DMOSF of opposite conductivity type is formed by a diffusion layer of opposite conductivity type.
A source region of ET can be formed.

Alternatively, a diffusion layer of opposite conductivity type and a DMOS of one conductivity type
A diode can be formed by the drain region of the FET.

[For production]

In the present invention, for example, within the isolation region limited by the isolation layer of an n-channel type DMOSFET, adjacent to the drain region connected to the drain electrode of the DMOSFET, an opposite conductivity type, that is, p
form a shaped diffusion layer. This p-swelling diffusion layer is formed in the p-channel type DMO formed within the isolation region.
It is used as the source region of SFET or the anode region of diode.

As a result, when an n-channel DMOSFET is turned on, minority carriers are injected into the lightly doped drain region from the p-swelled diffusion layer of the opposite conductivity type formed in the drain region, thereby increasing the conductivity of the high-resistance epitaxial layer. is modulated and its resistance value decreases significantly, resulting in such N
The on-resistance of a channel type DMOSFET can be lowered.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a sectional view of an embodiment of the present invention. In this example, an enhancement type n-channel DM with a breakdown voltage of 200V, an on-resistance of 100Ω, and a current capacity of roomA is used.
1 shows an integrated circuit including an OSFET.

In FIG. 1, on a high-resistance p-type substrate 1 with a specific resistance of 30 Ω·cm, a very high concentration n0-type buried layer 2 and a p0-type buried layer 3 of about several tens of Ω0 are formed, and on top of that, lOΩ・A low-type epitaxial layer 4 of approximately cn+ is grown in a vapor phase to a thickness of 20 to 30 μm. A p-type isolation diffusion layer 5 and a lo-type train wall diffusion layer 6 having a surface concentration of about 1016 to 10197 cm' and a deep diffusion depth are formed from the semiconductor surface. These diffusion layers 5 and 6 reach the p" type buried layer 3 and the n0 type buried layer 2, respectively.

Next, in order to improve the drain breakdown voltage, a p-swelling diffusion layer 7 is formed on the outer periphery of the p-type brace region 10a.

This p-swelling diffusion layer 7 has a very low concentration, 10167c
It is m3. The diffusion depth may be approximately 3 μm. A gate oxide film 8a with a thickness of about 0.1 μm is formed on the surface of the active region limited by the p-type substrate region 10a, and a Si2 layer 8 with a thickness of about 1 μm is formed on the remaining semiconductor surface.
b is formed by locos. A polysilicon gate region 9 having a thickness of approximately 0.6 μm is formed on gate oxide film 8a.

Further, as the p-type blasting region 10a, an ND channel layer 10a with a surface concentration of about 10''/cm' and a diffusion depth of 3 μm is formed. A ρ-type diffusion layer lOb is formed adjacent to the drain wall layer 6 as the anode region 10b of the diode D1 arranged in the ration region.At each contact portion of the p-type discharge region 10a and anode region 10b, p4 with a surface concentration of about 10197 cm' and a diffusion depth of about 1.5 μm.
A shaped substrate contact region 11a and an anode contact region 11b are each formed by diffusion. Furthermore, the source region 12a adjacent to these contact regions 11a and the drain wall contact layer 12b disposed in the drain wall layer 6 are coated with an
Formed by + type source/drain diffusion.

Thereafter, a Sin2 layer 13 is laminated on the Sin layer 8b by the CVD method, and then a contact hole is formed in this layer 13. Next, the n-channel type DMOSFET MN
The source/substrate electrode 14a, gate electrode 14b, and drain electrode 14C1 of I, and the anode electrode 14d of diode J)l formed in the same isolation region are formed of an A4-Si alloy. The drain electrode 14c also acts as a cathode electrode of the diode D1.

FIG. 2 shows an example of a push-pull circuit using the device shown in FIG. Here, MNI corresponds to the n-channel type DMOSFET shown in Fig. 1, and the output terminal 0UTI
It acts to absorb more current. MN2 functions to cause current to flow into the output terminal from the power supply.

Di corresponds to the diode shown in FIG. This diode DI protects the gate of MOS FET MN2,
DMOSFET when MOS FET MN2 is OFF
When MNI is ON, reverse bias is applied between the gate and source of MOS FET MN2.
This is to prevent MN2 from turning on and prevent through current from flowing. R is MOS FET MN2 ON
, is a resistance for smooth OFF operation, and is usually Ω in number.
It is.

Manually input an H signal to the first input terminal INI, and connect the DMOSFET.
When the MNI is turned on, current is sucked into the drain electrode 14c via the resistor R until the sink current reaches several hundred μA, but when the current value exceeds several hundred μA, a voltage of 0.6 V or more is applied to the diode Dl. Diode Di
A current flows through. At this time, 8i14
Since current flows into d, holes are injected into epitaxial region 4 from anode region 10b. At this time, the conductivity of the epitaxial region 4 is modulated by the injection of minority carriers, and its resistance value is significantly reduced.

As shown in Fig. 1, the on-resistance of [1MO5FET MNI can be expressed as Rwmth+Rburisd÷Rapl''RCh.For example, the entire on-resistance is 10
In the case of 0Ω, Rwa□ and Rburled are each several Ω
, Rap I is about 60Ω, and Reh is about 40Ω. However, due to the injection of minority carriers as described above, the resistance value Rapt of the epitaxial region 4 decreases to a value that can be ignored compared to Rch. Therefore, the on-resistance was reduced to 40Ω. On resistance 10
When designing with 0Ω, the area of the source/gate portion, which is the effective channel region, can be reduced to 40 Ω, and the device area can therefore be reduced. Furthermore, since the two devices MNI and 01 can be placed in one and the same isolation region, the effect of reducing the device area is also significant.

Since the source/substrate potential of the DMOSFET MNI and the potential of the p-type substrate 1 are generally equal, the substrate region 10a and the isolation layer 5 are connected via the p-swelling diffusion layer 7, as shown in FIG. It may also be a configuration. According to this configuration, the region between the isolation layer 5 and the p-swelling diffusion layer 7 in FIG. 1 can be omitted, which is effective in reducing the device area by that much.

FIG. 4 shows a cross-sectional view of yet another embodiment of the invention. This embodiment is a case where an n-channel type DMOSFET and a p-channel type DMO3FET are formed in the same isolation region.

In this embodiment as well, the n-channel type DMOS FET MN2a is formed in the same process as in the embodiment shown in FIG.
A p-swelling diffusion layer 7a is formed by diffusion in the same isolation region as this DMOSFET MN2a and between the p-swelling diffusion layer 7 and the drain wall layer 6,
This layer 7a allows p-channel type DMOSFET M
A drain region of Pla is formed. Furthermore, the surface concentration in the channel region between layers 6 and 7 is approximately 101 a /
n-swelled diffusion layer 15 with cm3 and diffusion depth of about 3 μm
is formed by diffusion. This p-channel DMOSFE
The p1 type source region 11c and drain contact diffusion region lid of TMPla are replaced by an N-channel DMOSFE.
Substrate contact diffusion region 11a of TMN2a
are formed in layers 15 and 7a, respectively, with the same diffusion process. The substrate area of p-channel DMOSFET MPla is N-channel DMOSFET MN2.
This is common to the drain region of a.

FIG. 5 shows a circuit using the device of the embodiment shown in FIG. Here, M82a is the n-channel DMO in FIG.
SFET, MPla is p-channel DMO in Figure 4
S FET, D2a is n-channel DMOS FET
This is a parasitic diode composed of the p-type breast region foa of MN2a and the n-type epitaxial layer 4. DMOSFET MP is connected to the input terminal IN3 from the power supply voltage.
When a voltage lower than the threshold voltage of la is applied, this DMOS FET MPla turns on,
A current flows through the resistor R1 connected between the gate electrode 14b and the source electrode 14a of the DMOSFET MN2a, and the voltage drop becomes the gate voltage. When the value of this gate voltage exceeds the threshold voltage of DMOSFET MN2a, this DMOSFET MN2a turns on and causes current to flow into load RL. Resistor R1 is DM(Is
This is necessary to smoothly turn on and off the FET MN2a. When the potential of the output terminal 01lT1 becomes higher than the power supply due to a change in the potential of the load side, the diode D2a immediately flows current to the power supply side to protect the element.
Reduce power loss and power load.

In this embodiment as well, the same effect of reducing on-resistance as in the previous embodiment can be obtained. 0M05 FETM connected to the power supply when DMOSFET MPla turns on and DMOSFET MN2a turns on accordingly.
DMOSFET MN2 from the source region 11c of Pla
Holes, which are minority carriers, are injected into the epitaxial region 4 directly under the gate a, the conductivity of this region increases significantly, and the on-resistance decreases. For this reason, DMOSFET
The device area of MN2a can be reduced. Furthermore, D.M.O.
Since the SFET MPla and MN2a are formed in the same isolation region, and the freewheeling diode D2a is also formed at the same time, it is effective in reducing the device area. It is important for this diode D2a to efficiently return the charge of the output terminal 0UTI to the power supply side.

However, in the conventional example, as shown in FIG.
From the drain wall layer 6 to the drain wall layer 6
When a current is applied to the p-type irradiated region 10a,
Epitaxial layer 4. p-type substrate 1 or isolation layer 5. When the parasitic PNP transistor in the p+ type buried layer 3 is turned on, a parasitic current flows into the p type substrate 1. p
Since the shaped substrate 1 is normally connected to the lowest potential, the potential difference with the potential of the output terminal is equal to or higher than the power supply voltage, and is usually equal to or higher than lθOv. Therefore, if a current is ideally applied to the power supply side, and the current flowing at that time is 1[^1, the power loss within the chip is 0.8I[wattl]
However, when the parasitic PNP transistor with a current amplification factor of hFE+ is ONI, the power loss due to the parasitic current to the p-type substrate 1 becomes about 100JrE+·I [watt1 or more].

Since h, 61 is usually about 0.3, a power loss of 30 times that in the ideal case occurs due to parasitic effects.

On the other hand, by adopting the structure shown in FIG. 4, when a current flows from the p-type substrate region 10a to the drain wall layer 6, a parasitic current flows to the p-type substrate 1, and at the same time, the p-channel DMOSFET MPa source area 1
Current also flows into 1c due to transistor operation. Since this source region 11c is connected to a power source, the current flowing into the source region 11c does not affect power loss much. In this case, the p-type blast rate region 10a
, epitaxial layer 4. LPN by source region 11c
The current amplification factor hFE2 of the P transistor is approximately 5.

Due to this transistor action, the current flowing from the p-type breast plate region 1 (la) to the drain wall layer 6 is 17
5 or less, the current flowing into the p-type substrate 1 is also reduced accordingly, and the power loss can be reduced to 115 or less compared to the conventional example.

(Effect of the invention) As is clear from the above, according to the present invention, N (p)
Channel type [1MO5FET and diode or P
In order to obtain the same on-resistance by forming the (n) channel type DMOSFET in the same isolation region, in the present invention, the first N (p)
The area between the source and gate of the channel type DMOSFET can be greatly reduced (for example, by 60 mm). In addition,
In the present invention, by forming the pixel elements in the same isolation region, the gap between the drain wall layer and the isolation diffusion layer is partially unnecessary, which is also effective in reducing the device area. For example, n(p)
By forming the channel type DMOSFET and the diode in the same isolation region, the device area can be reduced by about 5096 points compared to the conventional example. Also, n
When the (p) channel type DMOSFET and the p (n) channel type DMOSFET are formed in the same isolation region, the device area can be reduced by about 40 times compared to the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
3 and 4 are cross-sectional views showing two embodiments of the present invention; FIG. 5 is a circuit diagram showing an example of an application circuit of the device shown in FIG. 4; FIG. 6 is a sectional view showing a conventional example. DESCRIPTION OF SYMBOLS 1... ρ type substrate, 2... n+ type buried layer, 3... p+ type buried layer, 4... n- type epitaxial layer, 5... p1 type isolation layer, 6... n1 type drain wall layer, 7...p-type layer, 7a...p-type drain layer, 8a...gate oxide film, 8b...5i02 layer by Locos, 9...polysilicon gate region, 10a...p-type breast straight region, 10b...p
11a...P3 type substrate contact diffusion region, 11b...P' type anode contact diffusion region, 11
c...p type source region, lid...p1 type drain contact diffusion region, 12
a... Source region, 12b... B1 type drain wall contact diffusion region, 13... 5in2 film, 14a... Source/substrate electrode, 14b...
- Gate electrode, 14c...Drain electrode, 14d...Anode electrode, 14e...Source electrode, 14f...Gate electrode, 14g...Drain electrode, 15...Low type diffusion layer. -NrQ dimension 0 ■ ト 0 Ω ■ 0 Nono 0 +4b '#Yumei no I beg f) 叡1邜' D Revised drawing Figure 3

Claims (1)

[Claims] 1) Vertical DM of one conductivity type having a drain region within an isolation region limited by an isolation layer
1. A semiconductor integrated circuit in which an OSFET is arranged, wherein a diffusion layer of an opposite conductivity type is arranged in the isolation region adjacent to the drain region. 2) DMOSF of opposite conductivity type due to the diffusion layer of opposite conductivity type
Claim 1 characterized in that a source region of ET is formed.
The semiconductor integrated circuit described. 3) The diffusion layer of opposite conductivity type and the DMOSF of one conductivity type
2. The semiconductor integrated circuit according to claim 1, wherein a diode is formed by said drain region of ET.