TW200915560A - Resistive memory structure with buffer layer - Google Patents

Resistive memory structure with buffer layer Download PDF

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Publication number
TW200915560A
TW200915560A TW097127369A TW97127369A TW200915560A TW 200915560 A TW200915560 A TW 200915560A TW 097127369 A TW097127369 A TW 097127369A TW 97127369 A TW97127369 A TW 97127369A TW 200915560 A TW200915560 A TW 200915560A
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Taiwan
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oxide
buffer layer
electrode
memory device
memory
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TW097127369A
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TWI402980B (zh
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Wei-Chih Chien
Kuo-Pin Chang
Erh-Kun Lai
Kuang-Yeu Hsieh
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Macronix Int Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/028—Formation of the switching material, e.g. layer deposition by conversion of electrode material, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/90—Bulk effect device making

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  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Description

200915560 九、發明說明： 【發明所屬之技術領域】 本發明係與下列美國專利申請案相關聯：「可增進資料維 持生之電阻式隨機存取記憶結構」，申請於2⑻6年Η月 曰，其申請號為11/560,723，律師檔案編號]^沿(：1741_1 ;以 及「具有鎢化物之電阻式記憶體及其製造方法」，申請於2〇〇7 年12月16日，其申請號為11/955，137，律師播案編號祖1(： 1742-2。 本發明係關於§己憶體裳置以及製造高密度記憶體裝置之 方法，特別是關於含鶴-氧化合物之資料儲存材料之記憶體裝 【先前技術】 非揮發性記憶體裝置包括有磁性隨機存取記憶體 (MRAM)、鐵1_柿記紐(FRAM)，機倾機存取記 憶體(PCR^M)以及其他f阻式隨機存取記憶體_編）。由於 具有結構簡單、記馳尺寸小等優點，電阻式隨機存取記憶體 越來越受到重視。 含金屬-氧化物之電阻式隨機存取記憶體，在施加大小適 用於積體電路之電子脈衝時’其電阻可於二個以上之穩定範圍 間變化’而該電阻可以隨機存取之方式讀取或寫人，^用來 表示所儲存之資料。 目前有針對含氧化鎳(NiO)、二氧化鈦(Ti〇2)、二氧化給 (摘工氧化錯(Zr〇2)之電阻式隨機存取記憶體作為記憶胞 中的記憶材料之侧研究。此部分可胁ffiEE Int_i〇nal 200915560
Electron Devices Meeting 2004 之 IEDM Technical Digest 第 23.6.1-23.6.4 頁，由 Baek 等人發表之文章，，Highly Scalable Non-Volatile Resistive Memory using Simple Binary Oxide
Driven by Asymmetric Unipolar Voltage Pulses”。此種記憶胞乃 5 利用非自我排列(non-self_aligned)之製程形成於m-I-M之結構 中，其中Μ代表作為電極的貴金屬，而ϊ則為氧化鎳、二氧 化鈦、一氧化铪與二氧化錯中的任何一種。由於此種Μιμ結 構需要使用額外的遮罩及圖案化步驟來形成貴金屬電極與記 ， 憶材料，故其最終形成的記憶胞尺寸都很大。 10 目前亦有針對含有銅之氧化物(CuxO)之電阻式隨機存取 記憶體作為記憶胞中的記憶材料之相關研究。此部分可見於
IEEE International Electron Devices Meeting 2005 之 IEDM ^dmical Digest第746-749頁，由Chen等人發表之文 章”Non-Volatile Resistive Switching f0r Advanced Memory 15 Applications”。其中Cux〇材料係利用銅之熱氧化製程來形成， 並作為記憶胞的下電極，而上電極則由沉積並蝕刻而得之雙層 鈦/鈦化H(Ti/TiN)薄膜所、组成。此種结構需要使用額外的遮罩 ‘ 來形成上、下電極，且所形成之記憶胞尺寸都很大。此外，由 於抹除過程中施加的電場會促使銅離子形成銅之氧化物，則具 冑含銅之下電極會使得記鎌的抹除步驟變得更複雜。同時， CuxO僅具有1〇倍左右之相對窄的電阻操作區間。 目前亦有針對含有銅_三氧化鶴(Cu_w⑹之電阻式隨機 存取德體作為記憶胞巾的記憶材料之相關研究。此部分可見 於 2006 年 9 月’第 5 卷第 5 期之 IEEE Transactions on 5 Nanotechnology之第535_544頁，由K〇zic]d等人發表之文章，,a
Low-Power Nonvolatile Switching Element Based on 6 200915560
Copper-Tungsten 〇xide S福 Electrdyte，，，其中有關於鶴金屬 1成之_元件、含有鶴_氧化物以及經光嫌之朗電解質 - 以及銅之上電極的相關描述。該切換元件乃藉由將鎮-氧化物 成長或沉積於鎢材料上而形成，鎢_氧化物上並形成有一層 5 銅’其可透過光擴散作用而進入鶴氧化物内以形成固態電解 質，而在_電解質上卿成並圖案化有—作為上電ς的銅 層。於施加偏壓時，銅離子會由上電極處電沉積而進入固態電 解質，進而使切換元件改變電阻。此外，文中並提到「當I電 r 極缺少銅時，將無法偵測到切換活動」（見該文第539頁第1 10 攔）。據此，可知此種結構需要有一個銅之上電極，且其涉及 形成固態電解質之多個製程步驟。此外，該結構尚需要相反電 性之偏壓來引發銅離子之注入以程式化或抹除固態電解質。 【發明内容】 15 本發明之一實施例中提供了一種記憶體裝置，其包括第 一電極與第二電極以及介於第一與第二電極間並與其電性耦 , 接之記憶元件與緩衝層。記憶元件包括一種以上之金屬氧化合 物二緩衝層至少包括一氧化物或一氮化物。於某些實施例中， ，緩衝層包括一小於50埃之厚度。於某些實施例中，記憶元件 包括種以上之鶴氧化合物(tungsten oxygen compound)。於某 ，實施例中，緩衝層至少包括一種下列物質：二氧化矽(si〇2)、 氧化鎢(wo)、氧化鈦(Ti0)、氧化錄网〇)、氧化銘(A1〇)、氧 化銅(CuO)、氧化鍅(Zr0)、氮化矽(Si3N4)、.匕鈥(TiN)。於某 ，些實施例中，記憶元件至少包括一種下列物質：鎢之氧化物 "5 (W>〇x)、氧化鎳WiO)、五氧化二鈮(Nb205)、二氧化銅(Cu〇2)、 五氧化二钽(Ta2〇5)、三氧化二鋁(Al2〇3)、氧化鈷(c〇〇)、三氧 7 200915560 化二鐵(FqO3)、二氧化铪(Hf〇2)、二氧化鈦(了丨〇2)、鈦酸锶 (SrTi〇3)、鍅酸锶(SrZr〇3)、鈦酸勰鋇《BaSr)Ti〇3)、鍺鈦、 錫錳碲（SnMnTe)、銻碲（SbTe)、錳酸之鈣镨化物 (Pi^CaxMnO3)、（含銀離子或亞銅離子之碲-銅/釓氧化物、鍺 録)(Te-Cu/ GdOX，GeSb with Ag+ or Cu+)。 於另-實施财，記憶裝置包括第—電極與第二電極以 及介於第-與第二電極間並與其電_接之記憶元件盘緩衝 層，記憶裝置亦包括一或多種金屬之氧化合物。緩衝層具 小於50埃之厚度。 θ ^ 10 15 20 製造記憶裝置方法之一實施例可以下述步驟進行。形成 第-電極與第二電極’形成介於第―與第二電極間並與其電性 耦接之έ己憶體，該記憶體包括一或多種金屬之氧化合物，緩 層包括至少-氧化物或-氮化物。於某些實施例中，緩 介於記憶元件鮮-電極間並與其電性_。 ^ 二，，一，5。埃之厚度。於某些實施例-中實： 層具有-介於約，至約妒歐姆_公分間之電阻率。於= 實施例中…第二緩衝層乃形成於記憶元件與第二_之= 與其電性祕，且第二緩衝層包括至少__氧化物或__氮^並 與可=增嫌_結構鄉，包峨維持性 本發明之結構與方法將於文後料描述，且發明 用以界林發明，本發明之範圍應由申請專利 界疋。、+凡本發明之特徵、目的及優點等將可透過下列 賴式、實施方式及申請專利範圍獲得充分瞭解。°斤 8 25 200915560 【實施方式】 以下說明請配合參考第1至9圖以了解本發明各實施 例。應注意的是，本發明並不僅限於所揭露之實施例，且本發 明可以其他特徵、元件、方法與實施方式來實施。於圖式中二 相同元件乃使用相同編號來代表。 15 20 第1圖為本發明第-實施例之電阻式記憶結構1G之簡化 剖面圖，結構10包括一上方形成有鋁銅(A1Cu)堆疊12之義材 η ’而堆疊12上則形成有一介電層14，其通常是二氧化ς。 下電極16係由堆疊12處延伸通過整個介電層14，且下電極 ^為-導電元件。舉例來說，下電極1δ可以是存取電 =極端或是二鋪之—端。緩制18可職式電衆 漿賤鍍或反應性濺錄等方式形成於介電層14與下電極^ 士’且緩衝層18包括一小於5〇埃之厚度。採用緩衝層18的 m後詳述,。緩衝層18至少包括一氧化物或—氮化 說’緩衝層18可包括至少一種下列之物質：二氧 ^石夕、氧化鎢、氧化鈦、氧化鎳、氧化紹、氧化銅、氧化錯、 以及氮化鈦。緩衝層18之電阻率較佳係介於約1013。至 ,ϊ•公分間’且其厚度較佳係小於5奈米(即50埃）。 來形成。可姻如物理氣她積法或化學氣相沉積法之方法 18 關的記憶元件層2G乃沉積於緩衝層 包括鎮·氧““ 上的金純化合物，特別是 氧化二鶴(W2〇5)、二像疋一種以上的三氧化鶴(w〇3)、五 電衆氧化或埶氧化==(W〇2)。於某些實施例中，像是以 多種不同淡氧化合物產生。於—實施射， 9 25 200915560 右。五乳化二鶴/二氧化鱗，且其厚度為140埃左 電極22 形成於記憶元件層2〇上，而下電極16與上 /是崎呂銅之金屬。此外，下電㈣與上電極 了記'_域 24 ° _件層= 電性相=32部份組成了與下電極％以及上電極22 ^生稿接之雜耕26。記憶元件％可 —氧化一銘、氣化叙、：r备/μ -娜 __ γ m;lAMnG3)、（纽軒紐娜仅^ 於i喿作過程中’施加至下電極16以及上電極22之電壓 3:ί=Γ憶元件26之電流，並誘發記憶元件26 可程式化之變化’而電阻之變化則可用來表示儲存 itf中的資料。於某些實施例中，記憶元件26可儲 存一個位兀或以上之資料。 ⑽第2ff本發明第二實施例之電阻式記憶結構ι〇之簡化 =圖’其與第丨_她不包括_層18，而是包括介於 Ϊ憶=件26以及上電極22間之緩衝層19。第3圖為本發明 式記憶結構1G之簡化剖關，其則包括一 ;丨於下電極16與記憶元件26間之緩衝層18以及一介於上電 極22與記憶元件26間之緩衝層19。 μ ίΓ式記憶結構1G可_傳統之後段製程錄塞製程方 式來製作，且可湘單-遮罩來形錢料19與上電極22。 藉由緩衝層18、緩衝層19或同時採用二者，可增進電阻 式記憶結構H)之絲，靴讀乃配㈣4_8圖予以說明。 200915560 均直徑約為200夺米·上電極電極16係由鶴組成’且其平 約為5〇〇奈米⑽_其平均寬度 厚度約為14G埃；緩衝/8二由，之氧化物所組成，且其 為2太半^ 乃由二氧化伽成，且其厚卢約 構大圖中所顯示之結果乃是以 構大致相同，但不包括任何緩衝層 式之結 為傳統電阻式記憶結構)進行分析所得。隱、、·。構(文後稱 率與維細物峨態之電阻 對數刻度表f_W間(以 顯。相較之下，第5圖φ 特別疋在開啟狀態下最為明 幾乎是平坦電阻率與維持時間所描緣之直線則 憶結構之效能。α本發明大大地改善了傳統電阻式記 15 20 著時間大幅辦加；^不刪疋在開啟或關閉狀態，電阻率均隨 出本發明之電阻式記憶結 卞— 傳統電阻式記憶結構1G之U寫人—人數上，大大地改善了 圖，記憶結構ι〇其電阻率與讀取干擾之關係 態，均Hit之電畴不論是在開啟錢閉之狀 h、有、.、邑佳之讀取干擾特性(讀取 讀取狀態而造成之電阻增減）。卞熳疋U隐兀件26因 雷阳ίΛί為一積體電路110之簡化方塊圖，其包括了呈有 式魏結構ίο之記憶體陣列112。具有讀取、設定與重 25 200915560 設^之字元線解碼器114乃與複數條沿著記憶體陣列1 接i並電性相連。位元線(欄)解碼器118 乃與複數條/σ者陣列中之攔制之位元線m紐相連爭 5 10 15 20 取、设定與重設陣列112中的記憶元件26。位址乃 = '122提供至字元線解碼器及驅動器114與^石ς 118。於方塊124中，包括讀取、設定與纽模式所 及/或電流源的感應放大器與資料輸入結構乃藉由資料匯I 126搞接至位7〇線解碼|| 118。藉由資料輸人線128，資 由積體電路110上的輸人/輸出埠或由積體電路m内部3
1 之ίΐ資專送至方塊124中的資料輸入結構。積體電路 110還可以包括其他電路130，像是一般用途之處理器、I
用途之應用電路或是可提供陣列m所支持之系統單晶 能的模組或其組合。資料透過資料輸出線Π2由方塊12 應放大器傳送至積體電路削上的輸入/輸 J 路110内部或外部之資料目的地。 檟體電 於本實施例中，控制器134係以·調整狀態機構 其係控制偏壓調整供應電壓與電流源136，如讀取、程式化、 ，除、抹除驗證以及程式化驗證電驗/或電流。此外，控 裔134可利用技術領域甲已知的特殊用途電路來實作。於 其=實施方式中’控· 134可包括—般用途之處理器以執行 電腦程式來㈣元件的操作’崎處黯可以實作於相同 體電路上。於另外的實施方式中，控㈣134可利用特殊 邏輯電路與一般用途之處理器的組合來實作。 ” 種鎢-氧化合物\VXOy之形成方法乃是利用物理氣相沉 積法爾或磁控麟法，在丨至丨⑻毫托耳之壓力下配合使用 反應性ll體如魏、魏、減及/或絲#。沉積通常於室 12 25 10 15 20 200915560 =下進行，寬高比1〜5之準直器可絲提升填充之效能。此
At，也可以使用數十到數百伏特之直流偏壓來提升填充之效 此，而直流偏壓可與準直器同步使用。 =積後，可選擇性地在衫、氮氣歧合有氧氣/氮氣 ^ =下進行退火處理’藉以提升金屬氧化物之氧分佈情形。 g火處理之溫度可介於働i ，而處理時間則少於2小 化系種物ΓΑ之形成方法則是利用高溫氧 二、、、仃氧，象疋使用氧化爐或快速熱脈衝(RTp)系统。 ，在嶋歧合魏氣=數 乳堡之私兄下進^丁’而處理時間可從數分鐘至 二dr法則是電漿氧化，其中鹤之表面乃在1至 之壓力下’於純氧、混合錢氣/魏錢合有氬氣 /虱軋/氧軋之環境下，以射頻或直流電衍生 氧化時間可由數秒至數分鐘，氧 =仃。 端視電漿氧化之程度而定。4則可由室溫至3〇叱， 並未====二本發_ 結合而達=本發明之構件 神範嚕。因此，所有此脫ϊ本發明之精 明於隨附申請專利範圍及其均等展，式係忍欲洛在本發 說，在緩衝層與記憶元件電^定的範嘴之中。舉例來 或保護層。狀找紅啊_㈣之過渡層 前述所提及之專利、專利申請案以及各文獻均納入本案 25 200915560 作為參考。 【圖式簡單說明】 第1圖為本發明第一實施例之電阻式記憶結構之簡化剖 面圖，其包括一介於下電極與記憶胞間之緩衝層。 品固第為t發明第二實施例之電阻式記憶結構之簡化剖 面圖，，、匕括一"於上電極與記憶胞間之緩衝層。 10 第3圖為本發明第三實施例之電阻式記憶結構之簡化剖 面圖，其包括一介於下電極與記憶胞間之緩衝層以及一 電極與記憶胞間之緩衝層。 、 第4圖為不包括緩衝層 持時間之關係圖。 之電阻式記憶結構其電阻率與維 第5圖為本發明—實施例之電阻式記餘構其電阻 維持時間之關係圖’由此可看出本發明—實施例 15 20 料維持性。 θ %胃 第6圖為不包括緩衝層之電阻式記憶結構其電阻率與寫 入次數之關係圖。 第7圖為本發明一實施例之電阻式記憶結構其電阻率與 寫入次數之關侧，由此可看出本㈣—實施例具有增進之可 寫入次數。 第8圖為本翻—實施例之電阻式記憶結構其電阻率與 讀取干擾=_®’此可看料㈣—實關不論是在開啟或 關閉之狀態，均具有絕佳之讀取干擾特性。 第9圖為^括電阻式§己憶結構之積體電路方塊圖。 14 25 200915560 【主要元件符號說明】 10 電阻式記憶結構 11 基材 12 堆疊 14 介電層 16 下電極 18、19 緩衝層 20 記憶元件層 22 上電極 24 記憶胞區域 26 記憶元件 110 一積體電路 112 記憶體陣列 114 字元線解碼器 116 字元線 118 位元線解碼器 120 位元線 122 匯流排 124 感應放大器與資料輸入結構 126 匯流排 128 貧料輸入線 130 其他電路 132 資料輸出線 134 控制器 136 偏壓調整供應電壓與電流源 15

Claims (1)

  1. 200915560 十、申請專利範圍·· 1. 一種記憶體裝置，包括： ' 一第一電極與一第二電極；以及 -記憶元件與-麟層’介於該第—與該第二電極之間 5與该第-以及該第二電極電性祕，該記憶元件包括— 之金屬氧化合物，以及 該緩衝層至少包括一氧化物或一氮化物之一。 (2·如申請專職圍第1項贿之記憶體裝置，其巾該緩衝層係 10介於該記憶元件與該第-電極之間，並與該記憶元件以及該 電極電性耗接。 3.如申請專概圍第1項所述之記,_裝置，其巾該緩衝層包 括一小於50埃之厚度。 15 20 二，申請專，範圍第1項所述之記憶體裝置，其中該緩衝層包 括一介於約】〇13至約10i6歐姆_公分間之電阻率。 匕如，5專利範圍第2項所述之記憶體裝置，更包括-第二緩 第—緩衝層係介於該記憶元件與該第二電極之間，並愈 =::::綱_接，且該第二緩衝層至少包括 所述之記憶體裝置’其中該第二緩衝 7.如申請專利範圍第！項所述之記憶體裝i，其中該記憶元件 25 200915560 介於該第一與該第二電極之間的厚度係介於50至1000埃 8·如申請專利範圍第1項所述之記憶體裝置，其中該記憶元件至 少包括一種下列物質：鎢之氧化物(WCg、氧化鎳(Ni〇)、五氧化 二鈮(Nb>2〇5)、二氧化銅(Cu〇2)、五氧化二鈕(Ta2〇5)、三氧化二鋁 (，〇3)、氧化鈷(CoO)、三氧化二鐵(Fe2〇3)、二氧化铪(腦2)、二 氧化欽(Τι〇2)、鈦酸锶(SrTi〇3)、鍅酸鳃（SrZr〇3)、鈦酸锶鋇 ((BaSr)Ti〇3)、錯鈦(GeTi)、錫猛碲(SnMnTe)、録碲(SbTe)、猛酸之 妈镨化物(ΡΓΐ-ΑχΜη〇3)、（含銀離子或亞銅離子之碌_銅/釓氧化 物、鍺銻)(Te-Cu/ GdOX, GeSb with Ag+ or Cu+)。 15 20 9·如申請專利範圍第！項所述之記憶體裝置，射該緩衝層至 。）、氧化銅(Cu〇)、氧化錯(Zr〇)、氣化石夕(蝴4)、氮化 10 括二氧如:：::)範圍第1項所述之記憶體裝置，其中該緩衝層包 11. 一種記憶體裝置，包括： 一第一電極與一第二電極；以及 之金屬氧化合物，以及 接I己K牛包括-種或 該緩衝層包括一小於50埃之厚度。 12.如申清專利範圍第U項所述之記憶 介於該記憶元件與該第-電極之門 :^置，其巾該緩衝層係 《間並與該記憶树以及該第- 17 25 200915560 電極電性耦接。 13，如申請專利範圍第n項所述之記憶體裝置，其中該記憶元件 至少包括一種下列物質：鎢之氧化物(w〇x)、氧化鎳MiO)、五氧 5化二鈮(Nb2〇5)、二氧化銅(Cu〇2)、五氧化二钽(Ta205)、三氧化二 鋁(ai2o3)、氧化鈷(coo)、三氧化二鐵(Fe2〇3)、二氧化铪(Hf〇2)、 二氧化鈦(Τι〇2)、鈦酸锶(SrTi〇3)、鍅酸锶(SrZr〇3)、鈦酸锶鋇 ((BaSr)Ti〇3)、錄鈦(GeTi)、錫錳碲(SnMnTe)、銻碲(SbTe)、猛酸之 約譜化物(Pri-xCaxMn〇3)、（含銀離子或亞銅離子之碲-銅/釓氧化 w 物、鍺銻)(Te-Cu/ GdOX，GeSb with Ag+ or Cu+)。 l4.如申請專利範圍帛11項所述之記憶體裝置，其中該緩衝層包 括一介於約1013至約l〇i6歐姆_公分間之電阻率。 15 j5·如申請專利範圍帛η項所述之記憶體褒置，更包括一第二緩 衝層，該第二_層係介於該記憶元件無帛二電極之間，並與 該§己憶元件以及該第二電極電性輕接，且該第二緩衝層至少包括 一氧化物或一氮化物之一。 / 20 16.如申請專利範圍第15項所述之記憶體裝置，其中該第二緩衝 層免括一」、於5(1檢® ώ： _ 第11項所述之記㈣裝置，其中該記憶元件 "於該第-與该第1極之間之厚度係介於50至_埃。 18·如申凊專利範圍第u項所述之記憶體裝置，其中該緩衝層至 : 、氧化鈦(Ti〇)、氧化 _◦)、 氧化雖K))、氧化銅(Cu0)、氧化錯(zr0)、氮化石夕⑸州、氮化 25 200915560 鈦(TiN) 19.如申請專利範圍帛U項所述之記憶體裝置，其中該 括二氧化矽(Si02)。 2〇· —種製造一記憶體裝置之方法，包括： 形成一第一與一第二電極；以及 (、 15 20 令第猶層，該纖元件触緩衝層係介於 以及如二電極之間，並與該第—以及該第二電極 接’該記憶疋件包括-種或以上之金屬氧化合物，以及 魏衝層至少包括一氧化物或一氮化物之一。 ^ ί申請專利範圍第2〇項所述之方法，其中該緩衝層係以順、、古 式電水、電裝錢鑛或反應性麟之方式形成。抓 22·如申請專利範圍第2〇項所述之方法，苴 漿氧化或熱氧化之方式形成。方m己I件係以電 23.如申請專利範圍第2 記憶元件盥該第一，ικ乃古具甲及緩衝層係介於該 性搞接。 電極之間，並與觀憶元件以及該第-電極電 其中該緩衝層包括一小 柄述之方法， 25 200915560 26.如申請專利範圍第a項所述 層，該第二緩衝層μ & 域弟一_ 記憶元件以件與該第二電極之間’並與該 氧化物或-氮化^ j電_，城第二麟紅少包括一 ’其中該第二缓衝層包括 27.如申凊專利範圍第26項所述之方法 一小於50埃之厚度。 f i8. 料她’2G項所述之方法，其巾該記憶元件介於該 W 弟-與該第二電極之間之厚度係介於5〇至麵埃。 29.如申請專利範圍第20項所述之方法，其中該記憶元件至少包 括-種下列物質：鶴之氧化物(W0x)、氧化錄师0)、五氧化二銳 (Nb2〇5)、二氧化銅(Cu〇2)、五氧化二鈕(Ta2〇5)、三氧化二鋁 15 (^l2〇3)、氧化鈷(Co0)、三氧化二鐵(Fe203)、二氧化铪(ΗίΌ2)、二 氧化鈦(Τι〇2)、鈦酸锶(srTi〇3)、锆酸鰓（SrZr〇3)、鈦酸锶鋇 ((BaSr)Ti〇3)、鍺鈦(GeTi)、錫錳碲(SnMnTe)、銻碲(SbTe)、錳酸之 f 約镨化物(Pr^CaxMnO3)、（含銀離子或亞銅離子之务銅/釓氧化 、 物、鍺録)(Te-Cu/ GdOX, GeSb with Ag+ or Cu+)。 20 30·如申請專利範圍第20項所述之方法，其中該緩衝層至少包括 一種下列物質··氧化鎢(WO)、氧化鈦(Ti0)、氧化鎳(Ni〇)、氧化 銘(A10)、氧化銅(CuO)、氧化锆(Zr0)、氮化矽(Si3N4)、氮化鈦 (TiN) 〇 31·如申請專利範圍第20項所述之方法，其中該緩衝層包括二氧 化矽(Si02)。 20 25
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