TWI327381B - Apparatus, fabrication method and operating method and for non-volatile multi-bit memory - Google Patents

Description

1327381 • Ridge

达达编号号: TW3018PA IX. Description of the invention: m [Technical field of invention] The present invention relates to a non-volatile memory, a method of manufacturing the same, and a method of operation thereof, and in particular to a method suitable for constructing a large size super A component of a small memory system, a method of manufacturing the same, and an operation method. [Before technology] With the increase in the demand for stability, density, and reliability of non-volatile memory components, especially flash memory components, many different components have been introduced. A very useful technique is currently available that rivals dynamic random access memory (DRAM), in which memory cells can be transitioned between two or more states, each state having a characteristic impedance level. The ability to transition between states I can be easily converted to the ability to display two impedance levels, which can easily be equal to a logical value of 〇 or 1. A number of materials are currently available for such memory applications. One of them is a material called a chalcogen compound having at least two solid phases. These Φ materials can produce phase changes by applying a current suitable for the level of the integrated circuit. Generally, the resistance of the generally amorphous solid state is higher than that of the general crystalline solid phase, which can quickly sense the data. These features have been investigated for use as programmable impedance materials to form non-volatile memory circuits that can be read, written, and random accessed. The transition from an amorphous phase to a crystalline phase is generally operated at low currents. Changing from the crystalline phase to the amorphous phase, here as a reset, is typically operated at high currents. 'It includes a short, high current density pulse to melt or destroy the crystalline junction. 5 1327381 * ♦

The three-week: TW3018PA. After that, the phase change material cools quickly, terminating the phase change procedure, allowing at least a portion of the phase change structure to stabilize in an amorphous state. It is generally desirable to make the change current of the phase change material from a crystalline state to an amorphous state as small as possible. The magnitude of the reset current can be reduced by reducing the size of the phase change material unit in the memory cell in order to achieve a higher current density by varying the material unit with a small absolute current value. The current development direction is to form small holes in the integrated circuit structure, and then fill the small holes with a small amount of stylized impedance material. Patents relating to the development of small holes include: U.S. Patent No. 5,687,112, issued on November 11, 1997 by Ovshinsky, entitled "Multi-bit cell memory cells with tapered contact windows"; Zahorik et al. U.S. Patent No. 5,789,277, entitled "Memory Element of Chalcogenide", August 4, 1998; Doan et al., entitled "Controllable Ovnic Phase Change Semiconductor Memory Element" on November 21, 2000 U.S. Patent No. 6,150,253. φ Variations in the manufacture of small-sized components and in strict compliance with the strict specifications of large-scale memory components can cause problems. Furthermore, as the capacitance increases, The size of components has shrunk, and the industry has reached a field that is physically limited, such as atomic size, thus hindering future development. Therefore, it is necessary to continue to develop a better technique to increase the memory efficiency with reduced pitch. The present invention provides a memory element and a method of fabricating the same that can increase the efficiency of a memory with a reduced pitch. 6 1327381 ,

Sanda Number: TW3018PA The present invention provides a method of manufacturing a memory element that can increase the efficiency of a memory with a reduced pitch. * The present invention provides a method of operating a memory element that can increase the performance of the memory with a reduced pitch. One aspect of the present invention is to provide a memory element that selectively displays first and second logic levels. A first conductive material having a first surface and having a first memory layer thereon. A second electrically conductive material having a second surface and having a second memory layer thereon. A connecting conductive layer connects the first and second memory layers and is in electrical contact. The cross-sectional area of the first memory layer of the structure is smaller than the cross-sectional area of the second memory layer. The present invention provides a method of selecting a logic state of a memory cell that extends between bit lines bl and b2 and has RRAM cells at right angles to each other, the RRAM cell being composed of an L-type conductive bonding member, and The cross-sectional area of one of the first memory layers is smaller than the cross-sectional area of the second memory layer. The method includes: applying a voltage Vi to the bit line bl, and applying a voltage V2 to the bit line b2, wherein the voltages V! and V2 exceed the reset voltage of each memory cell; and by applying a selection Levels Vi and v2 select one of the first, second, third, and fourth memory unit logic levels. The invention further provides a memory element comprising a first conductive material, a second conductive material and a first conductive material connecting the conductive layers 0, having a first surface having a first memory layer thereon; and a second conductive material having a second surface having a second memory layer thereon. The first and second memory layers can selectively display the first and second logic levels, each logic level corresponding to one of the layers 7 1327381 * >

Sanda number: TW3018PA Electro-optical impedance. The cross-sectional area of the first memory layer is smaller than the cross-sectional area of the second memory layer. A conductive layer is bonded to connect and electrically contact the first and second memory layers. The present invention provides a memory device comprising a second plug, a common source line, a conductive material, two first memory layers, two second memory layers, two interconnected conductive layers and bit lines. Two plugs, located on the substrate. Common source line, located between the two plugs. Two word lines are located between each plug and the common source line. The conductive material is located above the common source line and the two-character line, and is electrically connected to the common source line. Two first memory layers are respectively located on the surface of the two plugs. The second memory layers are respectively located on sidewalls of the first conductive material, and each of the second memory layers has a cross-sectional area larger than a cross-sectional area of each of the second memory layers. The two connecting conductive layers respectively connect and electrically contact the first and second memory layers to form a memory unit. The bit line is electrically connected to the first conductive material. The invention further provides a memory unit comprising at least one word line, a dielectric layer, a plug, a common source line, at least one conductive material, a first memory layer, a second memory layer, a bonded conductive layer and a bit line. The word line is on the substrate. The dielectric layer is on the substrate. A plug and a common source line are respectively located in the dielectric layers on both sides of the word line. The conductive material has a cross section and is located on the dielectric layer and electrically connected to the common source line. The first memory layer is located on and electrically in contact with the surface of the plug. The second memory layer is located on and in electrical contact with the cross section of the conductive material, and the second memory layer has a cross-sectional area larger than that of the second memory layer. The conductive layer is connected to electrically connect the first and second memory layers. The bit line is electrically connected to the conductive material layer. In order to make the above description of the present invention more comprehensible, a preferred embodiment will be described hereinafter with reference to the accompanying drawings, as follows: 8 1327381 * ¥

Sanda number: TW3018PA [Embodiment] The multi-dimensional memory cell, array and manufacturing method of the memory cell will be described in detail with reference to Figs. 1 to 6 as follows. Figure 1 is a diagram showing an embodiment 100 of a memory cell having memory cells 10a, 100b in response to the needs of the appended claims. As with conventional memory cell designs, the memory cells illustrated and discussed herein are only part of a larger memory circuit in which memory cells 100a and 100b form memory cells 100. Memory cells are arrayed to control access, and a complete memory unit may contain more than one billion memory cells. Circuitry other than the memory unit is not within the scope of the invention. A typical memory circuit can be found in U.S. Patent Application Serial No. 1 " 155,067, entitled "Thin Film Melt Phase Change Random Access Recorder and Method of Making Same", the Applicant being the same as the present application, the contents of which are incorporated herein by reference. The memory cell 100 is constructed on the underlying structure 101, which is a conventional common source memory array structure. The structure is described in detail below, but it is worth noting that the unit is a structure in which the plane symmetry surrounds the axis of the common source line 108. Each half is equivalent to a single memory cell structure. In a conventional common source structure, each cell structure includes a word line 106 and a plug member 104. The plug member 104 is preferably formed of a heat resistant metal such as tungsten. Other suitable heat resistant metals include Ti, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru, and their oxides and nitrides. For example, TiN, RuO or NiO is a known useful heat resistant metal. The preferred word line 106 is polycrystalline germanium, metal germanide or 9 1327381 4 ψ

Sanda number: TW3018PA • Similar materials to form. These components are buried in a conventional inner dielectric layer/internal metal dielectric layer (ILD/IMD). As is conventionally known, these materials are preferred to have a low dielectric constant, and a preferred material is cerium oxide or a similar material. In the illustrated embodiment, the structure covering the common source layer is above the center of the metal layer 120, which can be metallized using copper. Other metals, including aluminum, titanium nitride and tungsten-based materials, can be used. In addition, non-metallic conductive materials such as doped polysilicon can also be used. The metal layers are located between the SiN layers 118' above and below the metal layers, respectively. This will be explained in more detail below. The three-layer assembly extends to near, but does not cover, the plug member 104. Furthermore, the SiN material does not cover the metal layer. The thickness of the metal layer is preferably between 10 and 2 Å, more preferably about 20 nm. The thickness of the two SiN layers is preferably between 2 Å and 1 〇〇 nm. More preferably, the 疋 is about 3 〇 nm. φ 忆 Π〇 and U2 are respectively disposed on the top surface of each plug member and the side wall of the metal layer. The composition of these material layers will be explained as follows. The shape is flat, and its thickness ranges from 2 nm to 300 nm, preferably about 1 Onm. Each of the 圯 It layers 11 〇 112 is formed using a material having at least two stable impedance levels, which is referred to as a resistive random access memory RRAM material. Currently, several materials have been proven to be useful in the fabrication of RRAM, as explained below. The melonized δ species group is an important RRAM material. The chalcogen element includes four elements of oxygen, sulfur, antimony and bismuth in the elements of the sixth group of the periodic table. 1327381 * ψ

Three M: TW3018PA. Any one of them. The sulfur eyebrow compound includes a chalcogen element and a compound of a cationic radical of eleCtr〇P〇SitiVe. Chalcogenide alloys include chalcogenides and other materials such as transition metal combinations. Generally, chalcogenide alloys include - elements of the sixth group of various periodic tables, such as bismuth and zinc. Generally, the chalcogenide alloy includes a combination of one or more of bismuth (external), marry (Ga), indium (In), and silver (Ag). Since the chalcogenide compound can include two solid phases and each has a characteristic impedance, a double memory characteristic can be achieved, and therefore, these materials are referred to as 'phase-to-gastric changes, materials or alloys. A variety of phase change memory materials have been disclosed in the scientific literature, including alloys of Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/. Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te, and Te/Ge/Sb/S. In the Ge/Sb/Te alloy population, the range of alloy compositions that can be implemented is very broad. Its composition can be expressed by TeaGebSbn^a+w. Researchers have studied that most of the useful φ alloys have an average concentration of Te in the deposited material of preferably less than 70%, typically less than 60%, and typically range from about 23% to 58%, more preferably. It is 48% to 58Λ. The average concentration of Ge in the material is greater than 5%, which ranges from 8% to about 30%, typically less than 50%. Preferably, the concentration of Ge ranges from about 8% to about 40%. The main constituent element remaining in the composition is Sb. These percentages are atomic percentages, and the atoms of all of the constituent elements are 100% (0vshinsky '112 patent, lines 10-11). Specific alloys studied by other researchers include Ge2SbTe5, GeSb2Te4, and GeSb4Te7. (Noboru Yamada, high data rate record 1327381 • ·

Sanda number: Potential of Ge-Sb-Te phase change optical disc of TW3018PA, SPIE 3109, pp. * 28-37, 1997). In general, the transition metal is, for example, chromium (Cr), iron* (Fe), nickel (Ni), and niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys thereof, which can be combined with Ge/Sb/Te. A phase change alloy with anti-stylulation properties. Specific examples of memory materials that can be used are described in lines 11-13 of the Ovshinsky '112 patent, examples of which are incorporated herein by reference. In the local order of the active channel region of the memory cell, the phase change alloy can be The transition between the first structural state and the second structural state is a material that is generally amorphous solid; the second structural state is a generally crystalline solid material. Some of these alloys are at least bistable. "Amorphous" means a structure having a relatively low order of order, which has a property comparable to that of a single crystal, such as a higher resistance than a crystalline phase. "Crystalline" means a structure with a relatively high order, which is more ordered than amorphous, and has detectable properties such as lower electrical resistance than amorphous phase. "A typical phase change material can be completely amorphous and fully crystallized." The transition between the detectable states of the local range of the entire spectrum between states. Other properties of materials that affect the amorphous and crystalline phases include the arrangement of atoms; the density of free electrons and the activation energy. The material can be converted to a different solid phase, or converted to two or more solid phases, providing a gray scale between the fully amorphous and fully crystalline states. The electrical properties of the material also change. Phase change alloys can be changed from one phase to another by the application of electrical pluses. Short, high amplitude pulses can cause the phase change material to change to a generally amorphous state. Long, low amplitude pulses can be 12

Sanda number: TW3018PA to make the phase change material change the β β 夂 一般 general crystal phase. Short, high-amplitude veins = crystal-structured bonds; short enough to avoid atomic re-knots / (10) applied to specific phase-change alloys based on experience or mode. In the following content, the phase change is expressed in GST, and other types of phase change materials can be used. The material used for PCRAM here is Ge2Sb2Te5 〇 « ', and other programmable resistance materials can also be used. One of these materials is a giant magnetoresistance (cmr) resistive material that can significantly change the impedance level in the presence of a magnetic field. Some of these materials are usually perovskite oxides (per〇vskite 〇xide) and can change their impedance under a magnetic field of a certain fem. When applied to RRAM, its preferred chemical formula is PrxCayMn03, where χ: y = 〇 5: 〇 5, or other composition is X: 0~l; y: 0~1. Other CMR materials including Μη oxides can also be used. • Other RRAM materials are two-element compounds such as Nix〇y,

TixOy > AlxOy, wx0y, Znx〇y, Zrx〇y, CuxOy, etc., where x: y = 0.5: 0.5. Or, the other components are: 〇~1; y: 〇~1. Alternatively, a doped polymer may be used, the doping of which is, for example, copper, C60, silver, the polymer of which is, for example, 7,7,8,8-tetracyanoquinonedioxane (TCNQ), [6, 6] phenyl C61 butyrate (PCBM), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCVQ, TCNQ doped with other metals, or any other bistable or multi-stable impedance A polymeric material that can be controlled by electrical pulses. 13 1327381

Three hall number: TW3018PA floor. Second, its r:-·- type has excellent adhesion. Second, the conductivity: said; change: the characteristic of the barrier, especially in the temperature rise, the second, the diffusion barrier material or the whole family (four) ιΓΓ ^ in the metal, for example, the preferred material for the intercalation::====:=

AbTa, Cu, pt, Ir, La, Ni, and the like. A preferred barrier layer is a width 1 112 that traverses the plug member. Preferably, the face of the glazing layer is completely covered with the metal layer m and the dielectric material layer 116, the barrier layer 114, which may be selected from the material of the inner dielectric layer 124. This film layer serves as a spacer for the alignment of the barrier layer m, which is more clearly illustrated in Fig. 6e. The inner metal dielectric layer 124 envelops the memory cell' preferably comprises a diamine in the dioxide, a nitrogen cut or other dielectric fill material. In the embodiment, the planarization is planarized, preferably by a chemical mechanical polishing process, to provide a flat surface for the underlying material layer of the human bit line 122 on the top surface of the inner metal dielectric layer. It extends into the inner metal dielectric layer to connect the metal layer 12 through the via window 123. This layer can be in contact with other portions of the memory circuit, as is known to those skilled in the art, and will not be described herein. This member can be formed using any of the known materials. In one embodiment, the material of the bit line is a Ti compound, for example 1327381 •

Sanda number: TW3018PA. TiN' or n+ polycrystalline stone or a multilayer material comprising a titanium layer, such as a TiN/W/TiN three-layer material, or a similar structure TiN/Ti/A1/TiN material. The equivalent circuit of the structure of Fig. 1 can be represented by Fig. 2. The two resistors 1^ and & are connected in series between the bit lines 31^ and BL2. The voltage applied to the bit line is represented by Vbl and Vb2, respectively. The voltage drops of the two resistors R and R2 are 乂丨 and v2. Thus the voltage drop between the two bit lines is Vb2-Vbl, which is equal to VfVa. As shown, the area of the RRAM cell &amp is smaller than the area of the cell R2. Therefore, the impedance Ri will be greater than R2. Table 1 status / value

Ri r2 Memory Cell Reset Reset 0 Reset Setting 1 δ and 疋 Reset 2 Setting Setting 3 The state combination of RRAM and the result of its memory cell value are shown in Table 1. The memory cell value corresponds to all relative impedance values. It is worth noting that the embodiment shown in Table 1 adopts a "small-endian" structure. That is, the last unit is the least significant digit (LSD) and the first unit is the most significant digit (MSD). Other embodiments may employ a "big-endian" mode in which the digits are reversed, the procedures described below are the same, but the two memory cells are reversed. The relationship between the state of each memory cell is shown in Fig. 3a-3d. Drawing 3a 15 1327381

Sanda number: TW3018PA shows the memory cell having the first memory cell unit 112 and the conductive resistance barrier layer 114 and the second memory cell unit 110. Here, both units are in a reset state with a low resistance value. If R represents the resistance of the larger RRAM cell 112, the resistance of the other cell 110 is a fixed value f relative to cell 112. In the illustrated embodiment, the impedance of unit 110 is higher than unit 112, and therefore, the fixed value f is greater than 1, but in other embodiments, it can be described in the reverse manner. The value of f determines the space in which the component operates, that is, the allowable change in resistance. When the component is operating, the f value is sufficient for 2-bit operation. As described above, in the embodiment of Figs. 3a-3d, the results show that two RRAM cells of different sizes produce different impedances. Among them, the smaller unit has a higher impedance. In other embodiments (not shown), the two cells can use different materials to produce impedances that are equally different. The structural differences between the two embodiments do not affect the description of their relationship to each other, but the difference is still expressed by a fixed value f. In this embodiment, the two RRAM cells are approximately the same thickness (described in detail later) but differ in width to produce different impedances. The two RRAM cells are connected in series, so the impedance of the entire memory cell can be expressed as R+fR or (1 +f) R. The lower order unit 112 is converted to a set state having a higher impedance level as shown in Fig. 3b. Here, the impedance level is increased by a ratio of a fixed value η. Different materials have different values depending on the particular compound or optional characteristics, but the relationship between the reset and set state of a given material, as shown in Figure 3b, can be expressed as R->nR. Therefore, the state shown in Fig. 3b can be expressed as Han + nR or (n + f) R. 1327381 I t

Triple M: TW3018PA Similarly, Figure 3c shows a schematic diagram of the result of the RRAM cell 110 transitioning to the set state; and the cell 112 maintaining the reset state. In the illustrated embodiment, the two cells are formed of the same material, and the fixed value η represents the difference between the set and reset states, and its resistance can be expressed in nfR. It can represent the resistance of the memory cell by (1+nf) R. Finally, Figure 3d shows the result of the RRAM cells 112 and 110 transitioning to the set state, producing R-nR and fR-nfR transitions. Its state can be expressed as nR+nfR, or n (1+f) R. The relationship of these four memory cell values can be expressed in Table 2 below. Table 2 Relationship of memory cell values Memory cell value (1+f) R 0 (n+f) R 1 (1+nf) R 2 n (1+f) R 3 It is worth noting that η value and f value Choose n=100 and f=2 respectively. These values produce all of the resistance values 3R, 102R, 210R, and 300R shown in Table 1. Applying a voltage to the bit lines BI^ and BL2 sets the memory cell to the desired value (Fig. 2). All four voltage values are sufficient to achieve all of the possible values in Table 1. Those skilled in the art will appreciate that there are many possibilities for actual voltage. In one embodiment, two positive voltages (positive with respect to Vbl at Vb2) and two negative voltages are used, the resulting voltages being expressed as Vhigh, Vlow, -Vhigh, and _Vl〇w. The absolute value of the applied voltage is related to the memory unit's characteristics: TW3018PA, and its associated properties include the materials and dimensions used. In the embodiment shown, the effective high value is 3.3 volts and the low value is 1.5 volts. First, the most critical program is a general reset (RESET), which causes two RRAM cells to go into a reset state, producing a memory cell value of zero. This procedure is shown in Table 3 below. Table 3 is all changed to reset, early morning, memory cell action tr9 —· early memory state state cell Ml 1 3 |Vi |>VRESET 0 0 M2 1 |V2|>VreSET 0 (Vb2~Vbi) = -Vhigh

As shown, the appropriate voltage for this transition is -VHIGH, which allows the absolute values of the voltage drops of Vi and V2 to exceed the reset value, respectively. In the two RRAM cells in the reset state, the total value of the memory cells is zero. The reset state is the starting point for all further operations. Since the transition between the intermediate states may have unpredictable results, it is preferable to return the cell to the reset state, and the memory cell value of the state opposite to the first step of the operation of changing the state is 3, as follows Table 4 shows. Table 4 0~3 transition early 兀 state memory cell action early 兀 state memory cell Ml 0 0 Vi>Vset 1 3 18 1327381

· A

Sanda number: TW3018PA M2 0 V2>VsET 1

(VB2_VB1) = VHIGH The Vhigh voltage applied here is sufficient to cause the two early elements to produce a voltage drop that exceeds VSET. When the two units are in the set state, the memory cell value is two bits 11 or 3. The procedure for generating the memory cell value 2 is shown in Table 5 below.

Table 5 0~2 transition early memory cell action XJVt — early memory state state Ml 0 0 V 1>VseT 1 2 M2 0 V2<VsET 0 (VB2-VB1) =VL〇w In this setting state, The pressure drop Vi is greater than the pressure drop required to produce the set state. Therefore, R! is the setting, but the pressure drop V2 is less than the set demand, and the remaining unit is in the reset state. I is in the set state, and the result of R2 in the reset state will cause the memory cell value to be two-dimensional οι or 2. Table 6 below is an illustration showing the generation of a memory cell value of 1. Achieving a value of 1 is more difficult than other transitions. It is obvious that if two units are reset at the beginning, a voltage sufficient to generate a set state at V2 must also be set to V!, and the resulting value is 3. Not 1. The solution is to return the memory cell to the fully set state, as shown in Table 3 above. Then, from memory 19 1327381 « *

Sanda number: TW3018PA At the beginning of cell value 3, the electric dust applied to -Vl〇w is sufficient to generate a reset at Ri' instead of R2, resulting in a memory cell value of double bit 01 or 1. Table 6 is changed to 3-1 - early memory cell action mouth one early memory state state cell Ml 1 3 |Vi|>Vreset 0 1 M2 1 |V2|<Vreset 1

(Vb2-Vbi) =-Vl〇W

The voltage-current characteristics of the memory cell of Fig. 1 are as shown in Fig. 4. In the figure, there are two curves, one is the transition from reset to set; the other is the opposite situation. The resulting current flowing through the memory cell 100 is as shown in Fig. 5. For the sake of clarity, only one of the units will be explained. As indicated by the arrows, current flows from the underlying circuitry via the plug member 104 to the memory unit. Then, the current passes through the memory layer 110, the barrier conductive layer 114, and the second memory layer 112. Of course, as explained above, the amount of current is regular in accordance with the impedance state of each memory layer. Current then passes through the metal layer 120 and flows outward through the bit line 122 to the memory circuit. In accordance with the principles described above, an embodiment of a method of fabricating a memory cell is illustrated in Figures 6a-6i. Referring to Fig. 6a, the underlying structure 101 is formed in a conventional manner, and the specific structure is as described above. For the sake of clarity in the following description, the same symbols are no longer weighted in the components of the underlying structure in the following figures. 20 1327381 • ♦

Sanda number: TW3018PA Double standard. Figure 6b illustrates the deposition of two barrier/insulation layers ii8a and 118b and a metal layer 120 therein. This process is preferably carried out using conventional chemical vapor deposition techniques. Then, patterning and trimming are performed by a conventional technique to form the structure shown in Fig. 6c. Figure 6d illustrates the formation of RRAM cells 112 and 11 〇. Each of the RRAM cells is formed by oxidizing the material of the metal layer 120 and the plug unit 104, respectively. Preferably, a plasma oxidation process is employed with a variable ratio of oxygen and nitrogen as a gas source. It is known that this process can be either direct or indirect, in which a downstream plasma is generated in a microwave generator and injected into the reaction chamber by a waveguide. In either case, the required power range is 800 to 3000 watts, for direct processes, the chamber pressure range is 1 〇 to 5 Torr; for indirect private 乂' chamber pressure range is 1 〇 〇〇 to 3000 Torr. The ratio of oxygen and nitrogen as described above may be from 1:1 to 100% oxygen, preferably from 9:1. The chamber temperature ranges from room temperature to 250 degrees Celsius, preferably 200 degrees Celsius. The time of the process is related to the thickness of the oxidized metal, preferably about 400 seconds. This process forms two RRAM cells in an l-type pattern as shown in Figure 6e. The actual dimensions of these components are related to the size of the metal layer 120 and the plug member 104 because these members are oxidized there. The thickness of this member is related to oxidation or other processes, as is known. RRAM cells are electrically contacted through conductive layer 114, conductive 21 1327381

* I Sanda number: TW3018PA Layer 114 is L-shaped' it covers the first RRAM cell ιι and is in the second direction (preferably about 9 degrees relative to the first direction RRAM cell 112 ' Conductive layer 114 can In the embodiment, the conductive layer is formed by using a germanium compound, such as ΤιΝ or n+ polycrystalline stone, or formed of a plurality of layers of materials, for example, TiN/Ti/Al/TiN material. The L-type layer 'such as the conductive layer 114' may be any one known to the well.

In the implementation of the method, the conformal conductive material is deposited on the entire barrier layer/metal layer 2G structure. Then, a material 116 is deposited on the barrier material. Next, a photoresist material is applied over the fL-type layer 114 in the oxidized material 116, and the oxidized material and the barrier material are removed by a two-step process. Both of these steps can be performed using a reactive ion bombing procedure for the anisotropic side. The preferred step of the compound is to use a gas-containing chemical such as ACF4 or F4C. In the case of TiN barrier materials, it is preferred to have a gas-containing process; 歹J such as 疋Cl2, BC13, and other conventional gas-containing chemicals. Since the materials of the material layers have significant differences, it is preferable to use the end point measurement and control method. Although the specific material has a suitable velocity, it can be etched by time control. It is worth noting that the preferred oxide and TiN are over etched to create a drain circuit control from the residual TiN. Similarly, by increasing the anisotropy, the shape of the L-type layer 114 can be ensured, e.g., by reducing the pressure of the chamber, increasing the plasma bias, or adjusting the rate of the polymer protective layer. In Figure 6f, the memory cells are covered by a dielectric fill material 124. This material 22 1327381

The Sanda number: TW3018PA layer may be selected from materials used as the inner dielectric layer/internal metal dielectric layer 102, or some equivalent materials known in the art. The dielectric filler material preferably comprises a dioxide dioxide, a polyaramine, a nitride or other dielectric filler material. In an embodiment, the dielectric fill material includes relatively good insulating properties for heat and electricity to achieve thermal and electrical insulation of the bridge. Figures 6g and 6h depict the formation of a joint member that is electrically connected to the portion of the circuit below the memory cell. First, referring to Fig. 6g, a via hole 121 is formed in the dielectric material 124, and the via is extended from the upper surface of the dielectric layer via the barrier/insulating layer 118 to be in contact with the metal layer 120. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

23 1327381 * »

Sanda number: TW3018PA [Simple description of the drawing] Fig. 1 illustrates an embodiment of a memory unit as claimed in the patent application. " Fig. 2 is a schematic view showing the circuit of the element shown in Fig. 1. Figures 3A-3D illustrate the impedance values of the logic states achievable by the components shown in Figure 1. Fig. 4 is a graph showing the relationship between voltage and current of the element of Fig. 1. Fig. 5 is a view showing a state in which the current of the element of Fig. 1 flows. 6A-6H are diagrams showing the manufacturing process of the memory element of Fig. 1. [Main component symbol description] 100: Embodiment 100a, 100b: Memory cell 101 Lower structure 104 Plug member 106 Word line 108 Common source line 110, 112: Memory layer 118: SiN layer 114: Barrier layer 116: Dielectric material 118a, 118b: barrier layer / insulating layer 120: metal layer 122: bit line 124: dielectric filling material 24

Claims (1)

2010/3/18 Amendment, Patent Application: A memory element comprising: a memory layer; the first conductive material has a first surface having a first-second conductive material having a second surface Recalling the layer; and /, having the first 5 touches ^^ conductive layer 'connected (four) first - and the second riding and electrically connected ==: r straight: (four) pieces, and the first memory layer has one The cross-sectional area of the cut. The area is smaller than the second memory layer. 2. The memory layer optionally displays the first and second logic levels as described in the application. The component of claim 5, wherein each component = displays a logic level according to a voltage level selected by the memory component. π弟一4. As stated in the 利β& The component of claim 4, wherein the first logic level corresponds to the impedance level of the component is (i+f) R, and the function of the thickness of the gap is 'and 11 is the first memory The resistance of one of the layer and the second hidden layer. 6. The component of claim 4, wherein the second 25 1327381 2010/3/18 amendment* » * I logic level corresponds to the impedance level of the component is (n+f) R, where f η is a function of the thickness of a dielectric spacer, η is a function of the material of the component, and R is the resistance of one of the first memory layer and the second memory layer. 7. The component of claim 4, wherein the third logic level corresponds to an impedance level of the component of (1+nf) R, where f is a function of a thickness of a dielectric spacer, η Is a function of the material of the component, and R is the resistance of the eleventh of the first memory layer and the second memory layer. 8. The component of claim 4, wherein the fourth logic level corresponds to an impedance level of the component of n (1+f) R, where f is a function of a thickness of a dielectric spacer, n is a function of the component material, and R is the resistance of one of the first memory layer and the second memory layer. 9. A method of selecting a logic state of a memory cell, the memory cell extending between bit lines bl and b2 and having RRAM cells at right angles to each other, the RRAM cell being comprised of an L-type conductive bonding member, and wherein The cross-sectional area of a first memory layer is smaller than the cross-sectional area of a second memory layer. The method includes: applying a voltage V! to the bit line bl, and applying a voltage V2 to the bit line b2, the voltage Vi And V2 exceeds the reset voltage of each of the memory cells; and by applying a selected level 乂! And V2, selecting one of the first, second, third, and fourth memory unit logic levels. 10. The method of selecting a logic state of a memory cell as described in claim 9 wherein the memory cell logic level is changed from a reset logic level to a two-dimensional logic level 3 by The bit line is applied with an electric 26 1327381 2010 with a correction pressure of 18 such that the voltage of each of the memory layers exceeds the vSET of each layer. 11. The method of selecting a logic state of a memory cell as described in claim 9 wherein the memory cell logic level is changed from a reset logic level to a two-dimensional logic level 2 by The bit line applies a voltage such that the voltage of the first memory layer exceeds the VSET of each layer and the voltage of the second memory layer is less than the Vset of the layer. 12. The method for selecting a logic state of a memory unit according to claim 9, wherein the memory unit logic level is changed from a two-dimensional logic level 3 to a two-dimensional logic level 1, A voltage is applied across the bit line such that the absolute value of the voltage of the first memory layer exceeds the VRESET of each layer and the absolute value of the voltage of the second memory layer is less than the Vreset of the layer. The memory element comprises: a first conductive material having a first surface and having a first memory layer thereon; a second conductive material having a second surface and having a second memory layer thereon; Each of the memory layers can selectively display first and second logic levels, each logic level corresponding to a known electrical impedance of the layer; and a bonding conductive layer connecting the first and second memory layers And electrically contacting, the connecting conductive layer is an L-shaped member, such that the first memory layer and the second memory layer are at right angles to each other; wherein a cross-sectional area of the first memory layer is smaller than a section of the second memory layer area. 27 1327381 2010/3/18 Amendment» » t 14. The memory element of claim 13 wherein the logic level of the memory layer is selected from the first, second, third and fourth logic Level. 15. The memory device of claim 14, wherein the first logic level corresponds to a component impedance level (1+f) R, where f is a function of a thickness of a dielectric spacer, and R The resistance of one of the first memory layer and the second memory layer. 16. The memory device of claim 14, wherein the second logic level corresponds to an impedance level of the component of (n+f) R, where f is a function of a thickness of a dielectric spacer, η is a function of the material of the component, and R is a resistance of one of the first memory layer and the second memory layer. 17. The memory device of claim 14, wherein the third logic level corresponds to an impedance level of the component of (1+nf) R, where f is a function of a thickness of a dielectric spacer, η is a function of the material of the component, and R is a resistance of one of the first memory layer and the second memory layer. 18. The memory device of claim 14, wherein the fourth logic level corresponds to an impedance level of the component of n (1+f) R, where f is a function of a thickness of a dielectric spacer , η is a function of the material of the component, and R is a resistance value of one of the first memory layer and the second memory layer 0 28 1327381 It is revised, and it is revised. 1327381 Proposal No. 095139862 in the 2010/3/18 patent 114 Circle 3A 114 Figure 3B 1327381 2010/3/18 Patent Application No. 095139862 Amendment 114 Figure 3C 114 3D Figure 1327381 /] /3⁄4 2010/3/18 Patent Application No. 0951398K Amendment 100 122 number 5 1327381 FiW month / Tw complex) is replacing page 2010/3/18 Patent Application No. 095139862 Section 6A ILD/IMD 118a 120 118b Section 6B 1327381 2010/3/18 Patent Application No. 095139862 6C round 104 6D匮 1327381 2010/3/18 Patent Application No. 095139862 Amendment 120 118 112 Figure 6E 124 Figure 6F 1327381 Monthly replacement (provisional) replacement page 2010/3/18 Patent Application No. 095139862 Amendment 118 121 120 124 Figure 6G 123 122 Figure 6H