TW200820469A - Apparatus, fabrication method and operating method and for non-volatile multi-bit memory - Google Patents

Abstract

A memory device that selectively exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-section area less than that of the second memory layer.

Description

2〇〇82_〇469tw3〇18pA IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory, a method of manufacturing the same, and a method of operating the same, and in particular to a suitable construction A component of a large-sized ultra-small memory system, a method of manufacturing the same, and an operation method. [Prior Art] With the increase in demand for stability, density, and reliability of non-volatile memory elements, particularly flash memory elements, many different components have been introduced. There is a very useful technique for competing with dynamic random access memory (DRAM), in which the memory cells can transition between two or more states, each state having a characteristic impedance level. The ability to transition between states can be easily converted to the ability to display two impedance levels, which can easily be equal to a logical value of 〇 or 1. A number of materials are currently available for such memory applications. One of them is a material known as a chalcogen compound having at least two solid phases. These materials can produce phase changes by applying a current suitable for the level of the integrated circuit. Generally, the resistance of the generally amorphous solid state is higher than that of the general crystalline solid phase, which can quickly detect no data. These features have been investigated for use as programmable impedance materials to form non-volatile memory circuits that can be read, written, and random accessed. The transition from an amorphous phase to a crystalline phase is generally operated at low currents. Changing from the junction phase to the amorphous phase, here as a reset, is typically operated at high currents. 'It includes a short, high current density pulse to melt or destroy the crystallographic junction 5

After rW3〇18PA 200820469, the phase change material cools quickly, terminating the phase change procedure, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is generally desirable to make the change current of the phase change material from a crystalline state to an amorphous state as small as possible. The magnitude of the reset current can be reduced by reducing the size of the phase change material unit in the memory cell in order to achieve a higher current density by varying the material unit with a small absolute current value. The current development direction is to form small holes in the integrated circuit structure, and then fill the small holes with a small amount of stylized impedance material. Patents relating to the development of small holes include: U.S. Patent No. 5,687,112, issued on November 11, 1997 by Ovshinsky, entitled "Multi-bit cell memory cells with tapered contact windows"; Zahorik et al. U.S. Patent No. 5,789,277, entitled "Civil Compound Memory Element," was approved by Doan et al. on November 21, 2000 as "Controllable Ovnic Phase Change Semiconductor Memory Element". U.S. Patent No. 6,150,253. The variation in the manufacturing process of small-sized components and the strict specifications of large-scale memory components can cause problems. Furthermore, as the capacitance increases, the component size As the industry shrinks, the industry has reached a field that is limited by physical limitations, such as atomic size, thus hindering future development. Therefore, it is necessary to continuously develop a better technique to increase the efficiency of memory under reduced pitch. The present invention provides a memory element and a method of fabricating the same that can increase the performance of a memory with reduced pitch.

rW3018PA 200820469 ---- A V ... The present invention provides a method of fabricating a memory element that can increase the performance of the memory with a reduced pitch. SUMMARY OF THE INVENTION The present invention is directed to a method of operating a memory device that can increase the performance of a memory with reduced spacing. One aspect of the present invention is to provide a memory element that selectively displays first and second logic levels. A first conductive material having a first surface and having a first memory layer thereon. A second electrically conductive material having a second surface and having a second memory layer thereon. A connecting conductive layer connects the first and second memory layers and is in electrical contact. The cross-sectional area of the first memory layer of the structure is smaller than the cross-sectional area of the second memory layer. The present invention provides a method of selecting a logic state of a memory cell that extends between bit lines bl and b2 and has RRAM cells at right angles to each other, the RRAM cell being composed of an L-type conductive bonding member, and The cross-sectional area of one of the first memory layers is smaller than the cross-sectional area of the second memory layer. The method includes applying a voltage Vi to the bit line bl and applying a voltage V2 to the bit line b2, wherein the voltage Vi*V2 exceeds a reset voltage of each memory cell; and by applying a selected level 乂! And V2, selecting one of the first, second, third, and fourth memory unit logic levels. The invention further provides a memory element comprising a first conductive material, a second conductive material and a bonded conductive layer. The first conductive material has a first surface and has a first memory layer thereon; the second conductive material has a second surface and has a second memory layer thereon. The first and second memory layers can selectively display the first and second logic levels, and each logic level corresponds to one of the layers. 7 200820469

A violation m · rW3018PA Electro-optical impedance. The cross-sectional area of the first memory layer is smaller than the cross-sectional area of the second memory layer. A conductive layer is bonded to connect and electrically contact the first and second memory layers. The invention provides a memory device comprising a second plug, a common source line, a conductive material, two first memory layers, two second memory layers, two connected conductive layers and bit lines. Two plugs, located on the substrate. Common source line, located between the two plugs. Two word lines are located between each plug and the common source line. The conductive material is located above the common source line and the two-character line, and is electrically connected to the common source line. Two first memory layers are respectively located on the surface of the two plugs. The second memory layers are respectively located on sidewalls of the first conductive material, and each of the second memory layers has a cross-sectional area larger than a cross-sectional area of each of the second memory layers. The two connecting conductive layers respectively connect and electrically contact the first and second memory layers to form a memory unit. The bit line is electrically connected to the first conductive material. The invention further provides a memory unit comprising at least one word line, a dielectric layer, a plug, a common source line, at least one conductive material, a first memory layer, a first s memory layer, a connection conductive layer and a bit element line. The word line is on the substrate. (7 丨 electric layer is located on the substrate. A plug and a common source line are respectively located in the dielectric layer on both sides of the word line. The conductive material has a cross section and is located on the dielectric layer, and the common source The first memory layer is located on and electrically in contact with the surface of the plug. The second memory layer is located on the cross section of the conductive material and is in electrical contact therewith, and the second memory layer has a cross-sectional area greater than The cross-sectional area of the second memory layer is connected to the conductive layer and electrically connected to the first and second memory layers. The bit line is electrically connected to the conductive material layer. - To make the above content of the present invention more obvious, the following A preferred embodiment, in conjunction with the drawings, is described in detail as follows: 8 2008 Love_Hidden [Embodiment] The memory cell of the memory cell, the array and the manufacturing method thereof will cooperate with Figure 1 to Figure 6 is described in detail below. Figure 1 is a diagram showing an embodiment 100 of a memory cell having memory cells 100a, 100b in response to the needs of the appended claims. As is typical of memory cell designs, here Draw and discuss The body unit is only a part of a larger memory circuit in which the memory units (100& and 100b form a memory cell 100. The memory cells are arranged in an array to control their access, and a complete memory unit may contain one billion More than one memory unit. Circuits other than the memory unit are not within the scope of the invention. A typical suffix circuit can be found in U.S. Patent Application Serial No. 11/155,67, entitled "Thin Film Melting Phase Change Randomly The reader and its manufacturing method are the same as those of the present applicant, and the contents thereof are incorporated in the present application. The memory cell 100 is constructed on the lower structure 101, which is a conventional common source memory array structure. The details are as follows, but it is worth noting that the unit is a structure in which the plane symmetry surrounds the axis of the common source line 108. Each half portion is equivalent to a single memory unit structure. In the pole structure, each unit structure includes a word line 106 and a plug member 104. The plug member 104 is preferably formed of a heat resistant metal such as tungsten. Suitable heat resistant metals include ruthenium, Mo, A, Ta, Cu, Pt, Ir, La, Ni, and RU, and oxides and nitrides thereof. For example, TiN, RuO, or Ni〇 are known to be useful heat resistant metals. The good word line 106 is polycrystalline germanium, metal germanide or 9 200820469

The inner dielectric layer of the two-spotted muscle. rW3018PA These materials can be formed by a oxidized or similar material. These components are buried in a conventional/internal metal dielectric layer (ILD/IMD). As is conventional, a material having a low dielectric constant can be preferred, and a preferred material is a material. In a non-embodimental embodiment, the structure covering the common source layer is located above the center of the metal layer no, which can be metallized using copper. Other gold materials, including aluminum, titanium nitride, and tungsten, are available. Alternatively, a non-metallic conductive material such as a doped layer may be used between the layers 118, above and below the metal layer, respectively. The three-layer assembly extends to near, but does not cover, the insert member 104. Furthermore, the 'coffee material does not cover the metal layer. The thickness of the metal layer is preferably between 1 G and fine nm, more preferably about 20 legs. The thickness of the two SiN layers is preferably between 2 Å, more preferably about 30 nm. Recessive layers 110 and 112 are provided on the top surface of each plug member and the side walls of the metal layer, respectively. The composition of these material layers will be explained as follows. The shape is flat, and the thickness thereof ranges from 2 nm to 3 nm, preferably about 10 nm. Each of the hidden layers 11〇, 112 is formed of a material having at least two stable impedance levels. This material is called a resistive random access memory RRAM material. Currently, several materials have been proven to be useful in the fabrication of RRAM, as explained below. The chalcogenide group is an important RRAM material. The chalcogen elements include the four elements of oxygen, sulfur, Shixi, and Lu in the elements of the sixth group of the periodic table. 200820469 _

Erda has compiled any of 3711 · rW3〇18PA. The chalcogen compound includes a chalcogen element and an electropositive element or a compound of a radical. Chalcogenide alloys include chalcogenides and other materials such as transition metal combinations. Typically, chalcogenide alloys include one or more elements of Group VI of the Periodic Table, such as cerium and zinc. Generally, the chalcogenide alloy includes a combination of one or more of cerium (lanthanum), gallium (Ga), indium (In), and silver (Ag). Since chalcogenide compounds can include two solid phases and each have a characteristic impedance, a double memory property can be achieved, and therefore, these materials are referred to as "phase change" materials or alloys. A variety of phase change memory materials have been disclosed in the scientific literature, including alloys of Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/. Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te, and Te/Ge/Sb/S. In the Ge/Sb/Te alloy population, the range of alloy compositions that can be implemented is very broad. Its composition can be expressed by TeaGebSbn^a. Researchers have studied that most of the useful alloys have an average concentration of Te in the deposited material of preferably less than 7〇0/. The formula, the type is less than 6%, and the usual range is about 23% to 58%, more preferably about 48% to 58%. The average concentration of Ge in the material is greater than 5%, which ranges from 8% to about 30%, typically less than 50%. Preferably, the Ge/Changing dry circumference is about 8% to 40%. The main constituent element remaining in the composition is Sb. These percentages are atomic percentages, and the atoms of all of the constituent elements are 100%. (0vshinsky, 112 patent, lines 10-11) ° Specific alloys studied by other researchers include Ge2SbTe5, GeSb2Te4, and GeSb4Te7. (Noboru Yamada, high data rate record 11 200820469

The potential of the Ge-Sb-Te phase change optical disc of Erda Burma·rW3018PA, SPIE 3109, pp. 28-37, 1997). In general, the transition metal is, for example, chromium (Cr), iron (Fe), nickel (Ni), and niobium (Nb), palladium (pd), platinum (Pt), and mixtures or alloys thereof, which can be combined with Ge/Sb/Te. Phase change alloy, its bucket has anti-stylization characteristics. Specific examples of memory materials that can be used are described in lines 11-13 of the Ovshinsky '112 patent, examples of which are incorporated herein by reference. In the local range of the active channel region of the memory cell (l〇cal 〇rder), the phase change alloy can be switched between the first structural state and the second structural state, the first structural state being a generally amorphous solid state The second structural state is a general crystalline solid material. These alloys are at least bistable. "Amorphous" means a structure having a relatively low order, which is more than a single crystal disorder, and has detectable characteristics such as a higher electrical resistance than a crystalline phase. "Crystal" means a structure with a relatively high order, which is more ordered than amorphous, and has detectable properties such as lower electrical resistance than amorphous phase. Typical phase change materials can be completely amorphous and completely Conversion between different detectable states of the entire range of the spectrum between crystalline states. Other properties of the material affected by the amorphous phase and the Lb germanium phase include the arrangement of atoms; the density of free electrons and the activation energy The material can be converted to a different solid phase, or transferred to two or more solid phases, providing a gray scale between the completely amorphous state and the fully crystalline L. The electrical properties of the material also change. The moxibustion alloy can be changed from one to another by applying electrical pluses. Short and high amplitude pulses can change the phase change material to a general amorphous state. Low amplitude pulses can be 12 200820469

—* TW3018PA to change the phase change material to a general crystalline phase. The short, high amplitude pulse is high enough to break the bond of the crystal structure; short enough to prevent the atoms from recrystallizing into a crystalline state. The appropriate pulse profile can be determined empirically or by analog (mode ling) and applied specifically to a particular phase change alloy. In the following inner valleys, the phase change material is represented by GST, and other kinds of phase change materials are also usable. The material used for pCRAM here is Ge2Sb2Te5. Other programmable resistive materials may also be used in other embodiments of the invention. One such material is a giant magnetoresistance (CMR) resistive material that can significantly change the impedance level in the presence of a magnetic field. These materials pass through the perovskite oxide and change their impedance over a range of magnetic fields. When applied to rRAM, the preferred chemical formula is PrxCayMn03, where X: y = 〇.5: 〇·5, or other composition is X: 0~l; y: 〇~1. Other CMR materials including Μη oxides can also be used. Other RRAM materials are two-element compounds such as Nix〇y, TixOy, Alx〇y, wx0y, ZnxOy, ZrxOy, CuxOy, etc., where X: y = 0.5·5· 〇·5. Or, the other composition x: 0~1; y: 0~1. Alternatively, a doped polymer may be used, which is doped with, for example, copper, C6 ruthenium, silver, and the polymer thereof is, for example, 7,7,8,8-tetracyano-p-dioxane (TCNQ), [6 , 6] phenyl 051 butyric acid methyl ester (PCBM), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60_TCVQ, TCNQ doped with other metals, or any other bistable or multi-stable state A polymeric material that can be controlled by electrical pulses. 13 200820469

A move / 1 lung m · / W3018PA layer. This layer must have three types of ones = one of the examples has excellent adhesion. The first-first and the following change materials have the electrical conductivity of the barrier property; third, the diffusion blocking material 3 stays at the temperature, for the metal such as plug or M1N, or more includes or one or, the barrier The layer may be τ_W. τντ ^ including one or more elements selected from Ti, the upper side, and the barrier layer being across the width of the plug member 112. Preferably, the metal layer 110 and the material layer m cover the barrier layer 1R, which can be electrically filled and selected from the inner dielectric layer 124. This film layer serves as a spacer for the self-blocking layer 114, which is more clearly illustrated in Figure 6e.矽, the ruthenium metal dielectric layer 124 encapsulates the memory cell, preferably including oxidized polyamine, tantalum nitride or other dielectric filler material. In an embodiment, the layer is planarized, preferably by a chemical mechanical polishing process, to provide a flat surface for the > redundancy process of the underlying material. The octal line 122 is located on the top surface of the inner metal dielectric layer and extends into the inner gold dielectric layer to connect the metal layer 12 through the via window 123. This layer is in contact with other parts of the circuit, as is known to those skilled in the art, and will not be described here. This member can be formed using any of the known materials. In an embodiment, the material of the bit line is a Ti compound, such as 200820469

A mover m · rW3018PA ΤιΝ, or n+ polysilicon, or a multilayer material comprising a titanium layer, such as a TiN/W/TiN two-layer material, or a similar structure TiN/Ti/A1/TiN material. The equivalent circuit of the structure of Fig. 1 can be represented by Fig. 2. The two resistor cores are connected in series with R2' between the bit lines BLi and bl2. The voltage applied to the bit line is represented by Vbl and Vb2, respectively. The voltage drop across the two resistors Ri and is γ2. Therefore, the voltage drop between the two bits is Vb2-Vbl' which is equal to Vi+V2. As shown, the area of the RRAM cell Ri is smaller than the area of the cell R2, and therefore, the impedance Ri will be greater than R2. To state/value

Ri Ruler 2 Memory Value Reset Reset 0 Reset Setting 1 Setting Reset 2 rHT. S again 设定 Set the result of the 3 RRAM state combination and its memory cell value as shown in Table i. The memory cell value corresponds to all relative impedance values. It is worth noting that the embodiment shown in Table 1 adopts a "small-endian" structure. That is, the last unit is the least significant digit (LSD) and the first unit is the most significant digit (MSD). Other embodiments may employ a "big-endian" mode in which the digits are reversed, the procedures described below are the same, but the two memory cells are reversed. The relationship between the state of each memory cell is shown in the 3 a_3d diagram. Drawing 3a 15 200820469

Erlang Airways JHV3018PA shows the memory cells of the cell unit 112 and the conductive barrier layer 11* and the second memory unit 110. Here, both units are in a reset state with a low resistance value. If R is the resistance of unit 112, the resistance of other unit 110 is a fixed value f relative to unit 112. In the illustrated embodiment, the impedance of 'early element 110' is souther than unit 112, and therefore, the fixed value f is greater than 1 'but in other embodiments, it can be described in the reverse manner. The value of f determines the space in which the component operates, that is, the allowable change in resistance. When the component is operating, the f value is sufficient for 2-bit operation. i As described above, in the embodiment of Figs. 3a-3d, the results show that two RRAM cells of different sizes produce different impedances. Among them, the smaller unit has a higher impedance. In other embodiments (not shown), the two cells can use different materials to produce impedances that are equally different. The structural differences between the two real-world examples do not affect the description of their relationship, but the difference is still expressed by the fixed value f. In this embodiment, the two RRAM cells are approximately the same thickness (described in detail later) but differ in width to produce different impedances. The two RRAM cells are connected in series, so the impedance of the entire memory cell can be expressed as R+fR or (1+f)r. The lower order unit 112 is converted to a set state with a higher impedance level, as shown in Fig. 3b. Here, the impedance level is increased by a constant value of n. Different materials have different settings depending on the particular compound or optional characteristics, but the relationship between the reset and set state of a given material, as shown in Figure 3b, can be expressed as R-nR. Therefore, the state shown in Fig. 31) can be expressed as fR + nR or (n + f) R. 16 200820469

—mmwju · TW3018PA Similarly, Fig. 3c shows a diagram showing the result of the RRAM unit 110 transitioning to the set state; and the unit 112 maintaining the reset state. In the illustrated embodiment, the two cells are formed of the same material, and the constant value η represents the difference between the set and reset states, and its resistance can be expressed in nfR. It can represent the resistance of the memory cell by (1+nf) R. Finally, Figure 3d shows the result of the RRAM cells 112 and 110 transitioning to a set sorrow, resulting in a Han-nfR transition. Its state can be expressed as nR+nfR, or n (i+f) r. The relationship between these four memory cell values can be expressed in Table 2 below. Recalling the relationship between cell values -- _ ^ mouth Ui hKJ * relationship iSm l¥rj ΙλΓ^ memory cell value r 0 __Cnil) R 1 _Uinf) R 2 r 3 It is worth noting that the n value and the f value are selected at n= 1〇〇 and f=2. These values can produce a table! All resistance values 汛, i〇2r, 2i〇r, and 300R are shown. Applying a voltage to the bit line ΒΙΆ BL2 sets the memory cell to the desired value (Fig. 2). All four electric difficulties are all possible. Those skilled in the art will appreciate that there are many possibilities for actual voltage. In one embodiment, two positive voltages (measured relative to Vm are positive) and two negative voltages are used, the resulting voltages being expressed as Vhigh, -Vhigh, and -Vlow. The absolute value of the applied electric dust and the characteristics of the memory unit 17 200820469

Erlian Lion Air · iW3018PA related, its related characteristics include the materials and sizes used. In the embodiment shown, the effective high value is 3.3 volts and the low value is 1.5 volts. First, the most critical program is a general reset (RESET), which causes two RRAM cells to go into a reset state, producing a memory cell value of zero. This procedure is shown in Table 3 below. Table 3 all changes to reset τΐσ —· early memory cell action σσ — early memory state state cell Ml 1 3 |Vi|>Vreset 0 0 M2 1 |V2|〉VREset 0

(Vb2~Vbi) = -VhigH The appropriate voltage for this transition is -Vhigh, which allows the absolute values of the voltage drops of Vi and v2 to exceed the reset value, respectively. In the two RRAM cells in the reset state, the total value of the memory cells is zero. The reset state is the starting point for all further operations. Since the transition between the intermediate states may have unpredictable results, it is preferable to return the cell to the reset state as the first step of the operation of changing the state. The opposite state has a memory cell value of 3, as shown in Table 4 below. Table 4 0~3 transition XXX3 one early state memory cell action TTtT one early 70 state memory cell Ml 0 0 Vi>Vset 1 3 18

200820469 ^ 一·TWj018PA M2 0 V2>VsET 1 (Vb2-VBi) =VHigh The VHIGH voltage applied here is sufficient to cause the two cells to produce a voltage drop exceeding vSET. When the two units are in the set state, the memory cell value is two bits 11 or 3. The procedure for generating the memory cell value 2 is shown in Table 5 below. Table 5 0~2 transition σσ I early memory cell action X3X* —' early memory cell state M1 0 0 Vi>Vset 1 2 M2 0 V2<VsET 0

(VB2-Vbi) =Vl〇W In this setting state, the pressure drop V! is greater than the pressure drop required to generate the set state. Therefore, Ri is set, but the pressure drop V2 is less than the set demand, and the remaining unit It is in the reset state. The heart is in the set state, and the result of R2 in the reset state will cause the memory cell value to be two digits 01 or 2. Table 6 below is an illustration showing the generation of a memory cell value of 1. Achieving a value of 1 is more difficult than other transitions. It is obvious that, assuming that two units are reset at the beginning, applying a voltage sufficient to generate a set state at V2 must also be set to Vi, and the resulting value is 3, and Not 1. The solution is to return the memory cell to the fully set state, as shown in Table 3 above. Then, from memory 200820469

Erda, i/t, CW3018PA, cell value 3 starts 'applied-Vl〇w' voltage enough to generate a reset at Ri' instead of R2, resulting in a memory cell value of two bits 01 or 1. Table 6 is converted to 3-1 mouth β a early memory cell action etJ — early memory state state cell Ml 1 3 |Vi|>Vreset 0 1 M2 1 |V2|<Vreset 1

(Vb2-VBi) = -Vl〇W The voltage-current characteristics of the memory cell of Fig. 1 are as shown in Fig. 4. In the figure, there are two curves, one is the transition from reset to set; the other is the opposite situation. The resulting current flowing through the memory cell 100 is as shown in Fig. 5. For the sake of clarity, only one of the units will be explained. As indicated by the arrows, current flows from the underlying circuitry via the plug member 104 to the memory unit. Then, the current passes through the memory layer 110, the barrier conductive layer 114, and the second memory layer 112. Of course, as explained above, the amount of current is regular in accordance with the impedance state of each memory layer. Current then passes through the metal layer 120 and flows outward through the bit line 122 to the memory circuit. In accordance with the principles described above, an embodiment of a method of fabricating a memory cell is illustrated in Figures 6a-6i. Referring to Fig. 6a, the underlying structure 101 is formed in a conventional manner, and the specific structure is as described above. In order to make the following description clearer, the same symbols are no longer heavy in the components of the lower structure in the following figures. 20 200820469

—^»5/1 · TW3018PA The standard is not. Figure 6b illustrates the deposition of two barrier/insulation layers 118a and 118b and a metal layer 120 therein. This process is preferably carried out using conventional chemical vapor deposition techniques. Then, patterning and trimming are performed by a conventional technique to form the structure shown in Fig. 6c. Figure 6d shows the formation of RRAM cells in and 110. Each of the RRAM cells is formed by oxidizing the material of the metal layer 120 and the plug unit 104, respectively. Preferably, a plasma oxidation process is used with a variable ratio (a mixed gas of oxygen and nitrogen as a gas source. It is known that the process can be either direct or indirect, and the latter produces a downflow in the microwave generator ( Downstream) plasma, which is then injected into the reaction chamber by a waveguide. In either case, the required power range is 8 〇〇 to 3000 watts, and for direct processes, the pressure range of the chamber is 10 to 500 Torr; for indirect processes, the chamber pressure ranges from 1000 to 3 Torr. As noted above, the ratio of oxygen to nitrogen may be from 1:1 to 1% oxygen, preferably 9 : 1. The chamber temperature ranges from room temperature to 25 degrees Celsius, preferably ^ 1 is 200 degrees Celsius. The time of the process depends on the thickness of the oxidized metal, preferably about 400 seconds. Λ This process can be Two RRAM cells are formed which are in the form of a l-shaped figure, as shown in Fig. 6e. The actual dimensions of these components are related to the metal layer 12A and the size of the plug member 104, since these components are made there. Oxidized. The thickness of this member is oxidized or otherwise Related to the process, as is known by the art. RRAM cells are electrically contacted through the conductive layer 114, conductive 21

200820469 pA

Second violation a / ΰ. rW30l8PA layer 114 is L-shaped 'which covers the first RRAM cell ii 〇 and covers the second RRAM cell m in the second direction (relatively about 9 degrees with respect to the first direction) The conductive layer 114 can be formed using any of the conventional materials in this field. In one embodiment, the conductive layer is formed of a bismuth "such as TiN or n+ polycrystalline stone" or formed of a multilayer material such as a TiN/Ti/Al/TiN material. L-type wide, such as conductive layer 114, can be deposited by any of the methods known in the art. In an embodiment, a conformal conductive material is deposited... in a positive barrier/metal layer 118/12〇 Structurally, then, a chemical material 116 is deposited on the barrier material. Then, a photoresist material is applied over the oxidized material ^, and then the oxidized material is removed by a two-step (four) (four) sequence. And the barrier material. Both of the ship-engraving steps can use the reactive ion surname program to perform the anisotropic surrogate. The preferred step of the object is to use a fluorine-containing chemical, such as ACF4, called For TM barrier materials, the preferred procedure is chlorine, which is C12, BC13, and other known chlorine-containing chemicals. Since the materials of the layers have a difference, it is preferred to use the end point. Rate γ 1 method 'If the specific material has a suitable residual speed: it can also be time controlled The etching is performed. It is worth noting that the preferred oxide and TiN are over-etched to produce an electrical path from the residual TiN. Similarly, by increasing the anisotropy, the shape of the L-type layer = 4 can be ensured. For example, reducing the pressure in the chamber, increasing the plasma bias, or adjusting the etch rate of the etched polymer protective layer. In Figure 6f, the memory cells are covered by a dielectric fill material 124. This material 22 200820469

A TW3018PA layer can be selected from the material used as the inner dielectric layer / inner eight, or known / read 102: = including two - sub; =; =, has a relatively good insulation ^ The t-electric filling material includes heat and electric appliances to achieve heat to the bridge and "and (4) describe the circuit portion underneath the formation of the connecting member. The first, the second is connected to the recording material m to form the via hole 12 The ruthen m is in the dielectric material via the barrier/insulating screen 11δ; the layer is 迢, the upper surface of the I electrical layer ^, ' 3 118 extends to contact with the metal layer 120. π is described above, although the invention The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the invention. It is to be understood that various modifications and changes can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is subject to the definition of the scope of the appended claims.

The two-dimensional arc · iW3018PA [Simple description of the drawings] Figure 1 shows an embodiment of a memory unit as claimed in the patent application. Fig. 2 is a schematic view showing the circuit of the element shown in Fig. 1. Figures 3A-3D illustrate the impedance values of the logic states achievable by the components shown in Figure 1. Fig. 4 is a graph showing the relationship between voltage and current of the element of Fig. 1. Fig. 5 is a view showing a state in which the current of the element of Fig. 1 flows. 6A-6H are diagrams showing an embodiment of a manufacturing flow of the memory element of Fig. 1. [Description of main component symbols] 100: Embodiments 100a, 100b: Memory cell 101: Lower structure 104: Plug member 106: Word line 108: Common source line 110, 112: Memory layer 118: SiN layer 114: Resistance Barrier 116: dielectric material 118a, 118b: barrier layer/insulation layer 120 · metal layer 122: bit line 124: dielectric filling material 24

Claims (1)

200820469 Erda compiled: TW3018PA X. Patent application scope: 1. A memory component, comprising: a first conductive material having a first surface having a first memory layer thereon; a second conductive material having a first a second surface having a second memory layer thereon; and a bonding conductive layer connecting the first and the second memory layer and electrically contacting the first memory layer, wherein the first memory layer has a cross-sectional area smaller than the second memory layer Cross-sectional area. 2. The component of claim 1, wherein each of the memory layers selectively displays the first and second logic levels. 3. The component of claim 1, wherein each of the memory layers displays the first and second logic levels in accordance with a voltage level selected by the memory component. 4. The component of claim 1, wherein the selection of the logical levels of the memory cells is selected from the first, second, third, and fourth logic levels. 5. The component of claim 4, wherein the first logic level corresponds to an impedance level of the component of (1+f) R, where f is a function of a thickness of a dielectric spacer. 6. The component of claim 4, wherein the second logic level corresponds to an impedance level of the component of (n+f) R, where f is a function of a thickness of a dielectric spacer, η A function of the material of the component. 25 200820469 三达编号:·018ΡΑ 7. The component described in claim 4, wherein the third logic level corresponds to the impedance level of the component is (1+nf) R, where f is a dielectric The function 'π' of the thickness of the spacer is a function of the material of the element. 8. The component of claim 4, wherein the fourth logic level corresponds to an impedance level of the component of n (1+f) R, where f is a function of a thickness of a dielectric spacer, η is a function of the material of the component. 9. The component of claim 1, wherein the bonded conductive layer is an L-shaped member, the first and second memory layers being at right angles to each other. a method of selecting a logic state of a memory cell, the memory cell extending between the bit lines bl and b2 and having RRAM cells at right angles to each other, the RRAM cell being composed of an L-type conductive connecting member, and wherein The cross-sectional area of a first memory layer is smaller than the cross-sectional area of a second memory layer. The method includes: applying a voltage V! to the bit line bl, and applying a voltage V2' to the bit line b2. And V2 exceed the reset voltage of each of the memory cells; and x selects one of the first, second, third, and fourth memory cell logic levels by applying a selected level Vi and v2 One. 11. The method of selecting a logic state of a memory cell as described in claim 10, wherein the memory cell logic level is changed from a reset logic level to a two-dimensional logic level 3 by The bit line applies a voltage such that the voltage of each of the memory layers exceeds the VSET of each layer. 12. The method for selecting a logic state of a memory unit according to claim 10, wherein the memory unit logic level is changed from a reset logic 26 200820469 2 遂 · TW3018PA alignment level to 2 digits Logic level 2 is achieved by applying a voltage across the bit line such that the voltage of the first memory layer exceeds the VSET of each layer and the voltage of the second memory layer is less than the VSET of the layer. 13. The method of selecting a logic state of a memory unit according to claim 10, wherein the memory unit logic level is changed from a two-dimensional logic level 3 to a two-dimensional logic level 1, Applying a voltage to the bit line such that the absolute value of the voltage of the first memory layer exceeds VresET' of each layer and the absolute value of the voltage of the second memory layer is less than the Vreset of the layer. a first conductive material having a first surface and having a first memory layer thereon; a second conductive material having a second surface and having a second memory layer thereon; wherein each of the memory layers is selectable Firstly displaying first and second logic levels, each logic level corresponding to a known electrical impedance of the layer; and a connecting conductive layer connecting the first and the second memory layer and electrically contacting, wherein The cross-sectional area of the first memory layer is smaller than the cross-sectional area of the second memory layer. 15. The memory element of claim 14, wherein the memory layers are arranged at an angle. 16. The memory element of claim 14, wherein the memory layers are arranged at substantially right angles. The memory element of claim 14, wherein the logic level of the memory layer is selected from the first, second, third and fourth logic levels. 18. The memory device of claim 17, wherein the first logic level corresponds to a component impedance level 〇+f) R, where f is a function of a thickness of a dielectric spacer. The memory element of claim 17, wherein the second logic level corresponds to an impedance level of the element (n+f) R, where f is a thickness of the dielectric spacer The function, n is a function of the material of the component. #20. The memory component of claim 17, wherein the second logic level corresponds to an impedance level of the component of (1+nf) R, where f is a function of a thickness of a dielectric spacer. , n is a function of the material of the component. The memory element according to claim 17, wherein the fourth logic level corresponds to the impedance level of the component is ^ ( i + f ) R , and tf is the thickness of a dielectric spacer The function, n is a function of the material of the component. 22· a memory element, comprising: at least two plugs on a substrate; to > a common source line, located between the at least two plugs; to J a sub-line, respectively located at each of the at least two Between the plug and the at least one common source line; a conductive material located above the at least one common source line and the at least two word line, and electrically connected to the at least one common source line; 28 200820469 /n. FW3018PA at least two first memory layers respectively located on the surface of the at least two plugs; at least two second memory layers respectively located on sidewalls of the conductive material, and each of the second memory layers has a larger cross-sectional area than each a cross-sectional area of the first memory layer; at least two connected conductive layers respectively connected and electrically contacting each of the at least two and each of the at least two second memory layers to form a memory unit; and " at least one bit A wire that is electrically connected to the conductive material. The memory element according to claim 22, wherein at least one sub-line of the mouth is symmetrically disposed on the substrate with the at least one common source line as an axis. The memory element according to claim 22, wherein the plug is symmetrically disposed on the substrate with the at least one common source line as an axis. The memory element of claim 22, wherein the conductive material is symmetrically disposed on the substrate with the axis of extension of the at least one common source line as an axis. The memory device of claim 22, wherein the at least two connecting conductive layers are symmetrical about the extending axis of the at least one common source line and symmetrically disposed on both sides of the conductive material. 27. The memory device of claim 1 , wherein each of the at least two connected conductive layers is an L-shaped member, each of the first and each of the second adjacent layers being at right angles to each other. The memory element of claim 22, wherein the materials of the first memory layers comprise phase change random access memory materials. 29. The memory device of claim 22, wherein the material of the second memory layer comprises a phase change random access memory material. 30. The memory element of claim 22, wherein the memory element is a resistive random access memory element. 31 - a memory unit comprising: at least one word line on a substrate; (a dielectric layer on the substrate; a plug and a common source line, respectively located on both sides of the word line a dielectric layer having a cross section and electrically connected to the common source line; a first memory layer on the surface of the plug and electrically connected thereto Contacting; a second memory layer on the cross section of the conductive material and in electrical contact therewith, and a cross-sectional area of the second memory layer is greater than a cross-sectional area of the second memory layer; at least one connecting conductive layer, electrically connected The first and the second memory layer; and the one-dimensional wire electrically connected to the conductive material layer. The memory unit according to claim 31, wherein the connecting conductive layer is an L-shaped member, The first and each of the second memory layers are at right angles to each other. 30 200820469 遂 就 · TW TW TW TW TW TW TW TW TW TW TW TW TW TW , , , , , , , , , , , , , , , , , , , , , Memory material The memory unit of claim 31, wherein the material of the second memory layer comprises a phase change random access memory material. 35. The memory unit according to claim 31, The memory component is a resistive random access memory component. 36. A method of fabricating a memory component, comprising: forming a dielectric layer on a substrate; # forming a common source line and a dielectric layer in the dielectric layer a plug; forming a patterned conductive material on the dielectric layer that does not cover the plug but is electrically connected to the common source line; forming a first memory layer on the surface of the plug; The sidewall of the conductive material forms a second memory layer; and the method of manufacturing the memory device according to claim 36, wherein the first memory layer and the second memory layer are connected to each other. The material of the first memory layer includes a phase change random access memory material. The method of manufacturing the memory device according to claim 36, wherein the material of the second memory layer comprises a phase change 39. A method of fabricating a memory device according to claim 36, wherein the first memory layer is formed simultaneously with the first memory layer. 40. Manufacture of memory elements 31 200820469 二遂公航· [W3018PA method, wherein the first memory layer and the first memory layer are formed by an oxidation process. 41. The memory element of claim 40 The manufacturing method, wherein the oxidizing process comprises a plasma oxidizing process. The method of manufacturing the memory device according to claim 41, wherein the plasma oxidizing process is conducted by using oxygen and nitrogen as a gas source. 43. The method of producing a memory element according to claim 42 wherein the ratio of oxygen to nitrogen is from 1:1 to 100% oxygen. 44. The method of fabricating a memory element according to claim 41, wherein the plasma oxidation process has a power of 800 to 3000 watts. 45. The method of producing a memory device according to claim 41, wherein the plasma oxidation process has a temperature ranging from room temperature to 250 degrees Celsius. 46. The method of manufacturing a memory device according to claim 36, wherein the method of forming the bonding conductive layer comprises: forming a material layer on the substrate, covering the patterned conductive material layer and the plug; Forming a layer of dielectric material on the layer; and etching back the layer of dielectric material and the layer of material to form the bonded conductive layer. 47. The method of fabricating a memory element according to claim 46, wherein the material layer is a barrier layer. 48. The method of fabricating a memory device according to claim 36, further comprising forming a barrier between the dielectric layer and the patterned conductive layer. 32 200820469 达达号: fW3018PA layer. 49. The method of fabricating a memory device according to claim 36, further comprising forming a word line on the substrate prior to forming the dielectric layer. 50. The method of fabricating a memory device according to claim 36, further comprising forming a one-dimensional line in the patterned conductive material layer to electrically connect the patterned conductive material layer. 51. The method of manufacturing a memory element according to claim 36 (the method further comprises forming a barrier layer on the patterned conductive material layer before forming the bit line. 52. The method of manufacturing the memory device of item 36, wherein a cross-sectional area of the first memory layer is smaller than a cross-sectional area of the second memory layer.