TWI310237B - Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states - Google Patents

Description

1310237

- Sanlian No.: TW2958PA, IX, invention description··Technical field to which the invention belongs

SUMMARY OF THE INVENTION The present invention is directed to a mass-density memory farm based on a programmable resistive memory material, comprising a metal oxide substrate and other methods of making the device. U [Prior Art] "Read/write optical discs widely use phase change-based memory materials. The climbing material contains at least two solid phases, for example, a general amorphous solid phase and a generally crystalline stationary phase. The laser pulse enables the reading/writing of the optical disc to be phase-switched and the material of the optical characteristic read after the phase change. Phase change basic memory materials, such as chalcogenide base materials and similar materials, can be phase changed by applying a suitable current level to the integrated circuit. Generally, the amorphous state has a higher resistance coefficient than the general crystalline stationary phase, and can immediately sense and indicate the data. Because of these characteristics, the use of materials that use programmable resistors to form non-volatile circuits has the potential to be read and written with random access. Generally, the amorphous state is changed to a crystalline form by a low current operation. Changing from crystalline to amorphous, referred to herein as reset ' is generally operated with a south current that contains an instantaneous high-density current pulse to refine or break the crystalline structure, and The phase change material is changed by the cooling phase; the sequence can be rapidly cooled' and at least some of the phase change structures are stabilized by #晶晶状. It is desirable to minimize the reset current intensity that causes the phase change material to change from a crystalline state to an amorphous state. Reduce the reset power required for the reset action

131: The flow intensity of TW2958PA can be achieved by reducing the size of the phase change material and the electrode and the contact area between the phase change material and the electrode, and achieving a higher current density with a small absolute current value by the phase change material. One direction of development is to create small holes in the integrated circuit and to fill the small holes with a small amount of programmable resistive material. U.S. Patent No. 5,687,112, issued on Nov. 11, 1997, to U.S. Patent No. 5,687,112, the disclosure of which is incorporated herein by reference. Memory 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the US Patent No. 6, 150, 253, issued on November 21, 2000. Same)” ° • Problems caused by the manufacture of such devices, such as the need for very small sizes of devices, and the need to change the process to meet the stringent specifications of large-size memory devices. As with the pursuit of larger recording capacities, phase-change memory is required. Each memory layer stores a plurality of bits. [Summary of the Invention] A bistable random access memory description Comprising a plurality of programmable resistive random access memory cells, where each programmable resistive random access 7

阮: TW2958PA memory cells have multiple layers of memory layers. Each memory layer stack includes a conductive layer overlying a programmable resistive random access memory layer. According to a first aspect of the invention, a first memory layer stack covers a second memory layer stack, and a second memory layer stack covers a third memory layer stack. The first memory layer stack includes a first conductive layer overlying a first programmable resistive memory layer. The second memory layer stack includes a second conductive layer overlying the second programmable resistive random access memory layer. The third memory layer stack includes a first conductive layer overlying a second programmable resistive random memory layer. The third programmable resistive random access memory layer has a memory area and is larger than a memory area of the second programmable random access memory layer. The second programmable random access memory layer has a memory area and is larger than the memory area of the first programmable random access memory layer. Each programmable resistive random access memory layer has a multi-level memory state, for example, the first bit is used to store the first state and the second bit is used to store the second state. The first memory stack is connected in series with the second memory stack, and the first sigma stack is in series with the third memory stack. The memory cell has three memory stacks and provides eight logic states (2k), where k represents the number of memory layers or memory stacks. For example, the number of billions of stacks can be reduced to two memory stacks per cell, or to four memory stacks per cell, looking at the memory design. Suitable materials for the first reversible resistive memory layer, the second programmable resistive random memory layer or the third programmable resistive random memory layer may include, but are not limited to, metal oxides, giant magnetoresistance Material (c〇l〇ssal magnet〇resistance, CMR), ternary oxide (three_element

: TW2958PA, 0Xlde), phase change materials and polymer materials. Resistive random memory (RRAM) for the first programmable resistive random access memory layer, the material of the programmable resistive random access memory layer, the same or non-resistive random access memory (10) AM) The material of the third programmable resistance access memory layer and the first programmable resistance access memory layer may be the same or different. The resistive random access memory (_) may be the same or different material used for the first resistive random access memory layer and the second programmable resistive random access memory layer. The thickness between the first, second and third programmable resistive random access memories is, for example, about n (nm) to 200 nm (nm). In a broad sense, the memory device includes a first conductive member covering a first programmable resistive random access memory device, and the first programmable resistive random access memory member has a first representation The area of the resistance value, the first conductive member and the first programmable resistive random access memory have sides, and a second conductive member covers the second programmable resistive random access § memory element A programmable resistive random access memory device is disposed over the second conductive member 'the first programmable resistive random access memory device is connected in series with the second programmable resistive random access memory device, and the second The program resistive random access memory has an area representing a second resistance value and the area of the second programmable random access memory component is greater than the area of the first programmable random access memory component. A method of fabricating a bistable resistive random access memory and having multiple § recall layers is described herein. a first memory layer stack including a first conductive layer overlying a first programmable resistive random access memory device 9

13 Qing: TW2958PA material, and the first § Reliance stack includes a second conductive layer covering a first programmable resistive access memory layer, and the first memory layer stack is stacked on the first A #回忆层 heap vertical. A mask is disposed on a portion of the first conductive layer in a dry or wet etch chemistry. The first conductive layer and the left and right sides of the first programmable resistive random access memory layer are etched to the top surface of the second conductive layer, thereby generating a first conductive member and a first programmable resistive random Access memory components. A dielectric sidewall is disposed on the left and right sides of the first conductive member and the first programmable resistive random access memory device. The thickness of the dielectric sidewalls affects the area dimensions of both the second conductive member and the second programmable resistive random access memory device. For example, 'the critical dimension (I) of the mask is about 0.15 micrometers (#ra), and the thickness of the dielectric sidewalls can be about 1 millimeter (nm), which means The area of the second programmable resistive random access memory is approximately twice the area of the first programmable resistive random access memory component. This area is inversely proportional to the resistance value, expressed as a mathematical relationship and P, where 』 represents the length of the programmable resistive random access memory component, and 4 represents the area of the programmable resistive random access memory component. . In this example, the resistance of the second programmable resistive random access *resonant member is approximately one-half the resistance of the first programmable resistive random access memory member. The ideal resistance difference between the first and second programmable resistive random access memory components is determined by the SE:T/RESET resistance window of the programmable resistive random access memory component ( Its resistance ratio from one state to another

I31〇m : TW2958PA 疋 meaning). The second conductive layer and the second programmable resistive random access memory and the left and right sides of the layer are etched to form a second conductive member and a second programmable resistive random access memory device. The left and right sides of the second conductive layer and the second resistive random access memory layer are etched to the next layer or the tooth passes the next layer. A via plug is placed next to the next. According to a second aspect of the present invention, a resistive random access memory for operating a stack of two memory layers arranged in series is disclosed. The first stack includes a first conductive layer overlying a first programmable resistive memory layer, and the second memory layer stack includes a second conductive layer overlying the second programmable resistive memory Take the memory layer. A first bit line voltage Vm is coupled to the top surface of the first conductive layer and a second bit line voltage is coupled to the bottom surface of the second programmable resistive random access memory. A programmable resistive random access voltage v1RRAM has a first end coupled to the first conductive member and a second end coupled to the first programmable resistive random access memory layer member. The second programmable resistive random access voltage V2RRAM is generally connected to the first programmable resistive random access memory component by a first end and to the first programmable second resistive random access memory component. . There are two important variables that affect how a bistable, programmable, resistive random access memory changes from one logic state to another. The first variable is represented by the symbol /3 to indicate the selected memory material characteristics. The second variable is represented by a symbol to indicate the thickness (or width) of the dielectric sidewall. This variable / can be selected or adjusted to change with the resistance 11

131023⁄43⁄4 : TW2958PA combined with a large enough operating window to perform a multi-bit resistive random access memory (RRAM) ° in a bistable random access memory for each memory The unit has two memory layer stacks, and the bistable resistive random access memory operates in four logic states, logic state "00" (or logic state "0"), logic state "01" (or logic state "1" "), logic state "10" (or logic state "2") and logic state "11" (or logic state "3"). The relationship between these four different logic states can be mathematically represented by two variables /1, f, and • the resistance value i?. The logic state "0" is represented by the mathematical formula +. The logic state" is represented by a mathematical expression. The logic state "2" is represented by the mathematical formula (1+/]/)/? The logic state "3" is represented by the mathematical expression /7 (1 */·/%. The advantage is that the overall density of a bistable resistive random access memory is increased by using multiple memory layer stacks by using each memory unit. The invention also provides a three-dimensional bistable random access memory design and manufacturing scheme. The present invention is more capable of reducing the resistance change of the bistable resistive random access memory. The structure and method of the present invention are disclosed in detail later. The summary of the present invention is not intended to define the present invention. The invention is defined by the scope of the patent application. In order to make the embodiments, features, aspects and advantages of these and other techniques more apparent, the following detailed description of the preferred embodiments : 12

Α : TW2958PA [Embodiment] For describing the structural embodiments and methods of the present invention, please refer to the first to seventeenth drawings provided. It is to be understood that the specific embodiments of the present invention are not to be construed as limited. The same elements are shared by the same reference numerals in the different embodiments. Figure 1 is a schematic diagram illustrating a memory array 1 实施 implemented in the manner described herein. As shown in Fig. 1, a common source line (c〇mm〇n source line) 128, a word line 123, and a character Φ line 124 are generally arranged in parallel in the Y-axis direction. One element line mi and 142 are generally arranged in parallel in the X-axis direction. Thus, the y_decoder and a word line driver 145 are coupled to word lines 123 and 124. An X-decoder and a set of sense amplifiers 146 are coupled to bit lines 141 and 142. The common source line 128 is in contact with the source terminals of the access transistors 150, 151, 152, and 153. A gate of the access transistor 150 is coupled to the word line 123. The gate of the access transistor 151 is coupled to the word line 124. The gate of the access transistor 152 is coupled to the elementary line 123. The gate of the access transistor 153 is coupled to the word line 124. The drain of the access transistor 150 is coupled to the sidewall memory cell (the sidewaU pin memory is coupled to the lower electrode member 132, and the sidewall pin 5 has the upper electrode member 134 and the lower electrode member 132. The upper electrode member 134 is coupled to the analog-line 丨 41. The common source line 128 can be considered to be shared by two columns of memory elements, and the column referred to herein refers to the Y-direction of the schematic. In other embodiments, The access transistor can be replaced by a diode, or the device can be selected to control the current flow.

1310^3⁄4 : Used to read and write data in the TW2958PA array. Figure 2 is a simplified block diagram of an integrated circuit 200 constructed of a resistive random access memory in accordance with a preferred embodiment of the present invention. The integrated circuit 275 includes a memory array using a side active pin bistable resistive random access memory cell on one of the conductive substrates. A column of decoders 261 is coupled to the plurality of word lines 262 and arranged along the columns of the memory array 26A. A pin decoder 263 is coupled to the plurality of bit lines 264 and extends along the pins of the memory array 206 to read and program the side of the memory array. Recall the body component data. The address provided by a bus 265 is provided to the pin decoder 263 and the column decoder 261. The sense amplifier and data input structure 2 6 6 is coupled to the pin decoder 2 6 3 through a data sink drain 2 6 7 . The data is supplied from the input/output port located at the integrated circuit 275 or from another data source located inside or outside the integrated circuit 275 via the data-in line 271 to the sense amplifier and the data. The data input structure of the input structure 266 is entered. In the description of this embodiment, 'other circuit diagrams are also included in the integrated circuit, such as general-purpose processor or special purpose application circuitry, or by thin film bistable. Resistive random access memory cell arrays provide a modular system-on-a chip module combination. The data is provided by a data-out line 272 'from the sense amplifier located in the sense amplifier and data input structure 266 to the input/output interface on the integrated circuit 275, or to other internal data destination units or external products. Body circuit 275. 14

13 1 ·· TW2958PA In this example, the controller uses a bias arrangement state machine 269 to control the bis arrangement supply voltage 268, such as read, program, erase, erase verify And the program verification voltage. This controller can be implemented using conventional special purpose logic circuits. In an alternate embodiment, the controller includes a multi-purpose multi-processor 'which can execute the same integrated circuit, and can also execute a computer program to control the operation of the device. In another embodiment, a multiprocessor that combines special-purpose logic circuits and multiple uses is also available for controller implementation. Figure 3 is a simplified diagram showing the steps of the deposition and lithography techniques for fabricating two programmable resistive random access memory layers of a bistable resistive random access memory layer in accordance with the present invention. The bistable resistive random access memory 300 includes a first programmable resistive random access memory layer 31 串 connected in series with a first private resistive random access memory layer 320. Each of the first programmable resistive random access memory layer 31 and the second programmable resistive random access memory layer 320 provides a capacity to store two sets of information states. The first and second programmable resistive random access memory layers 310, 320 provide a total of four sets of logic states in the bistable resistive random access memory 3: the first logic state "〇〇" (or " 0"), the second logic state "01" (or "1"), the third logic state "10" (or "2"), and the fourth logic state "11" (or "3"). In one embodiment, the first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 32 are the same material. In another embodiment, the first programmable resistive random access memory 15

131 (^2: TW2958PA layer 310 and the second programmable resistive random access memory layer 320 are different materials. The first programmable resistive random access memory layer 310 and the second programmable resistive random memory The thickness of the memory layer 320 can be the same or different, and the first programmable resistive random access memory layer 310 or the second programmable resistive random access memory layer 320 has a thickness ranging, for example, from about 1 nm. (nm) to 200 nm (nm) Each of the programmable resistive memory layers 310, 320 formed of the same material contains at least two steady-state resistance levels, that is, resistive random access memory materials. Subsequent narratives prove that different materials are beneficial for the manufacture of resistive random access memory. The term "bistable resistive random access memory" means controlling a resistance level and has the following meanings: voltage amplitude, current amplitude Or electrode. The state of the phase change memory is controlled by voltage amplitude, current amplitude or pulse time. The polarity of the bistable resistive random access memory 300 does not affect the bistable resistance type. The stylization of access memory 300. • The following is a brief summary of four types of resistive memory materials suitable for resistive random access memory. The first suitable memory material for the embodiment is giant magnetic Resistance (CMR) material, such as 镨-i bow-mass oxide (PrxCayMn〇3) where x:y=0. 5:0. 5 or x:0~1; y:0~l to form CMR, wherein Manganese oxide (Mn oxide) can be selectively used. A method of forming a CMR material is, for example, using a physical vapor deposition (PVD) trap or a magnetro-sputtering method, and using argon. Gas (Ar), nitrogen 16

TW2958PA (N2), oxygen (〇2), and or helium (He) are used as source gases, and the pressure is between 1 and 100 milliTorr (mTorr). The deposition temperature ranges from room temperature to 600 ° C depending on the conditions of the subsequent deposition treatment. A collimator with a sweep ratio of 1 to 5 can be used to improve fill-in performance. In order to improve the filling performance, the DC bias voltage can be used from tens of times the voltage to hundreds of times. On the other hand, it can be used in combination with a DC bias and a collimator. A magnetic field from tens of times Gauss to a Tesla (10, OOOGauss) can also be applied to • Improve the magnetic crystalline phase. A post-deposition annealing treatment can be selected for use in a vacuum or in a nitrogen or nitrogen/oxygen mixed environment to improve the crystalline state of the CMR material. The annealing temperature is between 400 ° C and 60 (TC), and the annealing time is at least less than 2 hours. The thickness of the CMR material depends on the design of the memory cell structure. For example, CMR with a thickness of 10 to 200 nanometers (nm) can be used. As a core material, a buffer layer of yttrium-yttrium-copper oxide (YBaCu〇3 is a high-temperature superconductor material) • Buffer layer is also often used to improve the crystallization state of CMR materials. This YBC0 system is deposited on CMR materials. The thickness of YBC0 ranges from 30 to 200 nanometers (nm). The second type of memory material is a compound of two elements, such as nickel oxide (NixOy), tantalum oxide (TixOy), and ft compound ( AlxOy), crane oxide (Wx〇y), zinc oxide (ZnxOy), mis-oxide (ZrxOy), copper oxide (Cux〇y), etc. 'where x:y=〇·5:0. 5 or x:0~l ; y:〇~l. A forming method is, for example, using PVD sputtering or magnetron sputtering method with reactive gas argon 17

1 : TW2958PA gas (Αι·), nitrogen nitrogen (Ν2), oxygen (〇2), or helium (He), etc., pressure between 1 and 100 millitorr (mTorr), using oxidized metal as dry material , such as nickel oxide (NixOy), titanium oxide (TixOy), oxide (AlxOy), tungsten oxide (WxOy), zinc oxide (Znx〇y), oxide (Zrx〇y), copper oxidation (CUxOy) and so on. The deposition is usually formed at room temperature. A collimator with an aspect ratio of 1 to 5 can be used to improve the filling performance. In order to improve the filling performance, a DC bias voltage of tens to hundreds of times can be used. The DC bias can also be used simultaneously with the collimator if required. • A post-deposition annealing treatment can be used to improve the oxygen distribution of the metal oxide in a vacuum or in a nitrogen or nitrogen/oxygen mixture. The annealing temperature is between 400 ° C and 600 ° C and the annealing time is less than 2 hours. An alternative formation method can use PVD sputtering or magnetron sputtering methods with reactive gases argon/oxygen (Ar/〇2), argon/nitrogen/oxygen (Ar/N2/〇2), pure oxygen (〇2) Gases such as helium/oxygen (He/〇2), helium/nitrogen/oxygen (He/N2/〇2), and a pressure of 1 to 100 mTorr (mTorr), using metal shore materials such as nickel (Ni) Titanium (Ti), aluminum (A1), tungsten (W), zinc (Zn), zirconium (Zr), copper (Οι), and the like. Its deposition is usually performed at room temperature. A collimator with an aspect ratio of 1 to 5 can be used to improve fill performance. In order to improve the filling performance, a DC bias voltage of tens to hundreds of times can be used. The DC bias can also be used simultaneously with the collimator if required. A post-deposition annealing treatment can be selected to be used in a vacuum or in a nitrogen or nitrogen/oxygen mixed environment to improve the oxygen distribution of the metal oxide. The annealing temperature is between 400 ° C and 600 ° C, and the annealing time is less than 2 small 18

丄 J 丄 ·- TW2958PA. Another method of formation is oxidation by a high temperature oxidation system, such as a bright furnace or a rapid thermal pulse (RTP) system. The temperature is 200~70 (TC and pure oxygen (〇2) and nitrogen/oxygen (仏/〇2) mixed gas, the pressure is several millitorr (mTorr) to 1 atmosphere (atm), and the time range is several minutes to several Another oxidation method is plasma oxidation. A radio frequency or DC source plasma is pure oxygen (〇2), argon/oxygen (Ar/〇2) mixed gas or argon/nitrogen/oxygen (Ar/Ch/O2). The mixed gas is used to oxidize the metal surface at a pressure of ι~ι〇〇mTorr φ (mT〇rr), such as Ni (Ni), Ti (τι), Ming (A1), Tungsten (W), Zinc ( Zn), knot (Zr), copper (Cu), etc. Its oxidation time ranges from a few seconds to several minutes. Its oxidation temperature ranges from room temperature to 3〇〇nc, depending on the degree of plasma oxidation. The type of material is a polymeric material, such as tetracyquinodimethane (TCNQ) doped copper (Cu), carbon 60 (α.), silver (Ag), etc. or phenyl C61 butyric acid Phenyl C61-butyric acid methyl ester (PCBM)-cyano-p-bifluorene-compound (TCNQ) mixed polymer. The formation method can be by thermal evaporation, electron beam Electroplating (e-beam evaportation) or molecular beam epitaxy (MBE) system is performed. The solid state TCNQ and the doped granules are co-evaporated in the morning (co-evap〇rated). The solid state of TCNQ and the granular material are doped into a crane boat (wb〇at) or a boat (Ta-boat) or a pottery boat. A high current or electron beam is applied to the melting source material for material mixing. And deposited on the wafer. Unreactive chemicals 19

131 : TW2958PA quality and gas. The deposition is carried out at a pressure of 10-4 to 10j (T〇rd. The temperature of the wafer ranges from room temperature to 2 〇〇. 〇. A post-deposition annealing treatment can be used for vacuum or nitrogen (NO ring) 3 brothers to improve the composition of the polymer material. The annealing temperature is from room temperature to 300 ° C, the annealing time is less than 1 hour. Another technique used to form a polymer-based memory material is doped TCNQ The solution is spin coated at a speed less than i rpm. After spin coating, the wafer is placed for a period of time until a solid state is formed (typically at room temperature or below 200 ° C). The placement time ranges from a few minutes to several days' depending on its temperature and formation state. The fourth type is a chalcogenide material such as GexSbyTez where x:y:z=2:2: 5 or consist of x:0~5, y:〇~5, z:0~10. GeSbTe can be doped with nitrogen (N-), yttrium (Si-), ytterbium (Sb_) or selective doping other The method of forming a sulfide material can be, for example, PVD tantalum or magnetron sputtering method and source gas argon (Ar), nitrogen (仏). And / or 氦 (He) gas body, the pressure is 1~1 〇〇 millitor (mTorr). The deposition is usually formed at room temperature. A collimator with an aspect ratio of 1~5 can be used to improve Filling performance. In order to improve the filling performance, the DC bias voltage can be used from tens to hundreds of times. If necessary, the DC bias can also be used simultaneously with the collimator. A post-deposition annealing treatment can be used. The crystal state of the sulfide is improved in a vacuum or in a nitrogen atmosphere. The annealing temperature is generally between 1 〇〇C and 400 C, and the annealing time is less than 30 minutes.

131 (3⁄43⁄4: TW2958PA thickness is higher than 8 nanometers (nm) and may have a phase change characteristic to cause the material to exhibit two stable resistance states. In the embodiment, the memory of the bistable resistive random access memory 300 The cell may include a phase change-based memory material, a sulfide-based material, and other materials, as the first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 320. The chalcogen element contains the sixth group of the periodic table and any of the four elements oxygen (Oxygen), sulfur (Sulfer), selenium (Selenium), and 碲# (Tellurium). The sulfide contains more positive electrical properties (electropositive) Element) or a radical chalcogen compound. Chalcogenide alloys contain chalcogenides and other materials such as transition metals. Chalcogenide alloys usually contain one or more elements from the sixth column of the periodic table elements such as ruthenium ( Germanium) and tin (Tin). Usually the chalcogenide alloy comprises a combination of one or more of anthony, galli, indium and sliver. Body materials have been described in scientific publications, including alloys: gallium/germanium (Ga/Sb), indium/bismuth (In/Sb), indium/selenium (In/Se), bismuth/bismuth (Sb/Te),锗/碲 (Ge/Te), 锗/锑/碲 (Ge/Sb/Te), indium/锑/碲 (in/Sb/Te), gallium/selenium/tellurium (Ga/Se/Te), tin/锑 / 碲 (Sn / Sb / Te), indium / 锑 / 碲 (In / Sb / Ge), silver / indium / 锑 / 碲 (Ag / In / Sb / Te), 锗 / tin / 锑 / 碲 (Ge /Sn/Sb/Te), 锗/锑/Selenium/碲 (Ge/Sb/Se/Te) and 碲/锗/锑/Sulphur (Te/Ge/Sb/S). 锗/锑/碲 (Ge In the /Sb/Te) alloy family, the alloys that can be used have a wide range of compositions, and their composition can be characterized by the 碲_锗-锑 compound (TeaGebSbm-wbO. A researcher has described the most useful alloys 21

• 13 1 OJH : TW2958PA The average concentration of cerium (Te) in the deposited material is preferably less than 7〇%, generally less than 60%' in the general range, from 23% to 58% Te, and preferably about 48%~58% Te. The concentration of germanium (Ge) is greater than about 5% and averages from about 8% to an average of 30% in the material, typically less than 50%. The main constituent element remaining in this compound is bismuth (Sb). These percentages are atomic percentages and the total amount of constituent element atoms is 1%. (Ovshinsky) 112patent, cols 10-11·). The special alloy evaluated by another investigator contains yttrium-tellurium-gallium compounds (Ge2Sb2Te5, GeSb2Te4 with 0 and GeSb4Te?) (Noboru Yamada," with gallium-germanium-tellurium (Ge) -Sb-Te) The possibility of phase-change optical discs for high-rate data recording, SPIE ν·3109, pp. 28-37 (1997). More broadly, a transition metal such as chromium (chromium, Cr), iron (iron), nickel (nickel, Ni), niobium (Nb), palladium (Pd), platinum (platinum, Pt), and mixtures thereof or alloys thereof may also be combined with 锗/锑/碲 (Ge/Sb/Te) are combined to form a phase change alloy to have programmable resistance characteristics. Special examples of memory materials may also be useful by Ovshinsky' 112 patent at columns 11-13. Examples are included in the reference. The phase change alloy can be switched between a first structural state in which the material is located in a generally amorphous solid phase and a second structural state in which the material is located. Generally crystalline solid phase, which is the active channel region of the memory cell Partial order (l〇cal order). These alloys are at least bistable. Amorphous refers to a relatively disorderly structure, which is less ordered than a single crystal and has detectable properties compared to a crystalline state. Such as higher 22

Ι31· ^ : TW2958PA • Resistivity. The crystalline state refers to its relatively ordered structure (ordered compared to the amorphous structure), which has detectable properties such as a lower electrical system I coefficient than the amorphous phase. In general, the phase change material can be electrically switched to each other in a detectable state between the range of fully amorphous and crystalline states of the local order. Other material properties are also affected by the phase changes in amorphous and crystalline properties, including atomic order, free electron density, and activation energy. The material can be switched to a different solid phase or a mixture of two or more solids to provide a gray scale between completely amorphous and fully crystalline states. The electronic properties in the material • will change accordingly. Phase change alloys can be changed from one phase to another by the application of electronic pulses. It can be observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy of a shorter, higher amplitude pulse is high enough to cause the crystal bond to be broken, and because the pulse is short enough to avoid rearranging the atoms into a crystalline state. The appropriate pulse waveform for a particular phase change alloy can be determined without undue experimentation. The phase change material disclosed in the subsequent sections refers to 锗-锑-碲 (GST), and it can be understood that other phase change materials can also be used. The material described herein that is useful for completing the phase chage random access nieniory (PCRAM) is a mis-recording-hoof compound (Ge2Sb2Te5). Other programmable resistive memory materials can also be used in other embodiments of the invention, including 锗-record-碲 (GST) doped nitrogen (N2), erbium-tellurium (GexSby), or other materials using different crystals. The change of phase depends on 23

I31〇m : TW2958PA determines its resistance; 镨-calcium-manganese oxide (PrXayMn〇3), 镨-锶-manganese oxide (PrSrMnCb), zirconium oxide (Zr〇x), tungsten oxide (W〇x) Titanium oxide (Ti〇x), aluminum oxide (A10O or other materials use electronic pulses to change their resistance state; 7, 7, 8, 8-cyano-p-dioxane complex (7, 7, 8,8-tetracyanoquinodimethane, TCNQ), methanofullerene 6,6-phenyl C61-butyric acid ester, PCBM, TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C6Q-TCNQ, TCNQ doped with other metals, or any other A polymer material controlled by an electronic pulse and having a state of bistable or multiple steady state resistance. The first conductive layer 312 is overlying the first programmable resistive random access memory layer 310 and is a conductive element. The second conductive layer 322 is disposed between the first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 320. The first conductive layer 312 is coupled to the first programmable The resistive random access memory layer 310 has connected conductive elements. The second conductive layer 322 is connected to the second programmable circuit. The random access memory layer 320 has connected conductive elements. The material suitable for the first conductive layer 312 and the second conductive layer 322 comprises: bismuth (Ti), titanium nitride (TiN), titanium nitride/tungsten/ Titanium nitride (TiN/W/TiN), titanium nitride/titanium/aluminum/titanium nitride (TiN/Ti/Al/TiN), n+polysilicon (n+polysilicon), nitrous oxide (TiON), tantalum (Ta) ), a nitride button (TaN), a nitrogen oxide button (TaON), and other materials. * In one embodiment, the first conductive layer 312 and the second conductive layer 322 are the same material, but in another embodiment The first conductive layer 31 £ and the second conductive layer 322 are different materials. The first conductive layer 312 and the second conductive layer 24

131: The thickness of the TW2958PA layer 322 may be the same or different. The first conductive layer 312 or the second conductive layer 322 has a thickness ranging, for example, between about 1 Å and about 2 nanometers (nm). A mask 330 is formed on the conductive layer 312. This mask 33 〇 spoon contains photoresist, hard mask (1 ^ (111 ^ 1 〇 ' such as 矽 oxide (^ 〇 3 [), Shi Xi gas = material (SiNx), Shi Xi oxynitride (SiOxNy) This mask can be trimmed to a critical dimension (CD) by selecting a suitable masking technique. If the mask 33n is used in a group of chlorine (ClBr and hydrogen bromide (HBr)-based reactive ion etching machines) γ Trimming the photoresist. If the mask 330 is a hard mask, wet-trimming with a suitable solvent can be used to trim the hard 豸 [in particular, dilute HF (DHF) can be used for oxidation. A mask made of 矽(Si〇x). Hot phosphoric acid (HPA) is used for hard masks made of ',,' nitrogen (SiNx). A schematic diagram of the step under the bistable resistive memory 30G, (4) to the second conductive acoustic layer have a deposition adjacent to the first conductive member 412 and the first programmable memory member 410. The first conductive sound is etched to the top surface of the second conductive layer 322 along with the conductive layer 312 and the first programmable resistance pattern as shown in FIG. 3 to form a first piece. The first-programmable resistive random access memory component 41=L sequence and the third first programmable resistive random access memory layer are single-non-equal (four), or two-ordered 'order' The first - money engraved chemical _ the first conductive layer batch · = two 'to the second her chemical _ first - programmable resistance random access 25 131

TW2958PA = two money carving chemicals can be based on a single material or: ", brother: if the first conductive member 412 = = first, the step is z conductive layer 312 ' and the second is the gasification of sulfur (10):; = - a programmable resistive random access memory layer 310. The -4H) material is stored on the left and right sides of the first programmable resistor/electrical component 412. The first dielectric side The sub-430 is placed on a portion of the top surface of the second conductive portion 322. The material suitable for the electro-optic sidewall includes oxidized hair (si(6) and gasification stone ' ́ and the material selected herein has a predetermined thickness. The first dielectric side The thickness of the sub-430 430 affects the area of the second conductive member 512 (as illustrated by s 5) to the second programmable resistive random access memory device 51 (as shown in Figure 5). For example: if The cover 330 has a critical dimension of "15 micrometers (μιη), and the thickness of the dielectric sidewall is set to be approximately 耵ηηη), so that the second programmable resistive random access memory The area of the member 510 is approximately twice as large as that of the first programmable resistive random access memory member 41. That is, in the same logic state (such as SET or RESET), the resistance of the second programmable resistive random access memory component 51 is approximately the power limit of the first programmable resistive random access memory component 41〇. The resistance difference between the first programmable resistive random access memory component 41 and the second programmable resistive random access memory component 51 is based on a resistive random access memory material SET/ RESET resistor window. Fake $ and SET/RESET window is about 10 times an order of magnitude (order of 26

1310: : TW2958PA magnitude), the resistance difference of the first programmable resistive random access memory component 410 and the second programmable resistive random access memory component 510 is approximately twice as appropriate. Figure 5 is a block diagram showing the next step of fabricating a bistable resistive random access memory in accordance with the present invention. The etching is performed through a second resistive random access memory layer. The second conductive layer 322 and the second programmable resistive random access memory layer 320 (as shown in FIG. 3) are pasted to the top surface of the underlying layer by a reactive ion etching machine or etched through a bottom layer 610 ( As shown in Fig. 6, the second conductive member 512 and the second programmable resistive random access memory > the memory member 51 are formed. The etching process can be performed on the second conductive layer 322 and the second programmable resistor. The random access memory layer 32 is etched by a single asymmetrical phase or a two-stage process. First, the first etch etch etches the second conductive layer 322. Second, the second etch etch etches the second programmable resistor. The random access memory layer 320. The etching chemistry can be selected according to the material or material. For example, if the second conductive member 512 is made of titanium nitride (TiN) and the second programmable resistive random access memory device 51Q Hexane gas π〇χ), the two-stage etching process uses gas (Ch) to etch the first conductive layer j? j, and fluorinated sulfur (SF 〇 to the second process ^ random access The memory member 510 performs a second etching. Equation 6_(4) is based on Invention double (four) programmable electrical access memory _ electric shouting _ access memory cell structure (9) legacy, 5 circle graph = _ tilt 61. has been _ through, == containing ^ ^. bistable programmable resistance random memory The memory _ packet bottom layer _ is set in the second programmable resistive random access memory 匕 27

13l (mA: TW2958PA device 510. The etching process of the bottom layer 610 is stopped on the top surface of the intermediate dielectric layer 63A. The bottom layer 610 is connected to the contact hole 62〇' is disposed under the bottom layer 61〇 and is dielectrically interposed. The layer 630 is surrounded. The embodiment of the contact hole 62A includes a tungsten plug (W-plug) or a polysilicon plug (p〇ly_Si plug), and the polycrystalline germanium plug can be made of a polycrystalline germanium (Poly_Si with a germanium (16) or Np diode ( The NP diode is constructed. Figure 7 is a diagram showing a current-voltage curve of a bistable resistive random access memory having a resistive random memory layer according to the present invention. 710 and the y-axis is current 720. In a RESET state 730, the resistive random access memory layer is low resistance. In a set (SET) state 740', the resistive random access memory layer is at a high Lightning resistance. In this example, the set/reset window of this resistive random access memory layer is approximately one order of magnitude of read voltage 750. This read voltage, shown as a dashed line 752, exhibits a high current state ( High logic state) and low current state (low logic) There is a significant gap between the states), and the current in the reset state 730 rises from the reset state 730 'after the voltage stress' to the Guru current. From the set state 740, the current in the set state decreases. The large swing, from low state to high state or from high state to low state, it becomes difficult to control different logic multiple states with voltage. Therefore, different resistive random access memory layers are connected in series, and this Each resistive random access 5 memory has its own P product or its own resistance for the bistable resistive random access memory to achieve different logic states. FIG. 8A is a diagram showing Bi-stable range 28 with two resistive random access memory components all in a RESET state

: A simplified schematic of the TW2958PA type resistive random access memory 600. When the first programmable resistive random access memory component 410 and the second programmable resistive random access memory component 510 are in a reset state, the bistable programmable steep random access memory 600 operates In the logic state "00". The second programmable resistive random access memory component 510 has a resistor egg 1 and the first programmable resistive random access memory component 410 has a resistance θ 820. The variable here is greater than 1 because the area of the first programmable resistive random access memory component 410 is smaller than the area of the second programmable resistive random access memory component 510. The total resistance of the bistable programmable resistive random access memory 600 is approximately (1+/) and . For example, assume that the variable / is equal to 2' and the total resistance can be calculated as 3i?, and the mathematical expression is expressed as (l+2/?) = 3i?. Figure 8B is a simplified schematic diagram of a bistable programmable resistive random access memory 600 having two resistive random access devices in a set (SET) and reset (RESET) state in accordance with the present invention. When the first programmable resistive random access memory component 41 is in a set state and the second programmable resistive random access memory component 51 is in a reset state, the bistable programmable resistive memory is stored. The memory 6 is operated in a logic state "01", and the second programmable resistive random access memory component 510 is still in a reset state or is not charged. The second programmable resistive random access memory device 510 has a resistor base 1 and a first programmable resistive random access memory component 41 having an electrical function, such as the variable here. ] is bigger than 1. The total resistance of the bistable programmable resistive random access memory 600 is approximately (1+/2i)i?. For example, if the variable f is equal to 2 and the variable /3 is equal to 10' and the total resistance is calculated as 21i?

-· TW2958PA The formula is expressed as (l〇+21)i?=31i?. Figure 8C is a diagram showing the simplicity of a bistable programmable resistive random access memory 600 having two resistive random access triple-element members in a set (SET) and reset (RESET) state in accordance with the present invention. schematic diagram. When the first resistive random access memory material member 410 is in a reset state and the second programmable resistive random access memory device 510 is in a set state, the bistable programmable resistive random access memory 600 operates in a logic state "10"' where the first programmable resistive random access memory component #410 is still in a reset state or charged. The second programmable resistive random access memory component 510 has a resistor 580 and the first programmable resistive random access memory component 410 has a resistor /i?860, where the variable is; 2 is greater than one. The total resistance of the bistable programmable resistive random access memory 600 is approximately (/7 + f) i?. For example, assuming that the variable / is equal to 2 and the variable /2 is equal to 10, the total resistance can be calculated as 12i?, and its mathematical expression is expressed as (10+2)i?=12i?. Figure 8D is a simplified schematic diagram of a bistable programmable resistive random access memory 600 having two resistive random access memory components in a set (SET) state according to the present invention. When the first programmable memory random access memory component 410 is in a set state and the second programmable resistive random access memory component 510 is in a set state, the bistable programmable power is randomly selected. The access memory 6 is operated in a logic state 11. The second programmable resistive random access memory device 510 has a resistor fli? 870 and a first resistive random access memory 41 having a resistor / 8000. The bistable programmable resistance random access memory 30 .131 .131

: The total resistance of TW2958PA 6〇0 is approximately. For example, assuming that the variable 彡 is equal to 2 and the variable /3 is equal to 10, the total resistance can be calculated as 3 〇芡, and the mathematical expression is expressed as 10 (1 + 2) at = 30. FIG. 9 is a diagram showing four logics of a bistable programmable resistive random access memory 6 提供 that provides two logic states by connecting two memory type Ik machines connected in series according to the present invention. The mathematical relationship of the state, and each memory cell stores two yuan. Three variable cases, and the equation of γ using the relationship of the gross resistance, where the variable 芡 indicates that the reset electrical group of a memory member, the variable /2 is related to the characteristics of the resistive random access memory material, and the variable f and The thickness of the electric side wall is related. In other words, the variables are dependent on the material properties. The variable f can be controlled by the thickness of the dielectric sidewalls. In the logic state "〇" 91〇, the total resistance of the bistable programmable resistive random access memory 600 is approximately (1+/)/?. In the logic state "丨" 92〇, the total resistance of the bistable programmable resistive random access memory is approximately (s). In the logic state "2" 93G, the total resistance of the bistable programmable resistive random access memory 600 is approximately. In the logic state "3 94〇' bistable resilience resistive random access memory 6〇〇 total resistance is about Z5(l + i)i?. Adjust the variable / to match the resistance transformation, so that the operation window In the case of bistable programmable resistance random access memory, for example, 'the above two-bit operation window is represented by the resistance L, and then succeeds. If the variable (four) (10), and the variable /= 2, and the two-bit operation window will be calculated as 3 and 300]?. 1/? Figure 10 illustrates the connection of multiple resistors 串联31 in series according to the present invention.

No. 1310212: TW2958PA A schematic diagram of a bistable resistive random access memory 1000 with random access memory components to provide multiple bits per memory cell. Multiple Resistive Random Access Memory Components connect each memory cell in series to provide multiple bits. The bistable resistive random access memory 1000 includes a multi-resistive random access memory layer connected in series, in other words, a first programmable resistive random access memory layer 310 and a second programmable resistive random access The access memory layer 320 is connected in series, and the second programmable resistive random access memory layer 320 is connected in series with the third programmable resistive random access memory layer 1010, ..., • the (nl)th programmable resistive random memory layer 1020 It is connected in series with the nth programmable resistive random access memory layer 1030. In an embodiment, each of the first, second, third, (n-1)th, nth programmable resistive random access memory layers 310, 320, 1010, 1020, 1030 provides the ability to store two logic states, respectively. In another embodiment, each of the first, second, third, (n-1)th, nth programmable resistive random access memory layers 310, 320, 1010, 1020, 1030 provides storage greater than two bits, respectively. The ability of meta information. In other embodiments, each of the first, second, third (nl)th, nth programmable resistive random access memory layers 310, 320, 1010, 1020, 1030 provides two or more stores, respectively. The two-digit information ability, in which each bit has the ability to store multiple pieces of information. The total number of logic states of the bistable resistive random access memory 1000 is determined by the number of Xs of each resistive random access memory layer and the number of layers y per bit, expressed by the mathematical formula Zx~, symbol Z The total number of total resistive random access memory layers. For example, if the bistable resistive random access memory 1000 has eight resistive random access memory layers, each resistive access memory layer can store one bit of resources.

13103⁄43⁄4: TW2958PA and each bit stores two logic states or current levels, and the total number of logic states can be calculated as 81#2 or 64 logic states. Each of the first, second, third, ... (n-ΐΓ, nth programmable resistive random access memory layers 310, 320, 1〇1〇, 1020, 1030 material respectively

The same material can be used for the same or different 'or some resistive random access memory layers, and some materials can be used in combination with other resistive random access memory layers. In addition, the thicknesses of the first, second, third, (nl)th, nth programmable resistive random access memory layers 310, 320, 1010, 1020, 1030 may be the same or different from each other, or some resistive random memory Take the memory using the same thickness 'part of the other resistive random access memory layers using different thicknesses. The first, first, third, ... (n_l)th, nth programmable resistive random access memory layers 310, 320, 1〇1〇, 1〇2〇, 1030 have a thickness ranging, for example, from about 1 nm (nm) ) to between 200 nm (ηιη). Each resistive random access memory layer is connected to a conductive layer. In addition to the first and second conductive layers 312, 322 described above, the third conductive Jan 1 12 is disposed on the third resistive random access memory layer 1 〇 1 。. (n_1)th

The conductive layer 1022 is disposed on the (n-1)th resistive random access memory layer. The nth conductive layer 1032 is disposed on the /th programmable resistive random access memory layer 1030. Figure 11 shows a bistable state with an etching process for the first and second programmable random access memory devices 41G, 510 with an A Saki (10) electrical sidewall 43°, 1U〇. A schematic diagram of resistive random access. The etching process can be further performed in a programmable resistive random access memory device 41〇, 33

: TW2958PA and subsequent resistive random access memory layers, such as the third resistive random access memory layer 1010. In this example, the third conductive layer 1〇12 is simultaneously etched in the third resistive random access memory layer 1010. The same dielectric sidewall is also disposed on the subsequent conductive layer and the resistive random access memory layer. In the practical example, the area of the second programmable resistive random access memory component 510 is mainly by the first The dielectric sidewall 43 is determined. Similarly, the area of the third resistive random access memory device 1〇1〇 is also mainly determined by the second dielectric sidewall 1110. Therefore, each of the resistive random access memory layers has its respective area and is mainly defined by the thickness of the dielectric sidewalls, and thus, the resistive random access memory layers have their respective resistances. Figure 12 is a schematic diagram showing a bistable resistive random access memory device 12 having a plurality of resistive random access memory devices and a plurality of conductive members after removing the dielectric sidewalls according to the present invention. The bistable resistive random access memory 1200 includes a first conductive member 412 disposed on the first programmable resistive random access memory device 41, and a first programmable resistive random access memory member 41. On the second conductive member 512, the second conductive member 512 is disposed on the second programmable resistive random access memory member 510, and the second programmable resistive random access memory member 51 is disposed on the third conductive member. The first conductive member 1220 is disposed on the third programmable gate random access memory device do.., and the nth conductive member 1040 is disposed on the nth programmable resistive random access memory layer 1030. In an embodiment, the first conductive member 412 has the same width as the first programmable resistive random access memory member 41, and 34

131 (^3⁄4: TW2958PA is smaller than the width of the second conductive member 512 and the second programmable resistive random access memory member 510. The second conductive member 512 has the same as the second programmable resistive random access memory member 510 The width of the nth conductive member 1040 and the nth programmable resistive random access memory layer 1030 is smaller than the width of the third conductive member 1220 and the third programmable resistive random access memory device 1210. A resistive random access memory component and a conductive member have a wide width. As shown in FIGS. 12 and 13, the bit line voltage is applied to the bistable programmable resistive random access memory 600 to achieve Different logic states. Structure 500 as shown in Figure 5 can be illustrated in Figure 13 in the same circuit diagram. In this embodiment, two programmable resistive random access memory layers are described, along with additional memory layers and corresponding bits. The first resistor Rd310 of the circuit 1300 represents the resistance of the first programmable resistive random access memory component 410, and the second resistor R21312 represents the second programmable voltage. The resistance of the resistive random access memory device 510 is connected to the first bit line BLd340 having the first bit line voltage Vbd320 and the second bit line BL21342 having the second bit_yuan line voltage Vb21330. The bit line voltage Vbl1320 is connected to the top surface of the first conductive layer member 412 and the second bit line voltage Vb21330 to the bottom surface of the second programmable resistive random access memory member 510. In this embodiment, the double The steady-state resistive random access memory 500 includes two ohmic resistance random access memory layers having two first and first programmable resistive random access memory components 410 and a second programmable resistive The voltage connected to the random access memory component 510, wherein the first voltage to the first programmable resistive random access memory 35

131023&: TW2958PA body member 410, indicated by symbol V1RRAM 1312 and second voltage to second resistive random access member 510, indicated by symbol VmAd314. The first programmable resistive random access voltage V1 RRAM 1313 has a first end connected to the first conductive member 412' and a second end connected to the first programmable resistive random access memory member 410. The second programmable resistive random access memory voltage VmAM 1314 has a first end generally connected to the first programmable resistive random access memory component 410 and the first programmable resistive random access voltage ν11ίΚΑΜ 1313, and A second end is coupled to the second programmable resistive random access memory component 510. Another programmable resistive random access memory voltage, such as V3 mM 1316, is coupled to the third programmable resistive random access memory 1210 and can be applied to the programmable resistive random access memory component of the subsequent performance. When the bistable resistive random access memory 500 is in a reset state, that is, a reset state, the bistable programmable resistive random access memory 600 has a logic state of "〇" (or state "〇〇" ”Setting 8 bistable programmable resistive random access memory 600 can be switched from logic state “逻辑” to logic state “1” (or state “〇1”), or from logic state” 〇” to logic state “2” (or state “1〇”), or logic state “〇” to logic state “3” (or state “11”). In the process of the programmable bistable resistive random access memory 500 from the logic state "〇〇" to the logic state "10", the first voltage is applied to the first bit line to reach the first bit line voltage Vbl1320 and one The second voltage is applied to the second bit line up to the second bit line voltage Vbd330. The voltage applied to the first bit line voltage Vbd320 may be a chirp voltage or a small negative voltage 36

131023⁄43⁄4 : TW2958PA pressure. The voltage difference applied between the first bit line Vbil320 and the second bit line voltage Vb2l330 is equal to the sum of the first resistive random access memory voltage V1RRAM1313 and the second resistive random access memory voltage V2mMl314' If expressed in mathematics, it is: V"b2-Vbl = V2mM + VlRRAM = Vlcw. The initial state of both the first programmable resistive random access memory component 410 and the second programmable resistive random access memory structure 510 is a reset state, that is, a low resistance state. In this embodiment, the area of the first programmable resistive random access memory component 410 is smaller than the area of the second programmable resistive access memory structure 510. Therefore, the resistance of the first programmable resistive random access memory component 410 is higher than the resistance of the second programmable resistive random access memory structure 510. This means that the value of the first resistive random access memory voltage ν1 ΚΜΜ 1313 is larger than the second resistive random access memory voltage V2 mM 1314, and if expressed in a mathematical relationship, it is VlRRM > V2 mM. Assuming that the first resistive random access memory voltage VlRRAM 1313 is larger than a reset voltage (VlRRAM>VsET), the first programmable resistive random access memory component 410 is changed from a reset state to a set state. ® (ie high resistance). If the second resistive random access memory voltage V2RRAK1 314 is less than the set voltage (V2RRAM < VsET), the second programmable resistive random access memory component 510 remains in the reset state. The resistance of the first programmable resistive random access memory device 410 has a resistance value of + from a logic state "0" (or state "00") to a logic state "2" having a resistance (or a state "10" "). For example, if the variable /=2, the variable/2=10, and the second programmable resistive random access memory member 510 has a reset resistance equal to i?, the total resistance will change from 3/?

13103⁄43⁄4 : TW2958PA to 21i?. & in the process of stabilizing the programmable resistive random access memory 6 from the logic (or state "〇〇") to the logic state "3" (or the state 1) The first voltage is applied to the first bit line to reach the first bit το line voltage Vbl132G, and the second voltage is applied to the second pass line to reach the first bit το line voltage vb2i330. The voltage applied to the first bit line voltage can be zero voltage or a small negative voltage. The initial state of the first programmable resistive random access memory component 410 and the second programmable resistive random access memory component 510 is a reset state, that is, a low resistance state. The voltage difference between the first bit line voltage Vbil32〇 and the second bit line voltage Vb21330 is sufficient (Vhigh), which is sufficient for the first resistive random access device voltage V to “1313 and the second resistive random memory The memory voltage V window "1314 is compared with the first-programmable resistive random access memory device 41" and the second programmable resistive random access memory device 51 () #V positive. The resistance states of the first programmable resistive random access memory component 410 and the second programmable resistive random access memory component 51 are changed from a reset state to a set state. The resistances of the first and second programmable resistive random access memory components 410, 510 are changed from a resistance value (1 + / from a logic state "〇" ^ state "〇〇") to a logic state of a resistance value 「" 3" (status "11"). For example, if the variable f=2, the variable n=1〇, and the second resistor of the second type of resistive random memory device 510 are equal to the allowable resistance, the total resistance will change from 3 to 30 犮. In the bistable programmable resistive random access memory 6 程式 from the logic state "〇" (or state "〇〇") to the logic state "丨" (or shape 38

In the process of I31C^^: TW2958PA state "01"), the bistable programmable resistive random access memory 600 firstly changes from the logic state "〇" (or the state "〇〇") to the logic state. 3" (or state "11")" and the first and second programmable resistive random access memory components 410, 510 also change from the reset state to the set state. The voltage supplied to the second bit line voltage Vb21330 may be a zero voltage or a small negative voltage, expressed by a mathematical expression: Vb2 - Vm = -Vi (jw < 0. The first bit line voltage Vbil 320 provides a positive voltage. In the set state, the area of the first programmable resistive random access memory component is smaller than the area of the second programmable resistive random access memory structure 510, so that the first programmable resistive random access memory The member 410 has a higher resistance than the second programmable resistive random access memory member 510. This represents that a high voltage drop occurs through the first programmable resistive random access memory component 410, expressed mathematically as | 71心1(|>丨%81^丨. If the absolute value of the first resistive random access memory voltage V1RRAM1313 is greater than the reset voltage (丨V1RRAM | >VRESET), the first programmable resistor is randomly stored. The memory member 410 is changed to a reset state (low resistance). If the absolute value of the second resistive random access memory voltage VmAM1314 is less than the reset voltage (|V2m« | <VmET), the second Program resistive random access memory The member 510 remains in the set state. The resistances of the first and second programmable resistive random access memory members 410, 510 are changed from the logic state "3" (or state "11") of the resistance value to the resistance value. (w/slave logic state 1 (or state "01"). For example, if the variable /=2, the variable/2=10 and the reset resistance of the second programmable resistive random access memory component 510 is equal to i?, when from logic state, 〇, 'change to, 3' when total 39

Uuml· : TW2958PA The resistance changes from 3i? to 30i?. When the logic state changes from "3" to "Γ", the total resistance changes from 30i? to 12i?. The two resistors Ril310 and IM312 are connected in series to the two-dimensional line BLil340 and Between BL21342. The voltages supplied to the bit lines are denoted as Vbl1320 and Vb21342, respectively, and the voltage leakage across the two resistors is VimdSIS and V2RIUMI respectively. The voltage between the two lines is Vb2_Vbl equal to VlRRAM. + V2R_. As shown in FIG. 5, FIG. 6, FIG. 8A to FIG. 8B, and FIG. 12, the area of the first programmable resistive random access memory device 410 is smaller than that of the second programmable resistance type. The area of the random access memory device 510 is small, so the resistance Ri is larger than Rz. The state of the resistive random access memory, and the resulting cell value are as shown in Table 1. This cell value corresponds to Relative to the overall resistance value. Table 1 status / value

Ri r2 cell reset reset 0 ("00,,) reset δ again 疋 1 ("01") set reset 2 ("10") 疋 set 3 ("11") It is worth noting that the first table The embodiment is represented by a small-endian structure. That is, the last component is a least significant digit (LSD) and a maximum of 40 131

TW2958PA Most significant digit (MSD). Other embodiments follow the big-endian mode, that is, the number system is saved, and the starting program is the same program, but the two memory units are reversed. The relationship of the mathematical derivation showing the state of each memory cell is described as shown in Figs. 8A to 8D. FIG. 8A illustrates that the memory cell having the first memory component includes the first programmable resistive random access memory component 41A and the first conductive member 420. And the second memory element M2 includes a second programmable resistive random access memory structure 510 and a second conductive member 52. (Here, the % components have low resistance in a reset state. If R can be As the resistance of the larger second programmable resistive random access memory structure 510, and then the resistance of the other first programmable resistive random access memory device 41〇 and the programmable resistive random access The certain value of the memory structure 510 is related. This embodiment shows that the resistance of the first programmable resistive random access memory component 410 is higher than that of the second programmable resistive random access memory structure 510. Therefore, the constant f is known to be larger than 丨, but other embodiments are semantically described as being reversed from the above. As shown, the difference in resistance exhibited by the 8A to 8D figures of this embodiment is due to the two-resistance type. The random access memory components are of different sizes. The smaller resistive random access memory components have a higher resistance value. In another embodiment (not shown), the two components use different materials to Get the same The difference in the structure of the two embodiments does not affect the representation of the relationship between the two. However, the difference can still be obtained by the constant ^. In this embodiment, the two-resistive random access memory The body members are approximately the same thickness (described in detail below), but differ in width to cause a difference in resistance.

: TW2958PA The two resistive random access memory components are arranged in series, and thus the resistance of the memory cells can all be represented by /i?, or . The lower order component M2 is switched to a set state having a relatively high resistance level as shown in Fig. 8B. The resistance level increases in proportion to the constant/2. Different materials have different constants depending on the characteristics or approval of a particular compound, but the relationship between the reset and set states of a given material can be determined by a relationship R to now nR as shown in Fig. 8B. Thus, the state illustrated in Figure 8B can be mathematically or described. • Similarly, Figure 8C shows the result of switching the resistive random access memory device 1^12 to the set state, leaving I in the reset state. In this embodiment, two members are formed in the same village material, and this constant η can describe the difference between the set and the reset, and allows the resistance value to be described. Derived a complete mathematical formula to describe the resistance of the memory cell. Finally, in FIG. 8D, the transition state of the transition RRAM component 沁, M2 to a set state is generated, and the transition i?~>/2i?(forM2) and /?·>/]//? (forMi) are generated. . This state can be expressed as or /2(l+/)i?. • The semantic relationship of the four cell values can be done as a whole in Table 2. The second table cell relationship relationship Cell value (l + /) i? - 0 ("00,') (nif) R 1 ("01") 2 ("10") nCHOR 3 ("1Γ) 42

131(^3⁄43⁄4 : TW2958PA An example of an inductive operation window can be realized by setting the parameter values η, / and P. If i?=l〇4Q, 22=10 and /=2, the resistance value of the four states can be expressed as 3χ104Ω. 1. 2χ105Ω, 2.1χ105Ω, and 3χ105Ω.—The detection voltage (read voltage) is 120mV, and the induced currents of the four states are 4 #A, 1#A, 0.6#A, and 0.4/zA, respectively. The difference voltage of the level operation can be set to 2·5βΑ, 0·8/ζΑ and 0.5//A. For an induced current higher than 2 5 //Α, a minimum resistance state can be defined as the state “〇” (or State "〇〇"). For induction currents less than 0. 5# Α, a maximum resistance • state can be defined as state "3" (or state "11"> for less than 〇8 /z A but less For a sense current of 2. 5 /z A, a low resistance state can be defined as state "1" (or state "01"). For detecting an induced current higher than 0.5//a but less than 0.8# A, The high resistance state can be defined as state "2" (or state "10"). The change in induced current is based on changes in the manufacturing process and changes in the nature of the material. The change in the thickness (or width) of the dielectric sidewall determines the area of the second programmable resistive random access memory device. The thickness and area determine the second programmable resistive random access memory. Therefore, the operation of a high quality multi-bit resistive random access memory requires a wide operating window. A higher constant and a higher coefficient ί can provide a wide operating window, thus avoiding product occurrence. Acknowledgment of error. By applying across the bit lines BL1 and BL2; the voltage is set to the desired value. The total value of the four voltages is sufficient to complete all possible values as shown in the table. Those skilled in the art It can be seen that there are some actual voltages available. In one embodiment, two positive voltages are used (here at 43

! : TW2958PA, VB2 measurement) and two negative voltages. The result is marked as two:: and. W. The absolute value of the applied voltage depends on the memory component and the material and dimensions. In this embodiment, it is shown that - high voltage =: (and then a low is L 5 volts (a) is a program-like reset" that is to drive the resistive random access to the reset state to generate Cell value. This procedure resets the transition process as a whole in Table 3 below.

As indicated above, the appropriate transition zone money Hh, such as the voltage drop, per: 邑 value V_* V·# exceeds the reset value. As the two resistive random access memory components are in the reset state, the overall value of the memory cells is 〇. The social reset status is the starting point for further operations. Since the unpredictable, '° effect occurs in the intermediate state transition, it is preferable to operate the .tT in any phase change step to reduce the unit to the reset state as the first step. In its opposite state, the cell value is 3, as shown in Table 4 below.

.1310^3⁄4 : TW2958PA Transition of Table 4-3 (Vb2-Vbl) = Vhigh Component Status Cell Value Action Element Status Cell Value Μι 0 0 Vi<Vset 1 3 m2 0 Y2>VsET 1 Apply a Vhigh high voltage, enough A voltage drop of more than two components of VsET is generated. This cell value is 11 or 3 of the binary as the two components are in the set state. To generate a cell value of 2, the procedure is as shown in Table 5 below. Transition of Table 5-2 (Vb2-Vbl)=Vlow Component State Cell Value Action Element State Cell Value Μι 0 0 Vl>VsET 1 2 m2 0 Y2<VsET 0 In this setting, this voltage bleed Vi is greater than one Set the state of the demand, so R! is the set state, but this voltage drop v2 is less than the set demand. This result causes Ri to be in a set state and R2 to be in a reset state, resulting in a cell value of two bits 01 or 2. The way to generate a cell value of 1 is shown in Table 6. It is more difficult to reach the value of 1 than other transitions. It can be clearly observed that if the two components start from the reset state, applying a voltage sufficient to generate the set state at V2 will inevitably be set at L, resulting in a value of 3 instead of 1. The solution is to first make the memory cells all set, as shown in the previous table. Then, from a cell 45

.1310235k : TW2958PA . Value 3 setting, apply -Vi. The voltage is sufficient for h instead of R to generate a reset state resulting in a two-bit cell value of 01 or 1. Transition of Table 6 3-1 (Vb2 - Vbl) = -Vl〇w Component Status Cell Value Action Element Status Cell Value Μι 1 3 | Vl | > Vreset 0 1 M2 1 1 V21 > Vreset 1 • Figure 14 The bistable programmable resistive random access memory 600 is illustrated in accordance with the present invention from a logic state "00" to three other logic states, a logic state "01", a logic state "10", and a logic state "11j". Flowchart 1400. In step 1410, the bistable programmable resistive random access memory 600 can be programmed from a logic state "〇〇" to a three logic state, a logic state "〇1", a logic state "10", and a logic state. "11". In step 1410, the bistable programmable resistive random access memory 600 is in a logic state "00". If the bistable programmable resist random access memory 600 is programmed from the logic state "〇〇" to the logic state "01", the bistable programmable resistive random access memory 600 is obtained in step 1420. First, the logic state "00" is programmed to the logic state "11", and then the logic state "11" is programmed to the logic state "01" in step 1430. In step 1420, the bistable programmable resistive random access memory 600 is programmed from a logic state "〇〇" to a logic state "11", and its bit/bit line voltage Vbl1320 and second bit line voltage yb2l330 The difference between the voltages is equal to the high voltage Vhigh 'in mathematical expression ybl-Vb2=Vhigh, this second 46

13103⁄43⁄4: The TW2958PA resistive random access memory voltage VmAM1314 is greater than the Vset voltage, and the first resistive random access memory voltage VlRRAM 1313 is greater than the VSET voltage. In step 1430, the bistable programmable resistive random access memory 6 is programmed from a logic state "11" to a logic state "01", and the first bit line voltage Vbl1320 and the second bit line voltage vb21330 The voltage difference between them is equal to a negative low voltage -V!. The stomach is expressed in the mathematical form as VwVwVw, the absolute value of the second resistive random access memory voltage VmAM1314 is less than the absolute value of the Vreset voltage' and the first resistive random access memory voltage Lu V1RRAM 1 3 1 3 is greater than VrESET The absolute value of the voltage. In step 1440, the bistable programmable resistive random access memory 600 is programmed from a logic state "00" to a logic state "10" between the first bit line voltage Vm1320 and the second bit line voltage Vb21330. The voltage difference is equal to a low voltage Vi. *, and expressed in mathematics as Vw-VbFV!. *, the second resistive random access memory voltage Vzmd314 is less than the Vsn voltage, and the first resistive random access memory voltage VmAM 1313 is greater than the Vset voltage. In step 1450, the bistable programmable resistive random access memory 600 is programmed from the _ logic state "00" to the logic state "11"' between the first bit line voltage Vm1320 and the second bit line voltage Vb2l330. The voltage difference is equal to the high voltage Vhuh, which is expressed by the mathematical expression as Vbl-Vb2=Vhigh, and the second resistive random access memory voltage V2mu 1314 is greater than the Vset voltage' and the first electrical random access memory voltage V1RRAM 1313 is nine times the vSET voltage. 15 is a diagram showing a bistable programmable resistive random access memory 6 〇〇 from a logic state “〇1” to three other logic states, a logic state “00”, a logic state “10”, and a logic state “10” according to the present invention. 47 of the logical state "11".

.1310253⁄4 : TW2958PA Flowchart 1500. In step 1510, the bistable programmable resistive random access memory 600 is in the logic state "〇1". In step 1520, the bistable resistive random access memory 6 is programmed from a logic state "01" to a logic state "00" and a voltage between the first bit line voltage Vbl1320 and the second bit line voltage Vb21330. The difference is equal to a negative high voltage -vhish, represented by the mathematical expression as Vbi-Vb2=-Vhigh, and the absolute value of the second resistive random access memory voltage V" 2RRAm 1314 is greater than the VRESET voltage, and the first resistive random The absolute value of the access memory voltage V1RRm1313 is greater than the Vreset voltage. • If the bistable programmable resistive random access memory 600 is programmed from the logic state "01" to the logic state "10", the bistable programmable resistive random access memory 600 is firstly used in step 1530. The logic state "01" is programmed to the logic state "00", followed by the logic state "00" to the logic state "10" in step 1540. In step 1530, the bistable programmable resistive random access memory 600 is programmed from a logic state "01" to a logic state "〇〇", between the first bit line voltage Vbil320 and the second bit line voltage Vb21330. The voltage difference is equal to a negative high voltage _ -Vhigh, expressed as Vbi-Vb2=-Vhigh in a mathematical expression, the absolute value of the second resistive random access memory voltage V2RRax1314 is greater than the VRESET voltage, and the first resistive Random access memory 1 "The absolute value of «1313 is greater than the VRESn voltage. In step 1540, the bistable programmable resistive random access memory 600 is programmed from the logic state "〇〇" to the logic state "1", and the first bit line voltage Vbil320 and the second bit line voltage The voltage difference between Vb2l330 is equal to a low voltage Vl. *' is expressed in the mathematical form as VbrVb^Vu, and the second resistive random access memory voltage VmAM1314 is greater than the Vresh voltage, and the 48th

1310^3⁄43⁄4 : TW2958PA A resistive random access memory voltage V1RRAM1313 is less than the VRESET voltage. In step 1550, the bistable programmable resistive random access memory 600 is programmed from a logic state "01" to a logic state "11", between the first bit line voltage Vbd320 and the second bit line voltage Vb21330. The voltage difference is equal to a high voltage Vhish, expressed as Vbl-Vb2=Vhigh in a mathematical expression, the second resistive random access memory voltage V2mM1314 is greater than the VSET voltage, and the first resistive random access memory voltage is greater than VSET Voltage. • Figure 16 illustrates a bistable programmable resistive random access memory 600 programmed from a logic state "10" to three other logic states, a logic state "00", a logic state "01", and Flowchart 1600 of logic state "11". In step 1610, the bistable programmable resistive random access memory 600 is in a logic state "1". In step 1620, the bistable programmable resistive random access memory 600 is programmed from a logic state "1" to a logic state "〇〇", its first bit line voltage Vbl 1320 and a second bit line voltage. The voltage difference between 1^1330 is equal to a negative high voltage _ -Vhuh, expressed as Vbi-Vb2=-Vhigh in mathematical expression, and the absolute value of the second resistive random access memory voltage VmAM 1314 is greater than the Vreset voltage. And the absolute value of the first resistive random access memory voltage Virram1313 is greater than the Vreset voltage 0. If the bistable resistive random access memory 600 is programmed from the logic state "10" to the logic state "0" In step 1630, the bistable programmable resistive random access memory 600 is first programmed from a logic state "10" to a logic state "u", followed by a logic 49 in step 1640.

-* : TW2958PA status "11" is programmed to logic state "〇1". In step 1630, the bistable programmable resistive random access memory 600 is programmed from a logic state "10" to a logic state "11", between the first bit line voltage Vbl1320 and the second bit line voltage Vb21330. The voltage difference is equal to the high voltage VhUh, expressed as Vbl-Vb2 = Vhigh, the second resistive random access memory voltage V2mMl314 is greater than the Vsn voltage, and the first resistive random access memory voltage Vimul313 is greater than the Vset voltage . In step 1640, the bistable programmable resistive random access memory 600 is programmed from the logic state "11" to the logic state "10", and the first bit line voltage Vbl1320 and the second bit line voltage Vb21330 The voltage difference is equal to the negative low voltage -V^, expressed as VM-Vb^-Vu in a mathematical expression, and the absolute value of the second resistive random access memory zero voltage VmAn 1314 is greater than the absolute value of the Vreset voltage, and The absolute value of the first resistive random access memory voltage Vuram 1313 is smaller than the absolute value of the Vreset voltage. In step 1650, the bistable programmable resistive random access memory 600 is programmed from a logic state "1" to a logic state "11", the first bit line voltage ν^1320 and the second bit. The voltage difference of the line voltage Vb21330 is equal to the high voltage Vhigh', which is expressed by the mathematical expression as Vbl-Vb2=Vhigh, and the second resistive random access memory voltage %13 is greater than the Vsn voltage, and the first resistive random access The memory voltage V1Rrm1312 is greater than the Vsn voltage. Figure 17 is a diagram showing the bistable programmable resistive random access memory 600 from the logic state "1" to the other three logic states, the logic state "00", the logic state "01", and the logic state "01" according to the present invention. The flow of logic state "10" is 圊Π00. The bistable programmable circuit in step Π10

13102ii2^: TW2958PA Resistive random access memory 600 is doubled from logic state "11" to logic state "00", which is the voltage difference between the first bit line voltage Vbl1320 and the second bit line voltage Vb21330. Equal to the negative high voltage -Vhigh, expressed as Vbi-Vb2=-Vhigh in the mathematical expression, the second resistive random access, the absolute value of the barrier voltage VmAM1 314 is greater than the Vreset voltage, and the first resistive random access memory The absolute value of the voltage ViRtmfl 313 is greater than Vreset%^. In step 1730, the bistable programmable resistive access memory 600 is programmed from the logic state "11" to the logic state "〇1", the first bit of the φ element line voltage Vm1320 and the second bit line voltage. The voltage difference between Vb21330 is equal to the negative low voltage 'calculated as Vbi~Vb2=_vl()w, the absolute value of the second resistive random access memory voltage VmAiil314 is greater than the absolute value of the Vreset voltage' and The absolute value of a resistive random access register body voltage Vim «1313 is less than the absolute value of the VRESET voltage. If the bistable programmable resistive random access memory 600 is programmed from the logic state "11" to the logic state "10", in step 1740 the bistable programmable resistive random access memory 6 is first logically State r 11" • Programmatically to logic state "00", followed by logic state "00" to logic state "10" in step 175. In step 1740, the bistable programmable resistive random access memory 60() is programmed from a logic state "11" to a logic state "00", the first bit line voltage Vbi 1320 and the second bit line. The voltage difference between the voltages Vb21330 is equal to the negative high voltage -Vhigh, expressed as VbrVb2=-Vhigh' in the mathematical expression. The absolute value of the second resistive random access memory voltage VmAM1314 is greater than the Vreset voltage, and the first resistive random The absolute value of the access memory voltage VlRRAM1313 is greater than the Vreset dust. At 51

, 131〇: TW2958PA. In step 1750, the bistable programmable resistive random access memory 6 is programmed from a logic state "〇〇" to a logic state "10", and its first bit line voltage The voltage difference between Vbl1320 and the second bit line voltage vb21330 is equal to the negative low voltage - 'Expressed as VbrVfViM in a mathematical expression, and the second resistive random access § Remembrance voltage V2RRAm1 31 4 is greater than VsET, and The first resistive random access memory voltage VurAm 1313 is smaller than the VsET voltage. For additional information on the fabrication, material composition, use, and operation of phase change random access memory devices, see U.S. Patent No. 11/155,067, Thin Film F峨 Phase Chang and

Manufacturing Method ” , ,, * This patent was filed on June 17, 2005 and is owned by the assignee of this application, including the reference cited herein, although the invention is not The present invention is used to define the present invention. 2 The preferred embodiment of the present invention is disclosed in the above-mentioned technical field, and has various modifications and refinements in the technical field of the present invention. • The scope of protection as defined by the scope of interest shall be attached to the application form 52

131023⁄4: TW2958PA [Simplified Schematic] FIG. 1 is a schematic diagram showing a bistable resistive random access memory array according to the present invention. Figure 2 is a block diagram showing an integrated circuit diagram of a resistive random access memory structure in accordance with a preferred embodiment of the present invention. Figure 3 is a simplified diagram showing the steps of deposition and lithography of two programmable resistive random access memory layers for fabricating a bistable resistive random access memory layer in accordance with the present invention. FIG. 4 is a schematic diagram showing a step of manufacturing a bistable resistive random access memory according to the present invention, etching to a second conductive layer, depositing a second conductive layer adjacent to the 10,000; first conductive member and first A dielectric sidewall of a programmable resistive random access memory device. Figure 5 is a block diagram showing a step under the fabrication of a bistable resistive random access memory in accordance with the present invention, etched through a second resistive random access memory layer. Figure 6 is a simplified schematic diagram showing the structure of a resistive random access memory cell in accordance with the bistable resistive random access memory of the present invention. Fig. 7 is a view showing an example of a current_electrical (I_v) curve of a bistable resistive random access memory having a resistive random access memory layer according to the present invention. Figure 8A is a simplified schematic diagram showing a bistable resistive random access s memory having two resistive random access memory components each located in a reset (RESET) state in accordance with the present invention. Figure 8B illustrates two settings (SET) 53 in accordance with the present invention.

131 view: A simple schematic diagram of the bistable resistive random access memory of the TW2958PA and the RESET state resistive random access device. Figure 8C is a simplified schematic diagram of a bistable resistive random access memory having two resistive random access memory components in a set (SET) and reset (RESET) state in accordance with the present invention. Figure 8D is a simplified schematic diagram of a bistable resistive random access memory having two resistive random access memory components in a set (SET) state in accordance with the present invention. • Figure 9 is a graphical representation of the mathematical relationship of four logic states of a bistable resistive random access memory in which two resistive random access memory components are connected in series to provide four logic states in accordance with the present invention. Figure 10 is a schematic diagram showing a bistable random access memory in which a plurality of electrical I1 and random access memory components are connected in series to provide multiple bits per memory cell in accordance with the present invention. 11 is a schematic diagram of a bistable resistive random access memory having an etch process on the first and second resistive random access memory layers and a deposited dielectric sidewall according to the present invention. Figure 12 is a schematic diagram showing a bistable resistive random access memory having a multi-resistive random access memory device and a plurality of conductive members after removing the dielectric sidewalls according to the present invention. Figure 13 is a diagram showing a bistable resistive random access memory device for applying a voltage to program a two-resistance random access memory device in accordance with the present invention. Figure 14 is a diagram showing bistable resistive random access in accordance with the present invention.

I31Q2^fe : The flow chart of the TW2958PA memory from the logic state "00" to the other three logic states, the logic state "01", the logic state "10", and the logic state "11". Figure 15 is a diagram showing the bistable resistive random access memory from the logic state "01" to the other three logic states, the logic state "00", the logic state "10", and the logic state "11" according to the present invention. Flow chart. Figure 16 is a diagram showing the bistable resistive random access memory from the logic state "10" to the other three logic states, the logic state "00", the logic state "01", and the logic state according to the present invention. Flow chart of 11". Figure 17 is a diagram showing the bistable resistive random access memory from the logic state "11" to the other three logic states, the logic state "00", the logic state "01", and the logic state "10" according to the present invention. Flow chart. Lu [Major component symbol description] 100: Memory array 123, 124, 262: word line 128: common source line, 132, 133: lower electrode member, 134: upper electrode member 135: sidewall pin memory cell 141, 142, 264: bit line 55

131: TW2958PA 145: Y-decoder and a word line driver 14 6 : X-decoder and a set of sense amplifiers 150, 151, 152, 153 :: access transistor 200, 275: integrated circuit 260 Memory array 261: column decoder 263: pin decoder φ 26δ: bus bar 266: sense amplifier and data input structure 267: data sink drain 268: bias arrangement supply voltage 269: bias arrangement state machine 271: Data input line 272: data output line 274: other circuits • 300, 1000, 500: bistable resistive random access memory 310: first programmable resistive random access memory layer 312: first conductive layer 320: The second programmable resistive random access memory layer 322: the second conductive layer 330: the mask 410: the first programmable resistive random access memory member 412, 420: the first conductive member 56

131: TW2958PA 430: first dielectric sidewall 510: second programmable resistive random access memory component 512, 520: second conductive member 600: bistable programmable resistive random access memory 610 : bottom layer 620: contact hole 630: intermediate dielectric layer 700: current-voltage curve example diagram • 710: voltage 720: current 730: reset state 740: set state 750: read voltage 752: dashed line 810 · • resistance i? 820, 860: resistance / i? _ 830, 880: resistance 850, 870: resistance Μ 910: logic state "0" 920: logic state "1" 930: logic state "2", 940: logic state "3" 1010 : third resistive random access memory layer 1012 : third conductive layer 57

· TW2958PA 1020: (nl)th programmable resistive random memory layer 1022: (nl)th conductive layer 1030: nth programmable resistive random access memory layer 1032: nth conductive layer 1110: second Electrical sidewall 1200: bistable programmable resistive random access memory 1210: third programmable resistive random access memory component 1220: third conductive member

1300: circuit system 1310: first resistor Ri 1312: second resistor R2, 1313: first programmable resistance random access voltage V1RRA « 1314: second programmable resistance random access memory voltage V2RRA « 1316 : additional programmable resistive random access memory voltage 1320: first bit line voltage Vbl 1330: second bit line voltage Vb2

1340: first bit line BLi 1342: second bit line BL2 1400, 1500, 1600, 1700: flowchart 58

Claims (1)

TW2958PA X. Patent Application Range: A method of operating a resistive random access memory device, having a -first conductive member, located in a -st programmable resistance random access. The first-programmable resistive random access memory component is located on the second conductive member, and the second conductive member is located on the second programmable resistive random access memory component. The method includes at least the first programmable resistive random access memory component and the second programmable resistive random access memory component connected in series, the first programmable resistive random access memory component having One representing a first resistance value, the second programmable resistive random access memory component has an area equal to a second resistance value R, and the second programmable resistive random access memory component has The first programmable resistive random access memory component has a first logic state ("00" state) and a second logic state. The first programmable resistive random access memory component has a larger area than the first programmable resistive random access memory component. ("or state"), the second programmable resistive random access memory component has a third logic state ("10" state) and a fourth logic state ("1 state"; Forming a dielectric sidewall on the first conductive member and the first programmable resistive random access memory member and on the κ surface of the second conductive member. The second programmable resistive random access The memory member has an area that is a function of the thickness of the first dielectric sidewall; and changes the logic state of the first and second programmable resistive random access memory 59: TW2958PA components to another The logic state, the logic state is a function of the material coefficient η and the thickness f of the dielectric sidewall. 2. The method of claim 1, wherein the first logic state operates according to a mathematical formula (1 + /) /?. 3. The method of claim 1, wherein the second logic state operates according to a mathematical formula. 4. The method of claim 1, wherein the third logic state operates according to a mathematical formula. 5. The method of claim 1, wherein the fourth logic state is based on a mathematical formula + operation. 6. The method of claim 1, further comprising: connecting a first bit line voltage Vbl to a top surface of the first conductive area; and connecting a second bit line voltage Vb2 to the second a bottom surface of the programmable resistive random access memory device; generating a first resistive random access memory voltage v1RRAM between the first conductive member and the first programmable resistive random access memory device; And generating a second resistive random access memory voltage VmAM between the first programmable resistive random access memory component and the second programmable resistive random access memory component. 7. The method of operating a resistive random access memory device according to claim 6, wherein the first and second programmable resistive random access memory components are in a reset (RESE:T) state. . The method of claim 6, wherein the memory device changes from the first logic state to the second logic state from the first logic state, thereby changing from the first logic state to the In the transient state, when Vbl-Vb2 = Vhigh, VmAM&gt;VsET and V〖rra«&gt;Vset', and when changing from the transition state to the second logic state, 'set Vb2-Vbl=-V1(^&lt;〇, I V2RRAM 丨 &lt; 丨VrESET I and 丨VlRHAM 丨&gt; | VrESET I. The method of claim 6, wherein the memory device is set by Virram&gt;Vset by the first logic state 10. The method of claim 6, wherein the memory device is set by Vbi-Vb2=Vhish' ¥2 (1&gt;乂3£ with v1RRAM>VsET 11. The operation method of claim 6, wherein the memory device is set by Vbi-Vb2=-Vhigh ' |v2RRAm|&gt;Vreset And | VlRRAM丨&gt;VrESET is changed from the second logic state to The method of claim 6, wherein the memory device moves from the second logic state to the third state from the second logic state, thereby changing from the first state to the In the transient state, when Vbl_Vb2 = _Vhigh ' |V2RRAm|&gt;VrESET and |ViRRAm|&gt;VrESET ' and when changing from the transition state to the third state, Vbi-Vb2=ViQW, V2m«&gt;VsET and VlRRAM< The operating method of claim 6, wherein the memory device is changed from the second logic state by setting Vbl-Vb2=Vhigh, V2RRAM&gt;Vsn and VlRRAM&gt;VsET The fourth logic state is the same as the operation method described in claim 6, wherein the memory device is set by Vbl-Vb2 = _Vhigh, |V2RRAM|&gt;VRESET and The operating mode of the invention is changed from the third logic state to the second logic state. a logic state, when changing from the third logic state to the transition state, setting Vbl-Vb2 = Vhigh, V2I?liAM&gt;VsET and VlRRAM&gt;Vsn, and changing from the fifth logic state to the second logic state VVVbfVb, .V2RRAM|&gt;|VRESET|a|VlRRAM|&gt;|V RESET 1 ° 16. The method of claim 6, wherein the memory device is from the third logic state To the fourth logic state, 'Vbl-Vb2 = Yhigh, V2RRAM>VsET and VlRRAM<V&quot;sn 0 17. The method of claim 6, wherein the memory device is set by Vbl-Vbas- Vhigh, |V2RRAM|&gt;VRESET and 丨>VRESET changes from the fourth logic state to the first logic state. 18. The method of claim 6, wherein the memory cartridge device is changed from the fourth logic state by setting VbrVfVlow, |V2RRAm|&gt;|VRESET, and 丨VlRRAM丨&lt;|VRESET丨The second logic state is the method of claim 6, wherein the memory device changes from the fourth logic state to the first:. logic state via a transition state, such that from the fourth logic When the state changes to the transition state'. Set Vbl-Vb2 = - Vhigh, |.V2RRA«|&gt;VrESET and |ViRRAm|&gt;VrESET' and when changing from the transition state to the fourth logic state, set Vbl- Vb2=Vi. * ’ V2RRAM>VsET and VimM<VsET ° 62