TWI305043B - Structures and methods of a bistable resistive random access memory - Google Patents

Description

1305043 • IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to high-density memory elements based on phase-converted memory materials (including chalcogenide-based materials and other materials), and The method used to make these components. [Prior Art] Memory materials based on phase conversion are widely used in reading and writing light discs. These materials include at least two solid phases, including, for example, a solid phase that is largely amorphous, and a solid phase that is substantially crystalline. Laser pulses are used to read and write optical discs to switch between the two phases and to read the optical properties of the material after phase inversion. Such phase-converting memory materials, such as chalcogenides and the like, can be converted by crystal phase by applying a current suitable for the current in the integrated circuit. In general, the amorphous state is characterized by a higher electrical resistance than the crystalline state, and this resistance value can be easily measured and used as an indication. This feature raises concerns about the use of programmable resistive materials to form non-volatile memory circuits that can be used for random access. The transition from amorphous to crystalline is generally a low current step. Transition from a crystalline state to an amorphous state (hereinafter referred to as a reset) is generally a high current step that includes a brief high current density pulse to melt or destroy the crystalline structure, after which the phase transition material will Rapid cooling suppresses the phase transition process so that at least a portion of the phase inversion structure is maintained in an amorphous state. In an ideal state, the magnitude of the reset current that causes the phase change material to transition from a crystalline state to an amorphous state should be as low as possible. To reduce the magnitude of the reset current required for resetting, this can be achieved by reducing the size of the phase change material components in the memory and reducing the contact area of the electrodes with the phase change material, so that this can be reversed.

Chinese snec -MacrnnixP940?.ri^ final 5 1305043 The material change component applies a small absolute current value to achieve a higher current density. One method developed in this field is to create tiny holes in an integrated circuit structure and fill these tiny holes with a trace of programmable resistance material. The patents dedicated to such microscopic holes include: 'Multibit Single Cell Memory Element Having Tapered Contact', published on November 11, 1997, 'Multibit Single Cell Memory Element Having Tapered Contact', inventor Ovshinky; USA announced on August 4, 1998 Patent No. 5,789,277, "Method of Making Chalogenide [sic] Memory Device", inventor Zahorik et al., US Patent No. 6,150,253, issued November 21, 2000, ''Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same", the inventor is Doan et al. A particular problem with conventional phase-converted memories and structures is the heat dissipation effect they produce. In general, the prior art teaches how to use metal electrodes on both sides of a phase change memory element, and the size of the electrodes is approximately equal to the phase change member. These electrodes act as heat sinks, and the high thermal conductivity of the metal quickly diverts heat away from the phase change material. Since the phase transition phenomenon is the result of heating, the heat dissipation effect causes a larger current to be required to produce an ideal phase transition phenomenon. In addition, problems arise when manufacturing these devices on very small scales and the stringent process variables required to produce large-size memory devices. Preferably, a memory cell structure is provided which includes a small size and a low reset current, and a method for fabricating such a structure which satisfies a strict process variable specification for producing a large-sized memory device. Moreover, it is preferred to provide a peripheral circuit that is compatible with the structure and that is compatible with the fabrication of the same integrated circuit. 1305043 SUMMARY OF THE INVENTION The present invention describes a structure and method for forming a bistable resistive random access memory that reduces the amount of heat dissipated from the electrode by mediating a heated region in the memory cell component. The heated region is defined in a core member including a programmable resistive memory material that contacts an upper programmable resistive memory member and a lower programmable resistive memory member. The sides of the programmable resistive memory member are aligned to the sides of the bottom electrode including the tungsten plug. The programmable resistance member and the bottom electrode act as a first conductor such that heat lost from the first conductor can be reduced. The programmable resistive memory material in the core component is in contact with an upper programmable resistive memory material. The upper programmable resistive memory material interacts with a top electrode as a second conductor such that heat lost from the second conductor can be reduced. In a first object of the present invention, a memory device includes: a top electrode structure vertically separated from a bottom electrode, the bottom electrode including a plug; and an upper programmable resistance memory member having a top and a top a contact surface electrically contacting the electrode structure; the lower programmable resistance memory member has a contact surface in electrical contact with the bottom electrode, the side of the programmable lower resistance member being aligned with a side of the plug; and The core component includes a programmable resistive memory material disposed within a sidewall to define a heating region and disposed between the upper and lower programmable resistive memory members. The core member is in electrical contact with the upper and lower programmable resistance members. In a second object of the present invention, a memory device includes: a first electrode vertically separated from a second electrode, the second electrode including a plug; and an upper programmable resistance memory member Have an electrical contact

Chinese soec.-MacronixP940202 final 7 1305043 Contact table to the first electrode - it has - electrical junction ^ can be programmed resistor memory member, the side contact surface of the resistance member ' can be programmed: -=:: = in the resistance _ system between the 'the member is electrically connected to the 'electrical wall or thick window φ

# ^ ^ ;,V,^ ^ t, ^ Γΰ LJU is a heating zone. In this case, the low heat dissipation effect caused by the twisting of the 埶3 reduces the heat from the & loss of the 'reinforced area'; its metal bit line or crane check plug, the top electrode (for example - all 属 mf "In addition, from the resistance of the material recall material" lost heat ^. A programmable resistance memory material is placed in the top electrode, ..., "t shoe-type resistance memory material has a low thermal conductivity, therefore: lost The heat. A programmable resistive memory material has a top portion of the base, which reduces the amount of heat lost from the tungsten plug due to the programmable resistive memory. In addition, the resistive memory material at the top of the crane plug self-aligns to the width of the tungsten plug. The jfe, array includes a plurality of such memory elements and access cells, arranged in columns and rows of a high density array. The access transistor is included in the semiconductor base (4) including the source and drain regions, and the gate reduced to the word line, the word line being disposed along the columns of the memory cells. These memory cell lines are formed on the second layer above the access transistor of the integrated circuit.

Chinese SDec.-MacronixP940202 final 8 !3〇5〇43 S= extends from the base of the corresponding access transistor to the slant: 成, and has the corresponding record; element:: above the memory cell :歹...(4) The electrode of the memory cell's foot, extending to the epipolar line 7b: in the middle, the two columns of memory cell lines share the point, the line is connected, and is substantially parallel along the word line in the array.

Preferably, the memory member of the present invention that reduces heat dissipation reduces the amount of heat that can be dissipated from the core component. The present invention also reduces the structure of the program. The following is a detailed description of the structure of the present invention. The program is not defined by the definition of the present invention.实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施'And the implementation of the invention can be carried out using other features, the bulls, the method and the implementation«. Similar elements in each patch are specified by similar numbers.卞 Refer to Section 1 for a schematic diagram of a memory array, which is implemented in accordance with the method of the present invention. In the picture! The common source line H-shaped turns 123 and 124 are arranged substantially parallel to the γ-axis. The bit lines 141 and 142 are arranged substantially in parallel along the X axis. Thus, a Υ decoder and a word line driver in block 145 are coupled to word lines 123, 124. The -X decoder and the set of sense amplifiers in block 146,

Chinese soec.-MaCT〇nixP940202 final 9 1305043 is coupled to bit lines 141 and 142. A common source line 128 is coupled to the source terminals of the access transistors 150, 151, 152, 153. Access transistor 15 dice

The gate is coupled to the word line 丨23. The gate of the access transistor 151 is coupled to the sub-line 124. The gate of the access transistor 152 is coupled to the word line 123. The gate of the access transistor 153 is coupled to the word line 124. The drain of the access transistor 150 is coupled to the sidewall of the bottom electrode member of the memory cell 135, which has a top electrode member 134. The top electrode member 134 is coupled to the bit line 141. Similarly, the drain of the access transistor 1 $ j is coupled to the sidewall of the bottom electrode member 133 of the memory cell, which also has the top electrode member 137. The top electrode member is coupled to the bit line 141. Access transistors 152 and 153 are also coupled to bit line 142 of the corresponding sidewall memory cells. As can be seen from the figure, the common source line 128 is shared by the two columns of memory cells, and in this figure, one column is arranged in the Y-axis direction. In other embodiments, these access transistors can be replaced by diodes, or other structures that control the current to be selected for reading and writing data in the memory array. " As shown in Fig. 2, in accordance with an embodiment of the invention, a simplified block diagram of an integrated circuit is shown. The integrated circuit 275 includes a memory array on a semiconductor substrate that utilizes sidewall active legs. The bistable separation is performed by accessing memory cells. A column of decoders 261 is woven into a number of το lines 262' word line lines along the memory array 26 :: line decoding, please lightly connect to a plurality of bit lines J line and two: ^ Recall the array fine Each line is set to pass from the address in the 26° frame of the = 化 经由 经由 经由 - - - - - - 263 263 263 263 263 263 263 263 263 263 263 263 263 263 263 263 263 263 263 263 263 263 The product 267 is coupled to the foot damper 263. Data from the integrated circuit ^

Chinese spec.-MacronixP940202 final 10 1305043 source input / output 埠, or the internal and external data of the integrated circuit to ί: = via the data wheel 271 to transfer data to the box into the structure. In the illustrated embodiment, other circuitry 274 is included on the integrated circuitry, such as 'rc ffl a 吩 guzzled, for example, a general purpose processor or a special purpose application, or can provide a single wafer system function. The mode is combined by a thin film fuse bistable resist random access memory cell array. The data is transmitted from the sense amplifier in block 266 to the integrated circuit 275 via the data output line 272, '埠 or other data destination located inside or outside of the integrated circuit 275. In the present embodiment, a controller of the biasing arrangement state 269 is used to control the applied bias supply voltage 268, such as reading, programming. The voltage is erased, erased, erased, and stylized. The controller can be implemented using a specific purpose logic circuit well known in the art. In an alternate embodiment, the controller includes a general purpose The processor, the general purpose processor can be arranged on the same integrated circuit' and the integrated circuit executes a computer program to control the operation of the component. In another embodiment, The controller is implemented by combining a specific purpose logic circuit with a general purpose processor. As shown in FIG. 3, it shows a type I programmable resistance memory according to a first embodiment of the present invention. A bistable resistive random access memory 300 of the material is formed on a semiconductor substrate 310. The access transistor is included in the p-type substrate 310. The inner action is an n-type terminal 312 of one of the common source regions and n-type terminals 314 and 316 acting as a drain region. The polycrystalline stone (gate) lines 320, 322 form a gate for accessing the transistor. The interlayer dielectric layer 330 includes dielectric buffers 330a, 330b, 330c, wherein the dielectric fill 330b is formed over the polycrystalline stone lines 320, 322. This layer is patterned and

English snec.*Macronix P940202 final 11 1305043 Forms a conductive structure comprising a common source line and plug structures 326, 328. The electrically conductive material can be a crane or other material and composite material suitable for use as a plug and wire structure. The common source line contacts the source region and acts as a common source line along a column in the array. The plug structures 326, 328 are in contact with the drain terminals 314 and 316, respectively. The plug structure 326 is etched at the top' and is filled with a programmable resistive memory material 340. The sides of the programmable resistive memory material 340 are aligned to the sides of the plug structure 326. The base structure 328 is engraved on top of it and filled with a programmable resistive memory material 342. The sides of the programmable resistive memory material 342 are aligned to the sides of the plug structure 328. A dielectric fill layer 350 is disposed over the dielectric fill 33A, the electrode member 340, the dielectric fill 330b, the electrode member 342, and the dielectric fill 330c. In some embodiments, the dielectric fill layer includes a relatively good thermal insulator and electrical insulator to provide a thermal and electrical insulating effect on the heated region 365 of the I-type structure. The dielectric fill layer 35 is etched and filled with dielectric sidewalls 360, 362. The dielectric sidewalls 36 are located between a first dielectric fill section 350a and a second dielectric fill section 35A, and the dielectric sidewalls 362 are located in the second dielectric fill section. Between 350b and the third dielectric fill section 350c. The programmable resistive memory material 370 located in the sidewalls 36, 362 is in contact with the programmable resistive memory material 340, 342. - The metal bit line 38G is located above the programmable electric (four) memory material 37〇. The bistable resistor random access memory 3 has a heating region 365 which is located in the opening of the dielectric sidewall 36. Bistable Resistor Random Access Memory 300! The structure is referred to as a component of the programmable resistive memory material 370 (upper programmable electrode member), a heating region 365 including a programmable resistive memory material, and a programmable resistive material (lower programmable resistor) Memory component) 34〇d

English soec.-Macronu P940202 final 12 1305043 * The method for fabricating the bistable resistive random access memory 300 is described in detail with reference to Figures 4-11. Figure 4 is a first step of a method for fabricating a bistable resistive random access memory according to a first embodiment of the present invention, which forms a simplified transistor structure. The transistor structure 4 includes an n-type terminal 312 functioning as a common source region, and n-type terminals 314 and 316 acting as a selection region over the p-type substrate 310. Although the illustrated crystal structure 400 is a common source structure, the present invention can be used in other types of transistor designs. The polysilicon gate line 32, 322 forms the gate of the access transistor. The interlayer dielectric 33 includes dielectric fills 330a, 330b, 330c, wherein a dielectric fill 330b is formed over the polysilicon lines 320, 322. Some materials suitable for use in the interlaminar dielectric 33 Å include a boron borosilicate glass (BPSG) oxide and a plasma enhanced ethyl phthalate (PETEOS) oxide. This layer is patterned and forms a conductive structure comprising embolic structures 326 and 328. The electrically conductive material can be used in conjunction with embolization or other materials and composites suitable for use as a plug and wire structure. The plug structures 326, 328 are in contact with the poleless terminals 314, 316, respectively. In Fig. 5, in accordance with a first embodiment of the present invention, a second step of a method for fabricating a bistable resistive random access memory 500 is shown in green, including depositing a resistive memory material. And grinding. A top portion of the plug is directly etched to remove tungsten to create a contact hole 510 from the plug 326, which has an aspect ratio of about 1:1. Similarly, the top of plug 328 is directly etched to remove tungsten and a contact hole 512 is created from plug 328 with an aspect ratio of about 1:1. The selectivity of the interlayer dielectric layer 33 is sufficiently high to protect the interlayer dielectric layer 33 from etching damage. A chemical suitable for tungsten etching is sulfur hexafluoride (SF6). The depth of tungsten etching is selected relative to the size of a contact hole. In one embodiment, the tungsten etch depth of the plug 326 is about 2 〇〇 nm with a contact hole of 〇 2 μπ.

A SD485. Each upper surface of the programmable resistive memory material 34, 342 is ground to remove excess programmable memory material 34, 342 that may be exposed from contact holes 510, 512. Examples of the polishing process include chemical mechanical polishing processes followed by brush cleaning and liquid and/or rolling body cleaning procedures, as is well known in the art.

In Fig. 6, a cross-sectional view of Fig. 6A illustrates a third step for fabricating a bistable resistive random access memory, including forming a dielectric layer 35, followed by dielectric sidewall etch. The dielectric layer 35 is deposited on the interlayer dielectric 330 and the programmable resistive memory material 34, 342. One of the properties of this dielectric layer 350 is its low thermal conductivity. The etching of the dielectric layer holes extends to the contact holes, the critical dimension of which is equal to or smaller than the size of the contact holes. Dielectric sidewalls 360, 362 also have low thermal conductivity properties. A conformal dielectric deposition process using a chemical vapor deposition process is used to fabricate dielectric sidewalls 360, 362 having a thickness that is less than one half of the contact holes. The dielectric sidewalls 360, 362 are dry-engraved using a compound having a fluorine-based compound. The engraving of the dielectric sidewalls 360, 362 will stop when the depth reaches the upper surface of the programmable resistive memory material 340, 342. ^ Dielectric fill layer 350 may include hafnium oxide, hafnium oxynitride, tantalum nitride, aluminum oxide, other low K (low dielectric constant) dielectric, or monooxide-nitride-oxide (ΟΝΟ Or a bismuth-oxide-nitride-oxide (SONO) multilayer structure. "Low Κ value" means a low dielectric constant. Alternatively, the filler may comprise an electrical insulator comprising one or more elements selected from the group consisting of: ♦, titanium", nitrogen, oxygen, and carbon. In the dielectric layer 35, including elements of the dioxide eve, The thermal conductivity of the filler is lower than that of cerium oxide by 0.014 J/cm*degK*sec. Representative thermal insulation materials include enpr fin»1 14 1305043, which is composed of ruthenium, carbon, oxygen, fluorine, and hydrogen. Composite material. A pure example of a thermal insulating material that can be used for a thermally insulating filling layer, including oxidizing, polythene, polyamidamine, and fluorocarbon polymers. Others can be used in thermal insulating filling layers. Examples of materials include fluorinated cerium oxide, silsesquioxane, polyfluorene ether (p〇iyaryiene lamp), parylene, fluoropolymer, fluorine-containing amorphous carbon , diamond-like carbon, porous diacetate, mesoporous nitric oxide, porous austenite, porous polyamidamine, and porous polyarylene ether. Single or composite layers are available Thermal insulation and electrical insulation effects. ® Figure 7 - Sectional view 700, which is shown A fourth step of the method of fabricating a bistable resistive random access memory includes depositing a second resistive memory material 370 and a metal bit line 380, followed by patterning of the bit lines. The second resistive memory material 370 is deposited. Within the dielectric sidewalls, and over the first dielectric fill section 350a, the second dielectric fill section 35〇b, and the third dielectric fill section 350c. The metal bit line 38 Located on the programmable resistive memory material 370. The metal bit line 380 can be used with a conductive material 'including titanium nitride, nitride button, titanium nitride/aluminum copper, nitride button/copper, and other types. Similar to the conductive material. Then, the bit line is patterned, and the direction of the bit line is perpendicular to the direction of the gate, the source, and the drain. The side of the bit line forms a straight line, which includes the upper line. The resistive memory material is a thin film laminated with a metal bit line 380. The metal bit line 38 is connected to the upper resistive memory material 37 and is referred to as an upper electrode. Alternatively, the metal bit line 380 is referred to as an upper electrode. , which is located on the upper programmable resistance material 370 ^ The upper middle programmable resistive memory material 370 reduces the amount of heat lost to the metal bit line 380. A feature of the invention is that the upper electrode 'i.e., the metal bit line' is not patterned to define a particular memory cell. In the patterned upper electrode, the metal bit line is in a single

Chinese soec.-MacronixP9402n2 final 15 1305043 The sides of the memory are etched to create a columnar structure. In the present invention, the metal position το line 38G extends across the entire bit line (e.g., a plurality of cells) so that the metal bit and the line are used as the top electrode and are shared by a plurality of memory cells. Figure 8 is a green area shown in the resistive memory material. "Electrical sidewalls 360 define a relatively small contact hole that is deposited with the resistive memory material 34 下 deposited on top of the contact plug 326, compared to the resistive memory material 370 deposited thereon. A small amount of electrical resistance to memory materials. "Heating area" 365 refers to a tiny area within dielectric sidewalls 36A that includes a programmable resistance memory material that can undergo phase switching. The current density in the heating zone 365 is maximized when the settings (SET) and reset (RESET) are programmed. The resistive memory materials 370, 340, 342, the dielectric sidewalls 360, 362, and the dielectric layer 350 both have low thermal conductivity. In one embodiment, the resistive memory materials 370, 34A, 342 have a lower thermal conductivity than the dielectric sidewalls 360, 362. The thermal conductivity of the dielectric fillers 360, 362 is equal to the dielectric layer 350. The heat generated from the heating zone 365 is not dissipated significantly because the heating zone 365 having the resistive memory material φ is surrounded by the resistive memory material, the dielectric sidewalls 360, and the dielectric layer 350. Therefore, the amount of heat lost from the heated area can be greatly reduced. In addition, the small-range resistive material in the heating region 365 also has low thermal conductivity properties, which can reduce heat loss from the resistive memory material 37, the electrical sidewalls 360, and the metal bit line 380, which helps to reduce the SET. Stylize current with RESET. The resistive memory material 370 can be selected from a variety of materials including, but not limited to, 'chalcogenide materials, giant magnetoresistive materials, two-element compounds, and polymeric materials. Resistive memory material 340, 342 is associated with a bottom electrode (i.e., contact plugs 326, 328). Resistor s ignoring material 34 〇 and contact plug 326 final 16 1305043 is a bottom electrode. The resistive memory material 370 is connected to the top electrode (also as a top electrode. A plurality of electrical-memory functions are used in the sense of j) without departing from the spirit of the invention. In the embodiment, the electrical memory material 340, 342 It is the same as the resistive memory material 37〇=-real: In the example, the 'resistive memory material 37〇 is selected from a chalcogenide ^ :+:: the resistive memory material 34〇, 342 is selected from a giant magnet, diterpenoid Compound, or a polymer material. # = (4) Includes materials based on phase-converted memory material and other materials. The furnace has one of four elements: oxygen (〇), sulfur (1), code. (C m forms part of the νι group on the periodic table. The chalcogenized chalcogen is combined with a more positive element or radical!! The chalcogen compound and other substances such as 3 weeks 3 Six columns of elements, such as the wrong (Ge) and tin (sn selected) from the i-chelate alloy, including more than one of the following elements, have been described in the technical documentation, including indium ί// , indium / recording, indium / code, recording / 碲, 锗 / 碲, 锗 / recorded / 碲, 锑 t gallium / code / 碲, tin / 锑 /碲, 锢 / recorded / wrong, silver / steel, / recorded / 碲, 锗 / recorded / Shixi / Lu, and 碲 / 锗 / recorded / sulphur. In 锗 / recorded 2 2 = in the middle can try the big Fan Park Alloy composition. This component can be squatted: Convergence table does not · TeaGebSb (10) VII. One researcher described the most useful human gold system as 'the average fragmentation degree contained in the deposited material is far lower than 70%, typical The soil system is less than 60%, and the cerium content in the general type alloy ranges from the lowest 23% to the highest 58%, and the optimum system is between ^./❶ to %%

Chinese soec.-Macr〇DixP940202 final 17 13〇5〇43 7 content. The concentration of cerium is above about 5% and its average range in the material ranges from a minimum of 8% to a maximum of 30% 'typically less than 50%. Optimally, the wrong 'farm range' is between 8% and 40%. The main component remaining in this ingredient is 锑. The above percentages are atomic percentages, which are 100% of all constituent elements. (〇vshinky ‘112 patent, columns 10-11) Special alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4, and

GeSb4Te7. (Noboru Yamada, "Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording55, • ν·37 (?9, pp. 28_37 (1997)) More generally, transition metals such as chromium ( Cr), iron (pe), nickel (Ni), niobium (Nb), palladium (pd), platinum (pt), and mixtures or alloys of the above may be combined with niobium/recording/ruthenium to form a phase-converting alloy. Included are programmable resistance properties. A special example of memory materials that can be used is described in columns 11-13 of the Ovshinsky '112 patent, examples of which are incorporated herein by reference. Phase change materials can be used in this cellular active channel region. The interior is switched between a first structural state in which the material is in a generally amorphous state and a second structural state in a generally crystalline solid state. The alloy is at least bistable. φ The term "amorphous" is used. By referring to a relatively inhomogeneous structure, one of the single crystals is more out of order, and has a detectable characteristic such as a higher resistance value than the crystalline state. The term "crystalline state" is used to refer to a relatively orderly structure that is more ordered than amorphous, so the package There are detectable features such as lower resistance values than amorphous. Typically, the phase change material can be electrically switched to all detectable different states between the fully crystalline state and the completely amorphous state. Materials affected by changes in crystalline and crystalline states include 'atomic order, free electron density, and activation energy. This material can be switched to a different solid state, or can be switched into a mixture of two or more solids. The gray-scale portion from the amorphous state to the crystalline state.

English snec -MacronixP〇4n2n2 final 18 1305043 The electrical properties of this material may also change. The j-mesh conversion alloy can be switched from the phase state to the state by applying an electric pulse

The observation shows that the shorter, larger amplitude pulse tendency ::: the phase of the conversion material changes to a substantially amorphous state. A longer, longer pulse tends to change the phase of the phase change material to a substantially knot: first. The energy in a shorter, larger amplitude pulse is large enough to break the bond, 钇, and bond, while being short enough to prevent the atoms from realigning into crystal =. In the absence of undue experimentation, it is possible to determine the appropriate pulse-quantity curve for a particularly suitable phase-shifting alloy. In the subsequent part of this article, this phase-converting material is referred to as GST, and we also need to understand that other types of phase-converting materials can be used. One of the materials described in this article for PCRAM is GexSbyTez, which has x:y:z = 2:2:5 °. Other GexSbyTez components include X: 〇~5; y: 〇~5; z : 0~10. Other programmable memory materials that can be used in other embodiments of the invention include doped N2iGST, GexSby, or others that are converted to different crystalline states.

Substance to determine the resistance; PrxCayMn03, PrxSryMn03, ZrOx, or other substance that uses an electrical pulse to change the resistance state; TCNQ(7,7,8,8-tetracyanoquinodimethane), PCBM (methanofullerene 6,6-phenyl C61-butyric Acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other substances, or any other polymeric material including bistable or controlled by an electrical pulse Steady-state resistance state; a giant magnetoresistance (CMR) material such as PrxCayMn03 where x:y = 0.5:0.5, or other components are x:0~1; y:〇~b or other giant magnetoresistance including manganese oxide Material; and a two-element compound such as NixOy, where x:y = 〇.5: 〇·5, or other components are X:0~1; y: 〇~1. Fig. 9 is a view showing a 1305043 bistable resistive memory of a second embodiment of the present invention which forms a via. A dielectric layer 350 is deposited over the surface of the surface dielectric 33G and over the programmable 340, 342. In one embodiment, the dielectric layer 35() comprises a fourth dielectric layer deposited by chemical vapor deposition (4) because of its low conductivity. The dielectric layer of the dielectric layer extends to the contact hole' whose critical dimension is fresher or smaller than the contact hole. As a result, the critical dimension of the tiny via 910 is much smaller than the contact plug 326. The patterning of the two-layer window 910 is located in the contact plug 326.

Above 340. In an embodiment, the threshold of the via window is

It is between about 10 nm and about 100 nm. The via window has an aspect ratio of from two to about two. 'J FIG. 10 is a diagram showing a process of resistive memory material and metal deposition in a next step of a method for fabricating a resistive memory according to a second embodiment of the present invention, and The patterning of a meta line. The second resistive memory material 370 is deposited into the vias 910, 912 and is located in the first dielectric fill section 35a, the second dielectric fill section 350b, and the third dielectric fill section 35〇c. on. The metal bit line 380 is located above the programmable resistive memory material 370. The metal wire can be used with a conductive material, including titanium nitride, nitride button, nitrogen = titanium / aluminum copper, nitride button / copper, and other types of similar conductive materials. Next, the patterning of the bit lines is performed, and the direction of the bit lines is perpendicular to the direction of the gate, the source, and the drain. The etching of the bit lines forms a straight line that includes a thin film stack formed by the upper resistive memory material 370 and the metal bit line 380. Figure 11 is a cross-sectional view showing the fabrication of a bistable resistive memory in a heated region of a resistive memory material according to a second embodiment of the present invention. 1100 ° each via 910 or 912 defines a relatively small The contact rhin«s« κηί*Γ -Μ«ΡτοηίγΡ04Γ)?η7 final 20 1305043 is compared to the resistive memory material 340 deposited on top of the contact plug 326, and the resistive memory material 370 deposited thereon. Next, a smaller amount of resistive memory material is deposited. The heated region 1110 occurs in a tiny region of the via 910 that includes the resistive memory material. The current density in the heating region 1110 is maximized when the setting (SET) and the reset (RESET) are programmed. The resistive memory materials 370, 340, 342, and the dielectric layer 350 each have low thermal conductivity. In one embodiment, the resistive memory material 370, 340, 342 has a lower thermal conductivity than the dielectric layer 35A. The heat generated from the heated region 1110 is not well dissipated because the heated region 1110 having the resistive memory material is surrounded by the resistive memory material and the dielectric layer 350. Therefore, the amount of heat lost from the heating zone can be greatly reduced. In addition, since a small range of resistive memory materials in the heating region 1110 also have low thermal conductivity properties, heat loss from the resistive memory material 370, the dielectric layer 350, and the metal bit line 380 can be reduced, and the set and RESET stylized currents are also Reduced. For additional manufacturing information, component materials, usage, and methods of operation for phase-converted random access memory devices, see U.S. Patent Application Serial No. 11/155, No. 67 'Thin Film Fuse Phase Change RAM and Manufacturing

Method, the application date is June 17, 2005, the applicant is the same as the case, and the case series is referred to in this case. Although the present invention has been described with reference to the preferred embodiments, what we will understand is ' The present invention is not limited by the detailed description thereof. The alternative and modified styles 6 are suggested in the previous description +, and other alternatives and modifications will be considered by those skilled in the art. In particular, According to the structural method of the present invention, all of the members having substantially the same composition as the present month, σ 5 and substantially the same result as the present invention do not depart from the spirit of the present invention. Therefore, the fourth (method) And modification

PhmMR - Μργγγ> τιΪυΡ04Π9. Π?. finnl 21 1305043 ^ is intended to fall within the scope of the invention of the invention of the patent red bread. Any text in the context of the special items mentioned in the scarf is a reference for this case. Ming case and printing [Simple description]

Recalling the first column. Figure (4) - this hair _ - a kind of bistable electric kiln machine access record box Figure 2. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified cross-sectional view of an integrated circuit of a first embodiment of the present invention, showing a cross-sectional view of a bistable resistive random access having a body Programmable resistive memory material for j-type structures. Figure 4 is a first step of a method for fabricating a bistable-resistive random access memory device which forms an interlayer dielectric in accordance with a first embodiment of the present invention. Figure 5 is a diagram showing a second step of a method for fabricating a bistable-resistive random access memory, including tungsten etching, forming a resistive memory material, and grinding, in accordance with a first embodiment of the present invention. Figure 6 is a diagram showing a third step of a method for fabricating a bistable-resistive random access memory to form a dielectric layer deposition followed by a dielectric sidewall etch according to a first embodiment of the present invention. Figure 7 is a fourth step of a method for fabricating a bistable resistive random access memory according to a first embodiment of the present invention, comprising depositing a first resistor δ remembrance material and metal, followed by patterning One yuan line. Figure 8 is a diagram showing a heating zone in the bistable resistance memory body in accordance with an embodiment of the present invention. Figure 9 is a diagram showing a method for fabricating a bistable 22 Γ .Macmni TP 940 ft 7 ' 1305043 - state resistive random access memory, including forming a via, in accordance with a second embodiment of the present invention. A second step of a method for fabricating a bistable resistive random access memory according to a second embodiment of the present invention includes performing deposition of a resistive memory material and a metal, and patterning a bit line. Figure 11 is a diagram showing the next step of a method for fabricating a bistable resistive random access memory, including forming a via, in accordance with a second embodiment of the present invention. [Main component symbol description] 100 memory array 123, 124 word line 128 common source line 132, 133 bottom electrode member 134, 137 top electrode member 135 memory cell 141, 142 bit line 145 γ decoder and word line driver 146 X decoder and sense amplifier 150, 151, 152, 153 access transistor 200 integrated circuit 260 memory array 261 column decoder 262 word line 263 row decoder 264 bit line 265 bus 266 sense amplifier and data input structure

Chinese spec.-MacronixP940202 final 23 1305043

267 data bus 268 bias supply voltage 269 bias arrangement state 271 poor input line 272 data output line 274 other circuit 275 integrated circuit 300 bistable resistance random access memory 310 semiconductor substrate 312, 314, 316 n-type terminal 320, 322 Crystal etch gate 326, 328 embolic structure 330 interlayer dielectric layer 330a, b, c dielectric fill 340, 342 programmable resistive memory material 350 dielectric fill layer 350a, b, c dielectric fill section 360, 362 dielectric sidewall 365 heating Area 370 Programmable Resistive Memory Material 380 Metal Bit Line 400 Transistor Structure 510, 512 Contact Hole 910, 912 Membrane 1110 Heating Area

Chinese «mec.-MacronixP940202 final 24

Claims (1)

1305043 X. Patent application scope i A memory element comprising: a beast electrode structure vertically separated from a bottom electrode, the bottom electrode package being electrically connected to a top surface resistive memory member having - and the top The electrode structure is electrically connected: the bottom electrode is electrically aligned with the side of the plug; and the side of the hidden member is coupled to the member, and the device includes a programmable resistive memory material, and the resistive material is disposed on the device The inner boundary of a side wall broadcasts f (4) the upper and lower programmable resistance memory member core members are electrically connected to the upper and lower programmable resistance memory structures; the second memory element, wherein the top battery unit The memory line is shared by the plurality of memory lines, wherein the upper memory and the top electrode structure function as a work. In the memory element described in claim 2, the wire system comprises a conductive material 1 /, a medium-μ copper, or a nitride/copper. Nitrided rattan, titanium nitride / Ming 5 · The memory element described in claim 1 of the patent, wherein the lower 25 English s〇ec.-MacronixP940202 final 1305043 stylized resistance memory member and the plug system The role is a second conductor. & The memory element as described in the patent application of the above-mentioned item includes a tungsten plug. The memory element of claim 1, wherein the plug comprises a polysilicon plug. The memory element of claim i, wherein the sidewall includes a dielectric sidewall. The memory device of claim 8, wherein the upper conductive layer, the chemical resistance (four) member, the lower programmable resistance memory member, and the k-heel member have lower thermal conductivity properties than the dielectric sidewall The thermal conductivity of the child. Baiyi is applying the memory element described in the first item of Patent No. 11, wherein the The lateral dimension of the two mainized resistive memory members is greater than the lateral dimension of the hybrid & W4 is the memory element according to item 1 of the patent application scope wherein the upper dimension is greater than the transverse dimension of the core member. The memory element of claim 1, wherein the upper β-stabilized memory member comprises the same programmable resistance material ΓΊ»«η^β^ on*»r-MarmniTpOdft^A^ final The memory element of claim 12, wherein the upper and lower programmable resistance memory components comprise GeSbTe. 14. The memory element of claim 12, wherein the upper and lower programmable resistance memory members comprise a combination of two or more of the following groups: bismuth, bismuth, bismuth, indium , titanium, gallium, germanium, tin, copper, palladium, lead, silver, sulfur, or gold. 15. The memory element of claim 12, wherein the upper and lower programmable resistive memory members comprise a giant magnetoresistive material. 16. The memory device of claim 12, wherein the upper and lower programmable resistive memory members comprise a two-element compound. 17. The memory element of claim 12, wherein the upper and lower programmable resistance memory members comprise a polymeric material. 18. The memory device of claim 1, wherein the upper programmable resistive memory member comprises a first type of programmable resistive memory material, and the lower programmable resistive memory material comprises a second Type programmable resistance memory material. 19. The memory device of claim 18, wherein the first type of material included in the upper programmable resistance memory member is GeSbTe, a giant magnetoresistive material, a two-element compound, or a polymer. The material, and the second row of materials included in the lower programmable resistance memory member is GeSbTe, a giant magnetoresistive material, a two-element compound, or a polymer material. Chinese st»ec.-Macr〇ttixP940202 final 27 1305043 wherein the two-solid phase 20. The memory element of the memory element according to claim 1 has at least two solid phases, and the system can borrow Reversible conversion by a current. 21. The memory element of claim i, wherein the stabilizing memory material comprises at least two solid phases, the two solids: comprising a substantially amorphous state and a substantially crystalline state. ^相匕 22. If you apply for a patent scope! The memory element described in the item, and the lower programmable resistance memory member, conduct heat generated by the core structure. Heating the 7-eyes to find the memory element described in item i, wherein the top wall structure of the phase wall and the bottom electrode are respectively formed by the minimum lithography of the lithography process for forming the element Feature ^. Sequence 乂 = Memory element as described in the patent application section ljf, the thickness of the wall is between 10 and 20 nm. /, the value of the memory = the thickness of the memory member described in the first paragraph of the patent range is about 80 legs or less. Wherein the core 26 is a memory element, comprising: a second electrode separating the second electric first electrode, the vertical electrode and the one pole including a plug; the upper programmable resistance memory member having the first Electrode connection 28 Ϊ305043 touch one contact surface; - lower programmable resistance memory member having a contact-contact surface, the lower programmable circuit; electrode electrically connected to the side of the plug; and hidden component The side is a pair of core components, comprising a programmable resistive memory material disposed in a dielectric sinter domain and disposed in the upper 」 」 加热 加热 加热 加热 加热 加热 加热 加热Between the members, the nucleus is electrically contacted to the upper and lower programmable resistance memory members. 27. A memory device, comprising: - a first electrode - comprising a plug perpendicular to a first pole; a knife-off, the first electrical hybrid programmable memory member having a first electrode One of the contact surfaces of the lightning contact; the element is electrically connected to the lower member, which has electrical connection with the second electrode; and the second side: the side of the stylized resistance memory member is a pair of core components - which includes - programmable The electrically resistive material is disposed in a via window to ==: between the stabilizing resistive memory members, the core member is electrically contacted to the upper and lower programmable resistive memory members. 28. A method for fabricating a memory device, comprising: providing a transistor body having a plug structure and an interlayer dielectric, the plug structure having a contact hole; and engraving a portion of the plug structure Depositing a layer of a programmable resistive memory material on top of the plug structure; rhinftCfi cn«· .MarrrtflirPOJn^n?fin»! 29 1305043 forms a sidewall on the layer of the programmable resistive memory material; A core member is formed by depositing a programmable resistive material in an opening formed by the sidewall, the core member electrically contacting the layer of the programmable resistive memory material and the layer of programmable resistive memory The material, the core member defines a heating region, and deposits a conductive material on the layer to program the resistive memory material. 29. The method of claim 28, wherein the etching step comprises selecting such that the selectivity of the interlayer dielectric is sufficiently high to prevent the interlayer dielectric from being damaged by the etching step. 30. The method of claim 28, wherein the embolic structure is filled with tungsten, and wherein the etching step comprises directly contacting the crane with an etch aspect ratio of about 1:1. The method of claim 28, wherein the etching step comprises etching the plug structure at a depth of about 200 nm in a contact hole of 0.2 μm. 32. The method of claim 28, wherein the etching step comprises an etch chemistry of sulfur hexafluoride (SF6). 33. The method of claim 28, further comprising, after the etching step, grinding an upper surface of the layer of the programmable resistive memory material, the upper surface protruding from the plug in the plug structure The upper surface of the hole. The method of claim 28, wherein before the step of forming the sidewall, the method further comprises: grinding an upper surface of the programmable resistive memory material under the layer. 35. The method of claim 28, wherein the sidewall sub-forming step comprises: depositing a dielectric layer over the layer to pattern the resistive memory material; etching the dielectric layer to create a hole The width of the hole is equal to or smaller than the width of the contact hole in the plug structure; a sidewall material is deposited in the hole to form the sidewall, the thickness of the sidewall is less than one half of the size of the contact hole Anisotropic etching is performed by dry etching of a fluorine-based compound to form the sidewall. 36. The method of claim 28, wherein the electrically conductive material comprises titanium nitride, tantalum nitride, titanium nitride/1 Lu copper, or tantalum nitride/copper. 37. The method of claim 28, wherein the electrically conductive material acts as a one-dimensional line. 38. The method of claim 37, wherein the direction of the bit line is perpendicular to a gate, a source, and a drain of the transistor body. P!hin«ft ςη« ·. -Μαπ*λ«ϊυΡΡ407Π?. final 31