TWI328873B - Thin film fuse phase change cell with thermal isolation layer and manufacturing method - Google Patents

Description

1328873 IX. Invention Description: [Related application materials] This case is related to the US continuation application filed on June 17, 2005. The application number of the application is 11/155,067, and the invention name is 'THIN. FILM FUSE PHASE CHANGE RAM AND MANUFACTURING METHOD" [Partners of Joint Research Contracts] International Business Machines Corporation New York Company, Wanghong International Co., Ltd. Taiwan Company and Infineon Technologies AG (Germany) are joint research contracts [Technical Field] The present invention relates to high-density memory elements using phase change memory materials, including chalcogenide-based materials and other materials, and methods for fabricating such elements [Prior Art] Memory materials based on phase 5 are widely used in reading and writing optical discs. These materials include at least two solid phases, including a solid phase such as a mostly amorphous state, and - The solid phase is generally crystalline. The laser pulse is used to read and write the wire + in two phases. Switching and reading the optical properties of the material after phase change. Such phase change memory materials such as chalcogenide and similar materials can be applied to the current in the integrated circuit by means of 5 1328873 and 2 amplitudes. Crystal phase transition σ° Generally, the amorphous state is characterized by its higher electrical resistance than the crystalline state. This resistance is easily measured and used as an indication. This property causes the use of a programmable resistive material to form a non-volatile memory. Circuit This circuit can be used for random access reading and writing. 曰α transition from amorphous to crystalline is generally a low current step. From crystalline to amorphous (hereinafter referred to as reset) A high current step comprising a brief high current density pulse to melt or destroy the crystalline structure, after which the phase change material rapidly cools, inhibiting the phase change process, so that at least a portion of the phase change structure is maintained amorphous In the ideal state, the reset voltage that causes the phase change material to change from a crystalline state to an amorphous state should be as low as possible. To reduce the magnitude of the reset current required for resetting, This is achieved by reducing the size of the phase change material element in the memory and reducing the contact area of the electrode with the phase change material, so that a lower absolute current value can be applied to the phase change material element to achieve a higher current density. One method developed in this field is to create tiny holes in an integrated circuit structure and fill these tiny holes with a trace of programmable resistance material. The patents dedicated to such tiny holes include: November 1997 U.S. Patent No. 5,687,112, "Multibit Single Cell Memory Element Having Tapered Contact", inventor Ovshinky; U.S. Patent No. 5,789,277, entitled "Method of Making Chalogenide [sic] Memory Device", published on August 4, 1998, The inventor is Zahorik et al.; US Patent No. 6,150,253, "Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same", published on November 21, 2000, the inventor is Doan et al. 6 1328873 Size 呓 f f 以 以 以 以 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些The H if is around the material m of the active region, and the cell-related problem occurs due to the failure of the main static number. In order to cause the phase change, however, the enthalpy generated by the current passing through the phase change material will be ΪΪΓ Conduction away. This will heat the phase change in the active region; the heating effect of k decreasing the current will also interfere with this phase change.

The operation of materials. It is therefore desirable to provide a memory cell structure including t-size and only divergence current' and a method for fabricating such structures that meet the stringent process variables of a large size memory device. More preferably, a manufacturing process and structure is provided that is compatible for use in fabricating peripheral circuits on the same integrated circuit. SUMMARY OF THE INVENTION The present invention describes a phase change random access memory (PCRAM) device that is suitable for use in a large size integrated circuit. The technique described herein includes a memory element including a first electrode having a top side, a second electrode having a side, and an insulating member located between the first V electrode and the second electrode There is a thickness between the first and second electrodes, near the top side of the first electrode and the top side of the second electrode. a thin film via bridge spans the insulating member and defines an inter-electrode path between the first and second electrodes, across the insulating member, the thin film viaduct includes an active layer of phase change material, and one provides A layer of thermal insulation blanket material between the active layer and its underlying structure. The blanket material providing thermal insulation may comprise the same material as the phase change material of the active layer. The thermal insulation blanket material may comprise 7 1 / 8873 second = composite structure having a - first isolation layer, and 1 wherein the isolation layer is an isolation active layer and a thermal insulation layer, and / or The barrier layer prevents the substance from migrating between the active layer and the thermal insulation layer: the inter-electrode path of the second expansion member has a length of _ path defined by the width of the bridge. For ease of explanation, this guide bridge can be regarded as the structure of the sense component. However, for phase change memory, it is not similar to ', the dangerous wire includes a chalcogenide material having at least two solid phases, and the two solid phases can be applied by applying a current therebetween or A material is applied between the first and second electrodes to reversibly induce. An electrically insulating material is attached to the blanket of thermal insulation material, wherein the thermal insulation blanket I has a lower thermal conductivity than the electrically insulating material layer. 'The volume of a memory material subject to phase change can be very small, the thickness of the insulating member (path length of the X-axis), the thickness (y-axis) used to form the viaduct, and the length of the guide bridge perpendicular to the path length. The width (defined by z.) In the embodiment, the width of the insulating member, and the thickness of the film memory material to be bridged, are defined by the thickness of the film and are limited by the two-pattern process for forming the memory cell. The & sound of the bridge is less than a minimum feature size F, which is unique to the lithography process used to pattern the material layers of the embodiment. In one example, the width of the bridge is Defined by the photoresist arm technology, wherein the second mask pattern is used to define a lithography photoresist structure on the wafer, which has a small f-feature size F, and the photoresist structure utilizes an isotropic property.彳^二Ϊ =. The trimmed photoresist structure and then the transfer of the lower germanium pattern to the insulating material layer on the read material may use other techniques to form the (four) material in the integrated layer of the integrated circuit. Phase change memory can be reset ^ Flow and low energy consumption, and easy to manufacture. Μ tiny 8 1328873 In an embodiment of the technology of the present invention, a memory cell array is provided. In this array, a plurality of electrode members and between the electrode members are located The insulating member is formed on an integrated circuit to form an electrode layer. The electrode layer has an upper surface which is a substantially flat surface in some embodiments of the invention. Between the pair of electrode members, across a plurality of film guides of the insulating member having a thermal insulating blanket. A current path from the first electrode of the electrode layer, the film via bridge passing through the upper surface of the electrode layer, and reaching the second electrode of the electrode layer Formed in each memory cell in the array. In the present invention, the circuit under the electrode layer in the integrated circuit is formed by a technique conventionally used to form a logic circuit and a memory array circuit. For example, a complementary metal oxide semiconductor (CMOS) technology. Further, in one of the array embodiments described herein, circuitry over the electrode layer and a via array with a thermally insulating blanket The column includes a plurality of bit lines. In the embodiment in which one of the bit lines described above is above the electrode layer, the electrode members located in the electrode layer are shared as a first electrode of a memory cell, which may result in a A single electrode member provides a first electrode as two memory cells in a row of the array. Further, in the embodiments described herein, the bit lines in the plurality of bit lines can be arranged to correspond along an array And a pair of adjacent memory cells in a corresponding row share a contact structure to contact the first electrode. The present invention also describes a method of fabricating a memory device. The method includes forming an electrode layer in a completed front-end process Forming a circuit on the substrate. The electrode layer has an upper surface, the electrode layer includes a first electrode and a second electrode, and an insulating member is formed between the first electrode and the second electrode for each Phase change memory cells. The first electrode, the second electrode and the insulating member extend on an upper surface of the electrode layer, and the insulating member has a wide-width between the first electrode of the second electrode and the second electrode of the second electrode, and the memory cell structure connection. The method includes a shape t-plane for each phase-to-form phase change memory cell, jrr: the bridge includes a memory material film = a path between the first electrode and the inter-electrode across the insulating member - The width of the insulating member is the same as that of the household. In an embodiment of the method, the structure is formed on the electrode layer by the formation of a patterned conductive layer for the conduction of the bridge. And the formation of a contact with the first electrode and the patterning of the patent for other purposes, the money will be fully understood through the application of the ship to the guide and the drawings. [Embodiment] The thin film fuse phase change memory cells, the memory cells ® / n, and the method for manufacturing the memory cells are described in detail in the drawings 1 to 16. Figure 1 is a diagram showing the basic structure of a memory cell 1G', comprising a memory material via U on the electrode layer, comprising a first electrode 12, a first electrode 13, and a first electrode 12 and The insulating member 14 between the two electrodes 13. As shown, the first and second electrodes 1213 have upper surfaces 12a and 13a. Similarly, it also has an upper surface 14a. In this embodiment, the upper surface 丨 2a, i3a, 14a of the 6-well structure in the electrode layer defines a substantially flat upper surface of the electrode layer. In other embodiments, the upper surfaces 12a, 13a, 14a are not in the same plane, for example, the insulating member 14 may be extended 1328873 to form an insulating wall between the electrodes. The memory material vial 11 includes an active layer 15 of memory material over the flat upper surface of the electrode layer such that contact between the first electrode and the via 11 and between the second electrode 13 and the via 11 This is achieved by the underside of the active layer 15 of the vial 11. The guide bridge 11 includes a thermally insulating blanket covering the active layer 15 of the memory material with a thermal insulating material comprising barrier layers 16 and 17 to limit the heat generated by the active layer 15 to the memory cells. Within an active area. This barrier layer 16 comprises a material such as hafnium oxide or tantalum nitride which provides electrical insulation between the active layer 15 and layer 17. The barrier layer 16 can also serve as a diffusion barrier layer between the thermal insulating material layer 17 and the memory cell active layer 15. In the embodiment shown, the blanket covers only the top of the active layer 15. In other embodiments, the blanket may also cover the side of the active layer 15. Further, the barrier layer 16 and the layer of thermal insulating material 17 may also comprise respective multilayer composite structures. Embodiments of the access circuit can contact the first electrode 12 and the second electrode 13 in a variety of configurations to control the operation of the memory cells such that they can be programmed to set the active layer 15 of the via 11 to the two solid phase In one of these, the two solid phases can be reversibly implemented using a memory material. For example, using a chalcogenide-containing phase change memory material, the memory cell can be set to a relatively high resistance state, wherein at least a portion of the bridge in the current path is amorphous. Most of the vias in the current path are in a relatively low resistance crystalline state. The active region in the active layer 15 is a region of a phase change memory cell in which the material is induced to switch in at least two solid phases. In the illustrated embodiment, the active area in the active layer 15 is generally above the insulating member 14. It will be appreciated that this active region can be made very small, reducing the magnitude of the current required to induce a phase change. 11 1328873 The length L (χ axis) of this active region is defined by the thickness of the insulating member 14 (referred to as channel dielectric in the drawing) between the first electrode 12 and the second electrode 13. This length L can be controlled by controlling the width of the insulating wall 14 in the memory cell embodiment. (In the representative embodiment, we have not defined the length of the insulating wall 14 using a film.) Similarly, the thickness T (y-axis) of the bridge in the memory cell embodiment can be very small. The bridge thickness T can be formed on the upper surfaces of the first electrode 12, the insulating wall 14, and the second electrode 13 by using a thin film deposition technique. Thus, in the memory cell embodiment, the via T thickness is below 50 nm. In other embodiments of memory cells, the thickness of the viaduct is 20 nm or less. In other embodiments, the via thickness T is 10 nm or less. It can be understood that the thickness T of the bridge can be even less than 10 nm, such as atomic layer deposition technology, depending on the needs of the particular application, as long as the thickness allows the bridge to perform its memory element, that is, at least The two solid phases are reversibly induced by a current or a voltage applied between the first and second electrodes. The width of the guide bridge W (z axis) is also very small. In the preferred embodiment, the bridge width W is less than 100 nm. In some embodiments, the bridge width is below 40 nm. Embodiments of memory cells include a guide bridge 11 constructed of a phase change based memory material, which may include: chalcogenide-based materials and other materials. The chalcogenide includes any of the following four elements: oxygen (〇), sulfur (S), selenium (Se), and tellurium (Te), forming part of the group VI of the periodic table. Chalcogenides include the combination of a chalcogen element with a more positive element or radical. The chalcogen compound alloy includes a combination of a chalcogen compound with other substances such as a transition metal or the like. The monochalcogenide alloy typically includes more than one element selected from the sixth block of the periodic table, such as germanium (Ge) and tin (Sn). Generally, the chalcogenide alloy includes one or more of the following 12 compounds and silver (Ag). Many u, ), gallium (Ga), indium (In), which are described in the technical documents, including the basic memory materials have been described I: 锗锗I: (9) components. This component can be represented by the following characteristic formula: One of the alloys of the surrounding alloy describes the most useful alloy system. 1 = b) contains the sulphur, the total enthalpy of the enthalpy, and is 'in the deposited material. The spread is 70%, typically less than 60%, and the bismuth content in the general type alloy ranges from a minimum of 23 58%, and the best system is between 48% and the guanidine content. The concentration of ruthenium is about 5%' and its average range in the material ranges from a minimum of 8% to a maximum of 30/. , generally less than 5%. Optimally, the concentration range of lanthanum is between 8% and 40%. The main component remaining in this ingredient is hydrazine. The above percentage is an atomic percentage which is a total of 1% by weight of all constituent elements. (Ovshinky '112 patent, column 1 〇 ~ η) Special alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7. (Noboru Yamada,’’Potential of Ge-Sb-Te Phase-change

Optical Disks for High-Data-Rate Recording 55, SPIE v. 3109^ PP. 28-37 (1997)) More generally, transition metals such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb) Palladium (Pd), platinum (Pt), and mixtures or alloys thereof, may be combined with ruthenium / osmium / iridium to form a phase change alloy which includes programmable resistance properties. A special example of a memory material that can be used is described in columns 11-13 of the Ovshinsky '112 patent, examples of which are incorporated herein by reference. The phase change alloy can be switched between the first structural state in which the material is in a generally amorphous state and the second structural state in a state of a general crystalline solid 13 1328873 in the active channel region of the cell. These alloys are at least bistable. The term "amorphous" is used to refer to a relatively unordered structure that is more unordered than one of the single crystals, with detectable features such as higher resistance values than the crystalline state. The term "crystalline" is used to refer to a relatively ordered structure that is more ordered than amorphous and therefore includes detectable features such as lower resistance than amorphous. Typically, the phase change material can be electrically switched to all detectable different states between the fully crystalline state and the fully amorphous state. Other materials that are affected by changes in amorphous and crystalline states include atomic order, free electron density, and activation energy. The material can be switched to a different solid state, or can be switched to a mixture of two or more solid states, providing a gray-scale portion from amorphous to crystalline. The electrical properties of this material may also change. The phase change alloy can be switched from one phase to another by applying an electrical pulse. Previous observations indicate that a shorter, larger amplitude pulse tends to change the phase of the phase change material to a substantially amorphous state. A longer, lower amplitude pulse tends to change the phase of the phase change material to a substantially crystalline state. The energy in the shorter, larger amplitude pulses is large enough to break the bond of the crystalline structure while being short enough to prevent the atoms from re-arranging into a crystalline state. In the absence of undue experimentation, an appropriate pulse viewing curve that is particularly suitable for a particular phase change alloy can be determined. In the subsequent part of this article, this phase change material is referred to as GST, and we also need to understand that other types of phase change materials can be used. One of the materials described in this document for use in PCRAM is Ge2Sb2Te5. Other programmable memory materials that can be used in other embodiments of the invention include GST doped with N2, GexSby, or other materials that are converted by different crystalline states to determine electrical resistance; PrxCayMn03, PrSrMnO, ZrOx, TiOx, NiOx, W0X Doped SrTi03 or other material that utilizes electrical pulses to alter the electrical state of the body; or other material that uses an electrical pulse to change the state of resistance

TCNQ(7,7,8,8-tetracyanoquinodimethane), PCBM (methanofullerene 6,6-phenyl C61-butyric acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, other substances The doped TCNQ, or any other polymeric material, includes a bistable or multi-stable resistance state controlled by an electrical pulse. The material of the layer of thermal insulating material 17 may be the same as the memory material, such as GST in an embodiment of the cell. In other embodiments, φ the thermal insulating material Π comprises polyvinylamine or other material having a lower thermal conductivity than the dielectric layer on the viaduct. A representative material of the layer of thermal insulation material, including the following elements: the stone, carbon, oxygen, fluorine, and hydrogen. A thermal insulating material suitable for use as a thermal insulating cap layer, including cerium oxide, cerium hydroxide, polytheneamine, polyamine, and fluorocarbon polymer. Other materials suitable for use as thermal insulation coatings, including fluorinated cerium oxide, silsesquioxane, p〇iyaryiene ether, parylene, fluoropolymer , fluorinated amorphous carbon, diamond-like carbon, porous oxidized second, mesoporous (mes〇p〇r〇us) oxidized oxide eve, poly #porous sesquioxide, porous polyimide and porosity Halogen ether. Single or multi-layer structures provide thermal and electrical insulation. Figure 2 depicts the structure of the PCRAM cell V. These cell lines are formed on a semiconductor substrate 21. For example, an insulating structure such as a shallow trench insulating dielectric (STI) (not shown) isolates pairs of memory cell access transistor columns. The access transistor system is in a p-type substrate 21, with an n-type terminal 26 acting as a common source region, and an n-type terminal 25, 27 acting as a terminal. The polysilicon word lines 23, 24 are used as gates for accessing the transistors. A dielectric fill layer (not shown) is formed over the polysilicon character line. This layer is a patterned conductive structure comprising a common source line 28 and a plug structure 15 1328873 29, 30 being formed. These conductive materials may be tungsten or other materials and combinations suitable for use as plugs and wire structures. The common source line 28 contacts the source region 26 and acts as a common source line along a column in the array. The plug structures 29, 30 are in contact with the drain terminals 25, 26, respectively. The fill layer (not shown), the common source line 28, and the plug structures 29, 30 each have a substantially flat upper surface or are suitable for use as a substrate for forming an electrode layer 31. This electrode layer 31 includes electrode members 32, 33, 34 which are separated from each other by insulating members such as insulated gates 35a, 35b, and a base member 39, wherein the insulated gate is formed by a side wall process as described below form. In the structure of this embodiment, the base member can be thicker than the insulated gates 35a, 35b and isolate the electrode member 33 from the common source line 28. For example, the thickness of the base member may be between 80 and 140 nm, and the insulated grid is much narrower because the capacitive coupling between the source line 28 and the electrode member 33 must be reduced. In the present embodiment, the insulating gates 35a, 35b include a thin film dielectric material on the sidewalls of the electrode members 32, 34, and the thickness of the surface of the electrode layer 31 is determined by the thickness of the film on the side walls. A composite memory guide 36a (e.g., GST) is placed over a blanket and includes a barrier layer 36a and a layer of thermally insulating material 36c on one side of the electrode layer 31 across the insulating sidewall 35a. A first memory cell is formed, and a thin film memory material guide 37 (for example, GST) is placed on a blanket, and includes a barrier layer 37a and a thermal insulating material layer 37c, which are located above the electrode layer 31. On the other side, a second memory cell is formed across the insulated gate 35b. A dielectric fill layer (not shown) is placed over the film viaduct. The dielectric fill layer includes hafnium oxide, polymethyleneamine, tantalum nitride, or other dielectric fill material. The thermal insulation layer blanket 37c has a lower thermal conductivity than the filled dielectric layer 16 1328873. The tungsten plug 38 contacts the electrode member 33. A patterned conductive layer 40 comprising a metal or other conductive material, including bit lines in the array structure, overlying the dielectric fill layer and contacting the plug 38 to establish for the left side corresponding to the film bridge Access to memory cells of active layer 36a and active layer 37a to the right of the film bridge. Fig. 3 is a view showing the structure on the semiconductor substrate 21 in Fig. 2, which is presented in a layout manner. Thus, the arrangement of word lines 23, 24 is substantially parallel to the common source line 28, along a common source line in a memory cell array. The plugs 29, 30 are in contact with the terminals of the access transistors in the semiconductor substrate and the bottom sides of the electrode members 32, 34, respectively. The thin film memory material guides 36, 37 are located above the electrode members 32, 33/34, and the insulated gates 35a, 35b separate the electrode members. The plug 38 is in contact with the electrode member 33 located between the bridges 35 and 37, and the bottom side of the metal bit line 41 (transparent in Fig. 3) below the patterned conductive layer 40. Metal bit line 42 (non-transparent) is also shown in Figure 3 to emphasize the array layout of this structure. In operation, access to memory cells corresponding to the via 36 is achieved by applying a control signal to the word line 23, which is the common source line 28 via the terminal 25, the plug 29, and The electrode member 32 is coupled to the film guide 36. The electrode member 33 is coupled by a contact plug 38 to a bit line in the patterned conductive layer. Similarly, access to memory cells corresponding to the via 37 is achieved by applying a control signal to the word line 24. It will be appreciated that a variety of different materials can be used in the structures of Figures 2 and 3. For example, copper metallization can be used. Other types of metallization such as aluminum, titanium nitride, and tungsten-containing materials can also be used. At the same time, non-metallic conductive materials such as doped polysilicon can also be used. The electrode material used in the embodiment of the invention is preferably titanium nitride or aluminum nitride. Alternatively, the electrode may be aluminum titanium nitride or aluminum nitride, or may include more than one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (A1), Sister (Ta), copper (Cu), 铭 (pt), 铱 (8) 镧 (La), nickel (four), and nail (Ru) and an alloy composed of the above elements. The inter-electrode insulated gates 35a, 35b may be di-oxidized; a thin dielectric, a oxidized oxide, a nitride, an oxide, or another dielectric having a low dielectric constant. Alternatively, the interelectrode insulating layer may include one or more elements selected from the group consisting of ruthenium, titanium, aluminum, ruthenium, nitrogen, oxygen,

Figure 4 is a schematic diagram of a green-memory array, which can be implemented by referring to Figure 2 of Figure 2. Therefore, 'the label in the figure is the standard label. It can be understood that the array shown in Figure 4 = 8 other words = \ real, f in the description of Figure 4, in the upper parallel square 45 γ decoding; to t thousand on the X axis. Therefore 'in

Line 23 24. In the square sub-wire driver, the X decoder coupled to the character block in block 46 is coupled to the bit line 41, 42 = and the group sense amplifier, the crystal 50, 51, 52 53 The pole line is coupled to the access wire to the word line Β. The access between the transistor access transistor 50 and the gate transistor 52 is connected to the word line 24. The gate is lightly connected to the word line 24. Save 23. The transistor 53 is accessed to the electrode member 32 to connect the non-wire connector 34 of the via 36 曰 body 50. Similarly, the access port is connected to the electrode member 33 to connect the bridge 37, and the bridge 1 is coupled to the electrode electrode member 34 and coupled to the bit line 4: Connected to the electrode member 34. The piece 34 is located at a different position from the bit line 41: = convenient solution, the electrode structure understands that in its embodiment 18 1328873, different memory cell guides can be used with different access transistors 52 and 53 The line 42 is coupled to the temple +. cell. As can be seen, the common source line 28 is produced by two columns: a few of which are recalled, with the columns arranged along the gamma axis. Similarly, the two systems are shared by two memory cells in a row in the array and are arranged along the X axis. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 5 is a block diagram of an integrated circuit according to the present invention. The integrated circuit Μ includes a memory array 6() which is formed on the 'semiconductor substrate by using a thin-risk phase change § cells, and the device 61 is coupled to the plurality of word lines 62 and along Record. - Columns are arranged in columns. A row of decoders 63 are coupled to the plurality of bits of the bit line _ A along the rows in the memory array 00 - 64, the multi-gate memory cells in the array 60 are read and programmed and used Supply from the bus bar to the row decoder 63 and the column decoder]. The sense amplifiers and data input structures in which the addresses are located are via sinks. The two blocks 66 to the line decode H 63. The address is extracted from the bus bar 65 and the column decoder 61. /· 十地" 丄芏 解码 解码 63 63 以 以 以 以 以 以 data data data data data data data data data data data data data data 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感Provide the source of the department or the internal data, and input the structure of the integrated circuit through the data round-trip. In the described embodiment, the purpose is to have its t-circuit 74, such as a general purpose processing 11 or a specific Γ / , or an integrated module of a single-chip (SyStem0naChiP) function supported by a thin film fuse phase change memory cell array. The sense amplifier in block 1, block 66, passes through data output line 72, and the value = to the input/output port of integrated circuit 75, or to other sources of information for the product or external. In the present embodiment, a controller of the state machine 69 is used to control the application of the bias voltage to supply the voltage 68, such as reading, programming, erasing, erasing confirmation, and stylizing confirmation voltage. This controller can use a conventional purpose specific logic circuit. In an alternate embodiment, the controller includes a general purpose processor that can be applied to the same integrated circuit that executes a computer program to control the operation of the component. In yet another embodiment, the controller uses a combination of a specific purpose logic circuit and a general purpose purpose processor.

Figures 6-16 show the fabrication of a structure and a dual array of electrode structures. In a double damascene structure, a dielectric layer is formed in a two-level (i.e., two-layer) pattern, wherein the first level pattern defines the trenches of the wires, and the second level pattern is connected to the via holes of the underlying structure. A single metal deposition step can be used to simultaneously form the wires and fill the via holes connecting the underlying structures to form conductive traces. The vias and trenches can be defined using a two-stage lithography step: the trench is typically (d) to - the depth, and the via is from the ground to a second depth to form a via opening that connects the underlying structure. After the via holes and trenches are etched, a deposition step can be used to simultaneously fill the vias and trenches with metal or other conductive material. After filling, the excess material deposited in the trenches utilizes a chemical mechanical polishing process. The double-inserted structure, which is filled with a conductive material on one side, is completed. No. 6, showing: a process diagram of a double-inserted structure, an electrically insulating material layer is suspended from a dielectric layer, formed on the front-end process structure, and the double-embedded structure after Sun is formed therein. The process of forming a quasi-CMOS device, in the illustrated embodiment, corresponds to the == matrix. The word line in the column, the source line, and the access transistor line 106 cover the doped region in the semiconductor substrate. The doped region 103 corresponds to the source terminal of the second access transistor on the first access side 20 1328873 f2 and the Ltf side on the left side of the figure. In this embodiment, the source line does not extend completely to the surface. One yt-doped t-domain two the first access transistor's drain. The sub-twist line containing a polycrystalline 矽1〇7 is shown in the figure as the first access transistor. 109俜Imitated in the 1iV7 of the 屮炙曰 — — 繊 繊 繊 繊 繊 繊 ( 一 一 一Embolization 110

Thus, the doped region is just the same, and a conductive path is provided to the structure 99: the second surface is connected to a memory cell electrode in a manner to be described later. The doped region 105 is used as a drain terminal for the access transistor. A sub-line system including a polysilicon line m is used as the gate of the second access transistor. A plug 1 1 2 contacts the doped region 105 and provides a conductive path to the upper surface of the structure 99 to be connected to a memory cell electrode in a manner to be described later. An electrically insulating material layer 651 is formed over the front stage process structure as shown. The double damascene process includes a first patterned photoresist layer 652 overlying layer 651, as shown in FIG. This first patterned photoresist layer 652 defines regions 651, 654, and 655 in layer 651 that are etched into trenches that correspond to the electrode features in the dual damascene electrode structure. Using the patterned photoresist layer 652 as a mask, layer 651 is etched to a first depth that does not completely penetrate layer 651 to form shallower trench regions 656, 657, and 658' as shown in Figure 8: Show. Thereafter, a second patterned photoresist layer 659 is formed over layer 651 as shown in FIG. This second patterned photoresist layer 659 defines the electrode members of the regions 660, 661 that are in contact with the plugs 11A, 112. Using the patterned photoresist layer 659 as a mask, the layer 651 is etched to fully penetrate to a second depth 'in contact with the plugs 11A, 112 to form a deeper trench region 662 in the trench regions 656, 657 and 658, 663, as shown in Figure 1. The dual-ditch layer 651 of the elementary layer is then filled with a metal such as copper or copper 21.328873 gold, having suitable adhesion and barrier layers well known to those skilled in the art to form layer 664, as shown in FIG. . As shown in the figure, chemical mechanical polishing or other similar technique is used to remove a portion of the metal layer 664 up to the dielectric layer 651 to form an electrode layer having dual embedded electrodes 665, 666, and 667 structures. The electrodes 665 and 6667 are in contact with the plugs 11A, 112, and the electrode structure 666 is isolated from the source line 1A6. In a F step, as shown in FIG. 13, a layer of memory material 668a, a barrier layer 668b, and a thermal insulating layer 668c are formed over the embedded dielectric layer 651, referred to herein as the electrode of the element. Floor. A patterned photoresist layer, including masks 670 and 671, as shown in Figure 14, is then formed over layer 668c. This mask 670 and 671 first out the location of the memory material bridge in this memory cell. Thereafter, an etching step is performed to remove portions of layers 669 and 668 that are not covered by masks 670 and 671, retaining a previously described multi-layer structure comprising a memory material active layer, a barrier layer, and a thermal insulating layer. The five built-up bridges 672 and 673. The active layer of the bridge 672 extends from the electrode structure 665 to the electrode structure 666 through an insulating member 674. Thus, the width of the member 674 is such that the length of the inter-electrode path of the memory material bridge 672 is increased. The active layer of the bridge 673 extends from the electrode structure 667 through an insulating member 675 toward the electrode structure 666. The width of this insulating member 675 is such that the electrode of the memory material bridge 673 is expanded: the length of the path. ^ As shown in Fig. 16, after the memory bridges 672 and 673 are defined, a dielectric fill layer (not shown) is formed and planarized. Then, the via is etched into the dielectric fill layer of the electrode member 666. These vias are filled with a plug such as tungsten to form a conductive plug 676. A metal layer is then patterned to define a bit line 677 that is in contact with the plug and arranged along the rows of memory cell pairs as shown in Figure 16. This dielectric filled material may not have a barrier layer with good thermal insulation. Thus, 22 1.328873. The thermal insulation materials used in memory bridges 672 and 673 have lower thermal conductivity than the dielectric filler material underneath. Fig. 2 shows the final structure produced by the process of the double-embedded electrode structure. The dielectric material removed from the electrode layer 651 of Fig. 16. Other content relating to the manufacture and material of a phase change random access memory device is disclosed in another U.S. Patent Application Serial No.

11/155,067 "THIN FILM FUSE PHASE CHANGE RAM AND MANUFACTURING METHOD", the application number is 2005

June 17 (Attorney Docket No. MXIC1621-1), the application series is a reference for this case' and this technique can be easily extended to the composite bridge structure described herein to form a very narrow active layer in this bridge. Most of the phase change memory cell species known to the applicant are formed by forming a micropore and filling in phase change memory cells, followed by formation of a top and bottom electrode contacting the phase change material. This tiny hole structure is used to reduce the stylized current. The present invention reduces the stylized current without the need to form tiny holes, thereby achieving better process control. In addition, there is no top electrode on the cell to avoid potential damage to the phase change material used to form the top electrode. Episodes The cells described herein include a bottom electrode and a dielectric therebetween, as well as a phase change material bridge over the electrode that spans the dielectric. The bottom electrode and the dielectric system are formed in the electrode layer above the CMQS logic function circuit structure of the front-end process, and the structure of the two-core, body and Wei circuit on the single wafer can be easily provided. System on chip (SOC) component. The advantages of the embodiments of the present invention include phase change phenomena occurring at the center of the vias on the electrically filled layer, rather than at the junctions of the vias and the electrodes, thus providing better reliability. At the same time, the current used in the reset and = 23 1328873 operation is limited to a small volume, allowing high current density and the local heating effect it produces, while requiring less reset current and lower Reset power consumption. Although the present invention has been described with reference to the preferred embodiments, it is understood that the invention is not limited by the detailed description. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, the structures and methods of the present invention, all of which are substantially identical to the components of the present invention and which achieve substantially the same results as the present invention, do not depart from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents. Any patent application and printed text mentioned in the foregoing are a reference for this case. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an embodiment of a phase change memory element film guide. Figure 2 is a perspective view showing a set of phase change memory elements having an access circuit under an electrode layer and a bit line above the electrode layer. Figure 3 is a plan view showing the structure of Figure 2: Figure 4 is a diagram showing a memory array containing phase change memory elements. Figure 5 is a block diagram of an integrated circuit component including a thin film fuse phase change memory array and other circuits. Figure 6 is a first step cross-sectional view of a double damascene process for forming a memory element electrode layer. Figure 7 is a second step cross-sectional view of a double damascene process for forming a memory element electrode layer. 24 1328873 Figure 8 is a cross-sectional view of a third step of a dual damascene process for forming a memory element electrode layer. Figure 9 is a cross-sectional view showing a fourth step of a double damascene process for forming a memory element electrode layer. Fig. 10 is a fifth step sectional view showing a double damascene process for forming a memory element electrode layer.

Figure 11 is a sixth step cross-sectional view of a double damascene process for forming a memory element electrode layer. Figure 12 is a seventh step sectional view of a double damascene process for forming a memory element electrode layer. A dual damascene process diagram for forming a memory element electrode layer. Figure 13 is an eighth step section. Figure 14 is a ninth step section. The figure is a tenth step sectional view. The double-insertion process of the memory element layer is formed to form a memory element. Electrode layer map. Figure 16 is a double-inserted process memory cell memory material guide bridge for forming an eleventh step sectional view of a memory element electrode layer. The first electrode upper surface of the second electrode insulating member active layer [main components Explanation of symbols] 10 11 12 12a, 13a, 14a 13 14 15 25 1328873

16 barrier layer 17 thermal insulating material layer 21 semiconductor substrate 23, 24 word line 25, 27 n-type terminal drain 26, 28 common source line 29, 30 plug structure 31 electrode layer 32, 33, 34 electrode member 35a 35b insulated gate 36a, 37a memory material 36b > 37b barrier layer 36c, 37c thermal insulating material layer 38 tungsten plug 40 conductive layer 41, 42 bit line 45 Υ decoder and word line driver 46 X decoder and one Group sense amplifiers 50 to 53 access transistor 60 memory array Ί 61 column decoder 62 word line 63 line decoder 64 bit line 65, 67 bus 68 supply voltage 69 bias arrangement state machine 26 1328873 71 72 74 75 99 103~105 poor input line data output line other circuit integrated circuit structure doped region 106 107,111 110~112 source line polysilicon plug 651 652 653,654,655 656,657,658 659 660,661 662,663 664 666,667 668a 668b 668c 670,671 672,674 674,675 676 677 Insulating material layer first patterned photoresist layer trench shallow trench second patterned photoresist layer embedding position deep trench metal layer electrode structure memory Material Barrier Layer ') Thermal Insulation Material Layer Curtain Guide Bridge Insulation Member Conductive Plug Position Bit 27

Claims (1)

1328873 X. Patent Application Area 1. A memory element comprising: a first electrode having an upper surface; a second electrode having an upper surface; and an insulating member located at the first electrode and the second electrode The insulating member has a thickness between the first electrode and the second electrode adjacent to the upper surface of the first electrode and the upper surface of the second electrode; a guiding bridge spanning the insulating member, The viaduct has a first side and a second side, and the first side contacts the upper surface of the first and second electrodes, and defines an inter-electrode path to the first across the insulating member Between the electrode and the second electrode, the inter-electrode path has a first path length from the width of the insulating member, wherein the guiding bridge comprises an active layer of a memory material on the first side and has at least two solid phases And a blanket of thermal insulation covering the memory material; and a layer of electrically insulating material over the blanket of thermal insulation, wherein the blanket of thermal insulation has a lower thermal conductivity than the electrical Edge of the material layer. 2. The component of claim 1, wherein the electrically insulating material layer comprises a dioxide dioxide. 3. The component of claim 1, wherein the insulating member has a thickness of about 50 nm or less, and the active layer of the memory material comprises a film having a thickness of about 50 nm or less. . 4. The component of claim 1, wherein the insulating member has a thickness of about 20 nm or less, and the active layer of the memory material comprises a film having a thickness of about 20 nm or less. . The object of claim 1, wherein the active layer of the memory material comprises a film having a thickness of about 10 nm or less. 6. The element of claim 1, wherein the blanket comprises a barrier layer of insulating material between the layer of filaments of the memory material and the blanket of thermal insulation material. The component of claim 1, wherein the blanket comprises a barrier layer located on the active layer of the memory material and the heat=8, as described in claim 1 of the scope of the patent application, and The material contains chalcogenide. T /, 中6玄热绝缘材二包3 = The component described in the first item, wherein the thermal insulation material phase includes: the component, wherein the at least two solids, the book is a non-Japanese phase and one It is usually a crystalline phase. The thickness of the application range is less than the size of the feature used to form the component. The micro-manufacture is as small as the element described in the scope of the patent application, and the active layer has a thicker texture. The material is located between the first side and the second side of the 5H. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Composition. 14. The component of claim 1, wherein the memory material comprises two or more compositions selected from the group consisting of germanium (Ge), germanium (Sb), and germanium (Te). , indium (In), titanium (Ti), gallium (Ga), bismuth (Bi), tin (Sn), copper (Cu), palladium (Pd), lead (Pb), silver (Ag), sulfur (S) And gold (Au). 15. A memory element, comprising: a substrate; an electrode layer on the substrate, the electrode layer comprising an electrode pair array having a first electrode having an upper surface and a second electrode having an upper surface and an insulating layer a member between the first electrode and the second electrode; an array of vias spanning the insulating member of the respective pair of electrodes, the via having a respective first side and a second side, and The first side touches the respective electrodes to the upper surface of the first and the first electrodes, wherein the respective active layers of the guide bridge comprising a memory material on the first side have at least two solid phases, and a blanket of thermal insulation material overlying the memory material; a layer of electrically insulating material over the array of vias, wherein the thermal insulation material has a lower thermal conductivity than the layer of electrically insulating material; and a bit line is Above the layer of insulating material, the via in the layer of electrically insulating material is in contact with the bridge in the array of vias. The thickness of the 丄汐厶〇〇/J. The component of item 15, wherein the insulating member comprises a thin adenes or below, and the active layer of the memory material has a thickness of about 50 Nano or below. 17的厚ΐ The object of claim 15, wherein the insulating member has a twisted nozzle of 2 nanometers or less and the active material of the memory material comprises a film having a thickness of about 2G nanometer or Town. Qin Guangyu The element of claim 15 wherein the memory material, the μ active layer comprises a film having a thickness of about 10 nm or less. 19. The element of claim 15 wherein the blanket comprises an electrically insulating material barrier between the active layer of the memory material and the blanket of thermal insulation material. 20. The element of claim 15 wherein the blanket comprises a diffusion barrier layer between the active layer of the memory material and the thermal insulation blanket. 21. The element of claim 15 wherein the thermally insulating material comprises a chalcogenide. 22. The element of claim 15 wherein the thermally insulating material comprises polyamidamine. 23. The element of claim 15 wherein the at least two solid 31 1328873 phase comprises a generally amorphous phase and a generally crystalline phase. 24. The component of claim 15 wherein the thickness of the insulating member is less than a minimum lithographic feature size used to form a lithography process of the component. 25. The component of claim 15 wherein the active layer of the memory material has a thickness between the first side and the second side that is less than a lithography process for forming the component. A minimum lithography feature size. 26. The element of claim 15 wherein the memory material comprises a composition formed by a fault, a record, and a flaw. 27. The element of claim 15 wherein the memory material comprises two or more compositions selected from the group consisting of germanium (Ge), germanium (Sb), and germanium (Te). , indium (In), titanium (Ti), gallium (Ga), money (Bi), tin (Sn), copper (Cu), palladium (Pd), lead (Pb), silver (Ag), sulfur (S) And gold (An). Ί 28. A method of fabricating a memory device, comprising: forming an electrode layer, the electrode layer comprising a first electrode having an upper surface, a second electrode having an upper surface and an insulating member on the first electrode And an upper surface of the electrode layer between the second electrode, the insulating member extends to form an insulating wall on the upper surface of the electrode layer, and the insulating member has the first electrode and the second electrode a width between the upper surfaces; 32 丄 (10) 873 layers of Ξί:: bridges across the electrode of the insulating member, the ί=Ϊ contact' and a thermal insulating blanket on the active layer; i and Μ哼; The inter-electrode path has a path through the first electrode 横跨:: across the insulating member - from the absolute phase; and an L length, wherein the memory material has at least two solid-formed-dielectric material layers thereon Including - a thermal blanket "having a guide-less contact with a blanket, wherein the insulating member comprises a thin crucible having a thickness of about 50 nm or a material (four) of the active layer package = method" wherein the insulating member comprises a film The active layer package of its thickness material ^Package::? The method of claim 28, wherein the thickness of the patch is about V1G nanometer or the middle and the lower is a pair of the plurality of pairs and the other electrode pair and the isolation member are separated . The method of claim 28, wherein the forming 1 33 1328873 forms a memory material layer over the upper surface of the electrode layer; forming a layer of thermal insulating material over the memory material layer; patterning the A layer of memory material and the layer of thermal insulation material define the bridge. The method of claim 28, wherein the forming the first and second electrodes comprises a double damascene process. 34