CN101132050A - Thin film fuse phase change cell with thermal isolation layer and manufacturing method - Google Patents
Thin film fuse phase change cell with thermal isolation layer and manufacturing method Download PDFInfo
- Publication number
- CN101132050A CN101132050A CNA2007101364861A CN200710136486A CN101132050A CN 101132050 A CN101132050 A CN 101132050A CN A2007101364861 A CNA2007101364861 A CN A2007101364861A CN 200710136486 A CN200710136486 A CN 200710136486A CN 101132050 A CN101132050 A CN 101132050A
- Authority
- CN
- China
- Prior art keywords
- electrode
- layer
- storage medium
- bridge
- insulating component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention discloses a memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A damascene patch crosses the insulating member aligned with the first and second electrodes, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. The bridge comprises a active layer of phase change material having at least two solid phases at the first end and a material layer of heat insulating cover layer is on the memory material, wherein the said heat insulating cover layer has lower thermal conductivity than the electrical insulating material layer.
Description
Technical field
The present invention relates to use the high density memory element of phase change storage medium, comprise material and other material, and relate in order to make the method for this element based on chalcogenide.
Background technology
The storage medium that turns to the basis with phase transformation is applied in the writable disc widely.These materials include at least two kinds of solid-state phases, comprise that as major part be amorphous solid-state phase, and the solid-state phase that is substantially crystalline state.Laser pulse is used for writable disc, switching in mutually at two kinds, and reads the optical property of this kind material after phase change.
As this phase change storage medium of chalcogenide and similar material, can be applicable to electric current in the integrated circuit by applying its amplitude, and cause crystalline phase to change.Generally speaking amorphously be characterized as resistance and be higher than crystalline state, this resistance value can measure and easily in order to as indication.This specific character then causes uses programmable resistor material with interest such as formation Nonvolatile memory circuits, and this circuit can be used for the arbitrary access read-write.
Be converted to crystalline state from amorphous state and be generally the low current step.Be converted to amorphous state (following denotion is for resetting (reset)) from crystalline state and be generally high electric current step, it comprises that of short duration high current density pulse is to melt or destruction crystalline texture, thereafter this phase-transition material cooling fast, the process that suppresses phase change makes that at least partly phase change structure is maintained in amorphous state.Under the perfect condition, causing phase-transition material to be converted to amorphous reset current amplitude from crystalline state should be low more good more.Desire reduces the required reset current amplitude of resetting, can by reduce the phase-transition material size of component in memory and reduce electrode therewith the contact area of phase-transition material realize, therefore can apply less absolute current value and realize higher current density at this phase-transition material element.
A kind of method of this field development is devoted to form small hole on integrated circuit structure, and uses micro-programmable resistance material to fill these small holes.The patent of being devoted to this small hole comprises: at No. the 5th, 687,112, the United States Patent (USP) " Multibit Single CellMemory Element Having Tapered Contact " that on November 11st, 1997 announced, the invention people is Ovshinky; No. the 5th, 789,277, the United States Patent (USP) of announcing on August 4th, 1998 " Method of Making Chalogenide[sic] Memory Device ", the invention people is Zahorik etc.; No. the 6th, 150,253, the United States Patent (USP) of announcing on November 21st, 2000 " Controllable Ovonic Phase-ChangeSemiconductor Memory Device and Methods of Fabricatingthe Same ", the invention people is Doan etc.
When making these devices and desire with very little yardstick and satisfy production large scale storage device, during required strict technological parameter, then can encounter problems.One of them problem relevant with the phase change cell of reduced size is that the conductive coefficient by the material that is surrounded on active region is caused.In order to cause phase change to take place, the temperature of the phase-transition material in active region must reach the critical value of phase change.Yet, can be conducted away very soon around structure by the heat that electric current produced by phase-transition material.The heat interior phase-transition material of active region thus conducts away the heating effect that can reduce electric current, also can disturb the running of this phase-transition material simultaneously.
Therefore, hope can provide a kind of memory cell (memory cell) structure its include small size and low reset current, and in order to make the method for this structure, the strict technological parameter specification when it can satisfy production large scale storage device.Preferably, provide a kind of fabrication schedule and structure, it is compatible in order to make peripheral circuit on same integrated circuit.
Summary of the invention
The present invention describes a kind of phase change random access memory (PCRAM) element, and it is applicable in the large scale integrated circuit.Technology described herein comprises memory element, and it comprises first electrode with top side, second electrode with top side and the insulating component between first electrode and second electrode.Insulating component has a thickness between first and second electrode, near the top side of first electrode and the top sides of second electrode.Film is led bridge across insulating component, and between first and second electrode, defined path between electrode across the insulating component place.This film is led the active layer that bridge comprises phase-transition material, and this active layer and its isolation of heat between structure layer of cover material down is provided.This cladding material that provides heat to isolate can comprise the material identical with the phase-transition material of active layer.This cladding material that provides heat to isolate can comprise composite construction, it has first separator, and second separator, wherein separator is isolated active layer and thermal insulation layered material, and/or prevents that as diffusion impervious layer material from moving between active layer and thermal insulation layered material.Across path between the electrode of insulating component, have path, its width by insulating component is defined.For convenience of description, this leads bridge and can be considered structure as fuse.Yet for Ovonics unified memory, its not similar fuse, but having comprised chalcogenide materials or similar material with at least two kinds of solid-state phases, these two kinds of solid-state phases can be by applying electric current or applying voltage and reversibly bring out between first and second electrode betwixt.Electrical insulation material layer is positioned on this heat insulator cover layer, and wherein this heat insulator cover layer thermal conductivity is lower than this electrical insulation material layer.
The volume that is subjected to the storage medium of phase change can be very small, and by the thickness (path of x axle) of insulating component, in order to form the film thickness (y axle) of leading bridge and to lead that the width (z axle) perpendicular to path is defined in the bridge.In an embodiment, the width of insulating component and lead the thickness of the film storage medium of bridge in order to formation is defined by film thickness, but is not limited in order to form two kinds of pattern process of this memory cell.The width of leading bridge is less than minimum feature size F, and this characteristic size F is peculiar by employed photoetching process when the material layer of the patterning embodiment of the invention.In one embodiment, the width of leading bridge utilizes the photoresist pruning technique to define, wherein on this wafer, it has minimum feature size F to mask pattern in order to the definition photoresist structure, and this photoresist structure utilizes isotropic etching to prune to realize the characteristic size less than F.Photoresist structure through pruning then is used to shift the insulation material layer of this narrower pattern to the storage medium.Simultaneously, also can use other technology to form the narrow line of material in the one deck in integrated circuit.Therefore, have the phase change memory cell of simple structure, can realize the very small reset current and the purpose of low power consuming, and be easy to make.
In the embodiment of technology of the present invention, provide memory cell array.In this array, a plurality of electrode members and the insulating component between electrode member form electrode layer on integrated circuit.This electrode layer has upper surface, and it is smooth in fact surface in certain embodiments of the invention.Between the paired electrode member, lead bridge across corresponding a plurality of films of insulating component, it has the thermal insulation cover layer.First electrode from electrode layer passes through the film of electrode layer upper surface and leads bridge, and arrives the current path of second electrode in the electrode layer, is formed in each memory cell in this array.
In the present invention, the circuit under the electrode layer in the integrated circuit utilizes knownly to form in order to the technology that forms logical circuit and storage array circuit, for example complementary metal oxide semiconductor (CMOS) technology.
In addition, in the described herein array implement example, the circuit on this electrode layer and have the tectal bridge array of leading of thermal insulation and comprise a plurality of bit lines.Among the embodiment of described herein bit line on electrode layer, the electrode member that is arranged in electrode layer is shared as first electrode of memory cell, can cause the unitary electrode member that first electrode as two memory cell in the array delegation is provided.In addition, among the described herein embodiment, the bit line in the multiple bit lines can be arranged to the corresponding row in the array, and two adjacent sub memory cells in the corresponding row are enjoyed contact structures to contact with first electrode.
The present invention also describes a kind of method of making memory element.The method is included on the substrate of finishing the FEOL generative circuit and forms electrode layer.This electrode layer has upper surface, and this electrode layer comprises first electrode and second electrode, and insulating component is about to the phase change memory cell of formation for each between this first electrode and this second electrode.This first electrode, second electrode and insulating component extend in the upper surface of this electrode layer, and this insulating component has a width between this first electrode and second electrode top, and are connected with described phase variation storage unit structure before.The method also comprises and forms the storage medium lead bridge, is being about to the phase change memory cell that forms across this upper surface of this electrode layer of this insulating component for each, and this leads bridge and has the thermal insulation cover layer.This leads bridge and also comprises the storage medium film, and it has one first end and one second end, and with first and second electrode in first end in contact.This leads bridge path between the definition electrode between across this first electrode of this insulating component and this second electrode, and the path has by the defined path of this insulating component width between this electrode.In the embodiment of the method, the access structure utilization on this electrode layer is led on the bridge conductive layer that forms patterning at this and is realized, and forms contact between the conductive layer of patterning therewith at this first electrode.
Other purpose of the present invention and advantage etc. can see through following to claims and fully understanding of the description of the drawings acquisition.
Description of drawings
Fig. 1 illustrates a phase change storage element film and leads the embodiment of bridge;
Fig. 2 illustrates one group of schematic perspective view that has at the phase change storage element of access circuit under the electrode layer and the bit line structure on this electrode layer;
Fig. 3 illustrates the floor map of structure among Fig. 2;
Fig. 4 illustrates the storage array that comprises the phase change storage element;
Fig. 5 is the integrated circuit component calcspar that includes film fuse phase change storage array and other circuit;
Fig. 6 is the first step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Fig. 7 is the second step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Fig. 8 is the third step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Fig. 9 is the 4th a step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Figure 10 is the 5th a step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Figure 11 is the 6th a step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Figure 12 is the 7th a step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Figure 13 is the 8th a step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Figure 14 is the 9th a step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Figure 15 is the tenth a step profile in order to the dual-damascene technics that forms the memory element electrode layer;
Figure 16 is the 11 a step profile in order to the dual-damascene technics that forms the memory element electrode layer.
Embodiment
Film fuse phase change memory cell of the present invention, the formed array of this memory cell and in order to make the method for this memory cell are done narration at length with reference to figure 1-16.
Fig. 1 illustrates the basic structure of memory cell 10, comprises the bridge of memory material 11 that is positioned on the electrode layer, and it comprises first electrode 12, second electrode 13 and the insulating component 14 between first electrode 12 and second electrode 13.As shown in the figure, first and second electrode 12,13 has upper surface 12a and 13a.In the same manner, also has upper surface 14a.In this embodiment, the upper surface 12a of these structures in electrode layer, 13a, 14a has defined the smooth in fact upper surface of electrode layer.In other embodiments, upper surface 12a, 13a, 14a for example can extend to form the wall of insulation between electrode by insulating component 14 not at grade.Bridge of memory material 11 comprises the active layer 15 of the storage medium on the flat upper surfaces that is positioned at electrode layer, make at first electrode and lead between the bridge 11, and second electrode 13 with lead contacting between the bridge 11, realized by active layer 15 bottom sides of leading bridge 11.This leads bridge 11 and comprises heat-insulating cover layer, and its heat insulator that includes barrier layer 16 and 17 covers on the active layer 15 of storage medium, with thermal limit that active layer 15 is produced in the active region of this memory cell.This barrier layer 16 comprises that as materials such as silica or silicon nitrides it can provide the electric insulation between active layer 15 and layer 17.And this barrier layer 16 also can be used as the usefulness of the diffusion impervious layer between heat insulator layer 17 and memory cell active layer 15.In shown embodiment, this cover layer only covers the top of active layer 15.In other embodiments, this cover layer also can coat the side of active layer 15.In addition, barrier layer 16 and heat insulator layer 17 also can comprise layered composite structure separately.
The execution mode of access circuit can multiple configuration contact to first electrode 12 and second electrode 13, operation with the control store unit, the active layer 15 that makes it to be programmed and will lead bridge 11 is set in one of two kinds of solid-state phases, and these two kinds of solid-state phases can be utilized storage medium and reversibly implement.For example, use contains the phase change storage medium of chalcogenide, this memory cell can be set to high relatively Resistance states, wherein this to lead at least one part of bridge in current path be amorphous state, and the major part of leading bridge in current path is in quite low-resistance crystalline state.
Active region in this active layer 15 is in the phase change memory cell, material is brought out with in two kinds of solid-state zones of switching in mutually at least.In shown embodiment, this active region that is arranged in active layer 15 is roughly on insulating component 14.Be understandable that this active region can be made very smallly, reduce in order to bring out the needed current amplitude of phase change.
The length L of this active region (x axle) is defined by the thickness of insulating component 14 (being called raceway groove electricity dielectric among the figure) between first electrode 12 and second electrode 13.This length L can be controlled by the width of the insulation wall 14 among the control store unit embodiment.(in representing embodiment, we do not use the length of film definition insulation wall 14 ...)
Similarly, in memory cell embodiment lead bridge thickness T (y axle) can be very small.Leading the bridge thickness T can be formed on the upper surface of first electrode 12, insulation wall 14 and second electrode 13 by using film deposition techniques.Therefore, among the memory cell embodiment, leading the bridge thickness T is below the 50nm.Among the embodiment of other memory cell, leading bridge thickness is below the 20nm.Leading the bridge thickness T in other embodiments is below the 10nm.Scrutablely be, lead the bridge thickness T even can utilize as technique for atomic layer deposition etc. and less than 10nm, demand on application-specific is decided, as long as this thickness can make and leads the purpose that bridge is carried out its storage element, that is have at least two kinds of solid-state phases and reversibly brought out by electric current or the voltage that is applied between first and second electrode.
It is also very small to lead bridge width W (z axle).In a preferred embodiment, this leads the bridge width W and is less than 100nm.In certain embodiments, leading the bridge width is below the 40nm.
The embodiment of memory cell comprise with phase transformation turn to the basis storage medium was constituted leads bridge 11, phase-transition material can comprise that chalcogenide is material and other material on basis.Chalcogenide comprises any one of following quaternary element: oxygen (O), sulphur (S), selenium (Se) and tellurium (Te), the part of VI family on the forming element periodic table.Chalcogenide comprises chalcogen and more electropositive element or combined with radical is got.The chalcogen compound alloy comprises chalcogen compound is combined with other material such as transition metal etc.The chalcogen compound alloy generally includes the element that is selected from the periodic table of elements the 6th hurdle more than, for example germanium (Ge) and tin (Sn).Usually, more than one compound in the column element under the chalcogen compound alloy comprises: antimony (Sb), gallium (Ga), indium (In) and silver (Ag).Many with phase transformation turn to the basis storage medium be described in the technological document, comprise following alloy: gallium/antimony, indium/antimony, indium/selenium, antimony/tellurium, germanium/tellurium, germanium/antimony/tellurium, indium/antimony/tellurium, gallium/selenium/tellurium, tin/antimony/tellurium, indium/antimony/germanium, silver/indium/antimony/tellurium, germanium/tin/antimony/tellurium, germanium/antimony/selenium/tellurium and tellurium/germanium/antimony/sulphur.In germanium/antimony/tellurium alloy family, can attempt large-scale alloying component.This composition can following feature formula be represented: Te
aGe
bSb
100-(a+b)
A researcher has described the most useful alloy and has been, average tellurium concentration included in deposition materials is far below 70%, typically be lower than 60%, and the tellurium content range in the general type alloy is from minimum 23% to the highest by 58%, and preferably between 48% to 58% tellurium content.The concentration height of germanium is about 5%, and its average range in material generally is lower than 50% from minimum 8% to the highest by 30%.Preferably, the concentration range of germanium is between 8% to 40%.Remaining main component then is an antimony in this composition.Above-mentioned percentage is atomic percent, and all constituent elements summation is 100%.(Ovshinky ' 112 patents, hurdle 10～11) comprises Ge by the specific alloy that another researcher assessed
2Sb
2Te
5, GeSb
2Te
4And GeSb
4Te
7(NoboruYamada, " Potential of Ge-Sb-Te Phase-change OpticalDisks for High-Data-Rate Recording ", SPIE v.3109, pp.28-37 (1997)) more generally, transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and above-mentioned mixture or alloy, can combine with germanium/antimony/tellurium to form the phase change alloy, it includes programmable electrical resistance property.The specific examples of spendable storage medium, as described in Ovshinsky ' 112 patent intermediate hurdles 11-13, its example is listed reference at this.
The phase change alloy can be first configuration state of general noncrystalline state and be to switch between second configuration state of general crystalline solid state at material according to its sequence of positions in this element active channel zone.These alloys are at least Bistable.This term " amorphous " is in order to referring to more inordinate relatively structure, and it is than monocrystalline property more out of order, and has detectable feature as than the higher resistance value of crystalline state.This term " crystalline state " is in order to referring to structure relatively more orderly, and therefore it include detectable feature, for example lower than amorphous state resistance value than amorphous state orderliness more.Typically, phase-transition material can switch to all detectable different conditions between complete crystalline state and the complete amorphous state by electricity.Other is subjected to the change of amorphous state and crystalline state and the material characteristics that influences comprises atom order, free electron density and activation energy.This material is changeable to become different solid-state or changeable becoming by two or more solid-state formed mixtures, provides from amorphous state to the gray scale part between the crystalline state.Electrical property in this material also may change thereupon.
The phase change alloy can switch to another phase from a kind of phase by applying electric pulse.The previous observation points out that short, the tendency of pulse by a relatively large margin changes in the phase with phase-transition material and is roughly amorphous state.Long, change in phase than the pulse tendency of low amplitude and to be roughly crystalline state phase-transition material.Short, the energy in the pulse is enough big by a relatively large margin, therefore is enough to destroy the bonding of crystalline texture, enough simultaneously shortly therefore can prevent that atom is arranged in crystalline state once more.Do not having under the situation of inappropriate experiment, can determine to be specially adapted to the suitable pulsed quantity varied curve that specific phase changes alloy.At the further part of this paper, this phase-transition material is with the GST designate, and we also need to understand simultaneously, also can use the phase-transition material of other type.Described in this article a kind of material that is useful among the PCRAM is Ge
2Sb
2Te
5
Other the programmable storage medium that can be used among other embodiment of the present invention comprises doping N
2GST, Ge
xSb
yOr other decides the Substance P r of resistance with different crystalline state conversions
xCa
yMnO
3, PrSrMnO, ZrO
x, TiO
x, NiO
x, WO
x, the SrTiO through mixing
3Or other utilizes electric pulse to change the material of resistance states; Or other uses electric pulse to change the material of resistance states; TCNQ (7,7,8,8-tetracyanoquinodimethane), PCBM (methanofullerene6,6-phenyl C61-butyric acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C
60It includes-TCNQ, the TCNQ that mixes with other material or any other polymeric material the bistable controlled with electric pulse or multistablely decides Resistance states.
The material of heat insulator layer 17 can use the material identical with storage medium, as the GST in an embodiment of this element.In other embodiments, this heat insulator 17 comprises that polyvinylamine or other have than this and leads the material that dielectric layer on the bridge is low heat conduction number.The representative materials of heat insulator layer comprises following element combinations and the material of layer: silicon, carbon, oxygen, fluorine and hydrogen.Be fit to use heat insulator, comprise silicon dioxide, hydrogen-oxygen carborundum, pi, polyamide and fluorocarbon polymer as the thermal insulation cap rock.Other is fit to use as the tectal material of thermal insulation, comprises fluorinated silica, silsesquioxane (silsesquioxane), poly-cyclenes ether (polyarylene ether), Parylene (parylene), fluoropolymer, fluoride amorphous carbon, diamond-like-carbon, poriness silicon oxide, mesopore (mesoporous) silica, porousness silsesquioxane, porousness pi and porousness cyclenes ether.The single or multiple lift structure can provide thermal insulation and electric insulating effect.
Fig. 2 has described the structure of PCRAM unit.These unit are formed on the semiconductor substrate 21.For example the insulation system of shallow ridges channel insulation electricity dielectric (STI) (not shown) etc. has been isolated paired memory cell access transistors row.This access transistor act as the common source zone and n type terminal 25,27 act as drain terminal with n type terminal 26 in P type substrate 21.Polysilicon word line 23,24 grids as access transistor.The dielectric fill layer (not shown) is formed on the polysilicon word line.This layer is the conductive structure of patterning, comprises that common source line 28 and embolism structure 29,30 are formed.These electric conducting materials can be the usefulness that tungsten or other material and combination are suitable as embolism and conductor structure.Common source line 28 contact is to the source region 26, and row in the array and act as common source line.This embolism structure 29,30 contacts respectively to drain terminal 25,26.The upper surface that packed layer (not shown), common source line 28 and embolism structure 29,30 all have general planar perhaps is fit to use the substrate as forming electrode layer 31.
This electrode layer 31 has comprised electrode member 32,33,34, it is by as insulated gate 35a, and insulating component such as 35b and with separate, and basal component 39, wherein insulated gate is formed by sidewall technology as described below.In the structure of present embodiment, basal component can be thicker than insulated gate 35a, 35b, and electrode member 33 and common source line 28 are isolated.For example, the thickness of basal component can be between 80 to 140nm, and insulated gate then far is narrower than this, because must reduce the capacitive coupling between source electrode line 28 and electrode member 33.In the present embodiment, insulated gate 35a, 35b have comprised the thin film dielectric material on the sidewall of electrode member 32,34, and its thickness on electrode layer 31 surfaces is determined by the film thickness on the sidewall.
The storage of composite material is led bridge 36a (for example GST) and is positioned on the cover layer, it comprises barrier layer 36a and heat insulator layer 36c, it is positioned at a side on the electrode layer 31, forms first memory cell across insulative sidewall 35a, film bridge of memory material 37 (for example GST) are positioned on the cover layer simultaneously, it comprises barrier layer 37a and heat insulator layer 37c, is positioned at opposite side on the electrode layer 31, forms second memory cell across insulated gate 35b.
The dielectric fill layer (not shown) is positioned at film leads on the bridge.Dielectric fill layer comprises silicon dioxide, pi, silicon nitride or other dielectric packing material.It is low conductive coefficient that this heat insulator layer cover layer 37c has than this filling dielectric layer.Tungsten plug 38 contacts to electrode member 33.Include the patterned conductive layer 40 of metal or other electric conducting material (being included in the bit line in the array structure), be positioned on the dielectric fill layer, and contact to embolism 38 and lead the active layer 36a of bridge left and the access that film is led the memory cell of right-hand active layer 37a of bridge for corresponding to film to set up.
Fig. 3 is presented at the structure on the semiconductor substrate 21 among Fig. 2, presents in the mode of layout.Therefore, the arrangement of word line 23,24 is parallel to common source line 28 in fact, the common source line in the memory cell array and arranging. Embolism 29,30 contacts the terminal of the access transistor to the semiconductor substrate and the bottom side of electrode member 32,34 respectively.Film bridge of memory material 36,37 is positioned on the electrode member 32,33,34, and insulated gate 35a, 35b separate these electrode members.Embolism 38 contact is to leading the electrode member 33 between bridge 35 and 37 and the bottom side of the metal bit line under patterned conductive layer 40 41 (being transparent) in Fig. 3.Metal bit line 42 (nontransparent) also is illustrated among Fig. 3, to emphasize the array layout of this structure.
In operation, correspond to the access of the memory cell of leading bridge 36, control signal to word line 23 and realize that word line 23 is coupled to film with common source line 28 via terminal 25, embolism 29 and electrode member 32 and leads bridge 36 by applying.Electrode member 33 is coupled to a bit line in patterned conductive layer via contact embolism 38.Similarly, correspond to the access of the memory cell of leading bridge 37, control signal to word line 24 and realize by applying.
Scrutable is can use multiple different materials in the structure of Fig. 2 and Fig. 3.For example, can use copper metallization.The metallization of other type such as aluminium, titanium nitride and tungstenic material etc. also can be used.Simultaneously, also can use as non-metallic conducting materials such as polysilicon through mixing.Employed electrode material in described embodiment is preferably titanium nitride or tantalum nitride.Perhaps, this electrode can be TiAlN or the aluminium nitride tantalum maybe can comprise the element that is selected from more than in the following cohort: titanium (Ti), tungsten (W), molybdenum (Mo), aluminium (Al), tantalum (Ta), copper (Cu), platinum (Pt), iridium (Ir), lanthanum (La), nickel (Ni) and ruthenium (Ru) and by alloy that above-mentioned element constituted. Insulated gate 35a, 35b can be the electric dielectric of silicon dioxide, silicon oxynitride, silicon nitride, aluminium oxide or other low-k between electrode.Perhaps, insulating barrier can comprise the element that is selected from following cohort more than between electrode: silicon, titanium, aluminium, tantalum, nitrogen, oxygen and carbon.
Fig. 4 is the schematic diagram that storage array is shown, the description that it can be done with reference to figure 2 and Fig. 3 and implementing.Therefore, the label among Fig. 4 is corresponding to the label among Fig. 2 and Fig. 3.Scrutable is that the array structure shown in Fig. 4 can utilize other cellular construction and implement.In the explanation of Fig. 4, common source line 28, word line 23 are parallel to Y-axis haply with word line 24.Bit line 41 is parallel haply in X-axis with 42.Therefore, Y decoder and word line driver in square 45 are coupled to word line 23,24.X decoder in square 46 and one group of sensing amplifier then are coupled to bit line 41,42.Common source line 28 is coupled to the source terminal of access transistor 50,51,52,53.The gate coupled of access transistor 50 is to word line 23.The gate coupled of access transistor 51 is to word line 24.The gate coupled of access transistor 52 is to word line 23.The gate coupled of access transistor 53 is to word line 24.The drain coupled of access transistor 50 to electrode member 32 is led bridge 36 with connection, leads 36 on bridge and then is coupled to electrode member 34.Similarly, the drain coupled of access transistor 51 to electrode member 33 is led bridge 37 with connection, leads 37 on bridge and then is coupled to electrode member 34.Electrode member 34 is coupled to bit line 41.Convenient for diagram, electrode member 34 is positioned at diverse location with bit line 41.Be understandable that in other embodiments, different memory cell are led bridge can use different electrode members.Access transistor 52 and 53 also is coupled to corresponding memory cell on bit line 42.As seen, common source line 28 is shared by two array storage units institute among the figure, and row are wherein arranged along Y-axis.Similarly, electrode member 34 is shared by two memory cell of delegation in array institute, and the row in array then is to arrange along X-axis.
Fig. 5 is the simplification calcspar of integrated circuit according to an embodiment of the invention.Integrated circuit 75 comprises storage array 60, and it utilizes the film fuse phase change memory cell and is based upon on the semiconductor substrate.Column decoder 61 is coupled to a plurality of word lines 62, and each row in the storage array 60 and arranging.Row decoder 63 is coupled to plurality of bit lines 64, these bit lines in the storage array 60 each row and arrange, and read and programming data in order to the multiple-grid utmost point memory cell from array 60.Address is supplied to row decoder 63 and column decoder 61 on bus.Sensing amplifier in the square 66 and data input structure are coupled to row decoder 63 via bus 67.Address provides to row decoder 63 and column decoder 61 from bus 65.Sensing amplifier and data among square 66 are read in (data-in) circuit, are coupled to row decoder 63 via data/address bus 67.Data from the ic substrate 75 input/output end port or from other inside or the external data sources of integrated circuit 75, the data input structure to square 66 is provided via Data In-Line road 71.In described embodiment, this integrated circuit comprises other circuit 74, is supported and the integrate module of SOC (system on a chip) (system on a chip) function can be provided with purpose processor or specific purpose application circuit or with film insurance phase change memory cell array as general.The sensing amplifier of data from square 66 be via DOL Data Output Line road 72, and be sent to the input/output end port of integrated circuit 75, or be sent to integrated circuit 75 inner or other outside data purposes.
The controller of user mode machine 69 in the present embodiment, the application of control bias voltage arrangement supply voltage 68 is for example read, programmes, is wiped, erase-verifying and programming affirmation voltage etc.This controller can use known specific purpose logical circuit.In alternate embodiment, this controller comprises the general purpose processor of using, and it can be applicable in the same integrated circuit, and this integrated circuit is carried out computer program and controlled the operation of this element.In another embodiment, this controller has used specific purpose logical circuit and general combination with the purpose processor.
Fig. 6-16 shows the technology of a kind of structure and dual damascene electrode structure.In dual-damascene structure, dielectric layer forms in two stratum (promptly double-deck) pattern, the groove of first stratum's pattern definition lead wherein, and second stratum's pattern definition connects the through hole of fabric.Single metal deposition step can be used to form lead simultaneously, and insert connect fabric through hole to form conductive connecting line.This through hole and groove can use the lithography step definition of two stages.Groove normally is etched to first degree of depth, and through hole is to be etched to second degree of depth to form the via openings that connects fabric.After through hole and groove were etched, a deposition step can be used to insert metal or other conductive materials at through hole and groove simultaneously.After filling, the unnecessary material that is deposited outside the groove then utilizes chemical mechanical milling tech to remove, and plane, the dual-damascene structure that is filled with conductive materials are finished like this.
Fig. 6 illustrates the artwork of dual-damascene structure, electrical insulation material layer 651, normally dielectric layer is formed on the FEOL structure, as after dual-damascene structure can be formed at wherein usefulness.Utilize FEOL to form the standard CMOS element in the illustrated embodiment, it corresponds to word line, source electrode line and access transistor in the array shown in Figure 2.In Fig. 6, source electrode line 106 cover in the semiconductor substrates through doped region 103, wherein correspond to the source terminal of second access transistor on right side among first access transistor in left side among the figure and the figure through doped region 103.In this embodiment, source electrode line 106 extends to the upper surface of structure 99.In other embodiments, this source electrode line also not exclusively extends to the surface.Through the drain electrode of first access transistor so far of doped region 104 correspondences.The word line that comprises polysilicon 107 is as the grid of this first access transistor.Dielectric layer (not being shown among the figure) 109 is positioned on this polysilicon 107.Embolism 110 contacts so far through doped region 104, and the conductive path surface of structure 99 so far is provided, and is connected to the memory cell electrode in the following manner.Doped region 105 is as the drain electrode end of second access transistor.Include the grid of the word line of polysilicon lines 111 as this second access transistor.Embolism 112 contact is to through doped region 105 and the upper surface of conductive path to structure 99 is provided, and is connected to the memory cell electrode in following mode.Electrical insulation material layer 651 is formed on the FEOL structure, as shown in FIG..
This dual-damascene technics comprises the first patterning photoresist layer 652, and it covers on the layer 651, as shown in Figure 7.This first patterning photoresist layer 652 defines the zone 653,654 and 655 that can be etched in the layer 651 to groove, and it is corresponding to the electrode member in this dual damascene electrode structure.
Use patterning photoresist layer 652 as mask, layer 651 is etched to first degree of depth that does not have complete penetrated bed 651, to form more shallow trench region 656,657 and 658, as shown in Figure 8.Afterwards, as shown in Figure 9, the second patterning photoresist layer 659 is formed on the layer 651.This second patterning photoresist layer 659 defines the electrode member in the zone 660,661 that contacts with embolism 110,112.Use patterning photoresist layer 659 as mask, layer 651 is etched to and penetrates into second degree of depth that contacts with embolism 110,112 fully, to form darker trench region 662,663 in trench region 656,657 and 658, as shown in Figure 10.
Two channeled layer 651 of being finished are inserted metal then, as copper or copper alloy, have well-known to those skilled in the art suitable adhere to and the barrier layer with cambium layer 664, as shown in Figure 11.As shown in Figure 12, the metal level 664 that cmp or other similar techniques are used to remove a part forms the electrode layer with dual damascene electrode 665,666 and 667 structures till dielectric layer 651.This electrode 665 contacts with embolism 110,112 with 6667 structures, and electrode structure 666 is then isolated with source electrode line 106.
At next procedure, as shown in Figure 13, layer storage medium 668a, barrier layer 668b and thermal insulation layer 668c are formed on and inlay on the dielectric layer 651, are called the electrode layer of this element here.The photoresist layer of patterning comprises mask 670 and 671 as shown in Figure 14, is formed on then on layer 668c.This mask 670 and 671 defines the position of storage medium bridge in this memory cell.Afterwards, carry out etching step, keep the previous described memory bridge that multilayer structure constituted 672 and 673 that comprises storage medium active layer, barrier layer and thermal insulation layer to remove the part that layer 669 and 668 not masked 670 and 671 covers.The active layer self-electrode structure 665 of this bridge 672 is extended to electrode structure 666 by insulating component 674.The width of this insulating component 674 defines the length in path between this electrode of crossing over storage medium bridge 672.The active layer self-electrode structure 667 of this bridge 673 is extended to electrode structure 666 by insulating component 675.The width of this insulating component 675 defines the length in path between this electrode of crossing over storage medium bridge 673.
As shown in Figure 16, after defining memory bridge 672 and 673, dielectric fill layer (not being shown among the figure) is formed and planarization in addition.Then, through hole is etched in the dielectric fill layer of inserting electrode member 666.These through holes are received in the embolism as tungsten, to form conductive plug 676.Metal level is patterned then with definition bit line 677, and it contacts with embolism, and arranges to arrange along each right row of memory cell as shown in Figure 16.The material that this dielectric is filled does not perhaps have good heat-insulating barrier layer.Therefore, use heat insulator to have than the lower thermal conductivity of dielectric packing material under it in memory bridge 672 and 673.
Fig. 2 shows the final structure that this dual damascene electrode structure technology is produced, with the dielectric substance of removing in Figure 16 electrode layer 651.
Other and manufacturing and the relevant content of material of implementing the phase change random access memory device, be disclosed in another Application No. the 11/155th of the applicant, in No. 067 " THIN FILM FUSE PHASE CHANGE RAM ANDMANUFACTURING METHOD ", its applying date is on June 17th, 2005 (lawyer's Docket No. MXIC1621-1), this application is classified the application's reference as, and this technology can extend to compound bridge construction described herein easily to form very narrow active layer in this bridge.
In the phase change memory cell kind known to the applicant, most of by forming small hole and inserting phase change memory cell, then form and contact so far that the top and the hearth electrode of phase-transition material form.This small pore space structure is in order to reduce program current.The present invention has reduced program current and need not form small hole, therefore can reach technology controlling and process preferably.In addition, on the unit, there is no top electrode, avoid phase-transition material to be subjected to potential damage in order to the technology that forms top electrode.
Unit described herein comprises two hearth electrodes and electric dielectric therebetween, and is positioned on the electrode, leads bridge across the dielectric phase-transition material of electricity.This hearth electrode and electric dielectric are formed in the electrode layer on FEOL CMOS logical construction or other functional circuit structure, provide and to support built-in storage and the functional circuit structure on single-chip easily, this wafer can be given an example as SOC (system on a chip) (system on chip, SOC) element.
The advantage of embodiment of the present invention comprises that the phase change phenomenon occurs in to lead bridge central authorities on the dielectric fill layer, but not occurs in the face that connects of leading between bridge and the electrode, and therefore preferred reliability is provided.Simultaneously, the electric current that is used in replacement and the programming operation is confined in the small volume, the localized heating effect that has allowed high current density and produced, and only need less reset current and lower replacement power consumption.
Though the present invention is described with reference to preferred embodiment, will be appreciated that the present invention's creation is not subject to its detailed description by us.Substitute mode and revise pattern and advise in formerly describing, and other substitute mode and modification pattern will be expected by those skilled in the art.Particularly, according to structure of the present invention and method, all have be same as in fact member of the present invention in conjunction with and realize with the present invention in fact identical result do not break away from spiritual scope of the present invention.Therefore, all this substitute modes and modification pattern will drop on the present invention in the scope that appended claims and equivalent thereof defined.Any patent application of mentioning in preamble and printed text are all classified the application's reference as.
Claims (34)
1. memory element comprises:
First electrode with upper surface;
Second electrode with upper surface;
Insulating component, it is between described first electrode and described second electrode, described insulating component has certain thickness between described first electrode and described second electrode, near the described upper surface of described first electrode and the described upper surface of described second electrode;
Lead bridge, it is across described insulating component, the described bridge of leading has first side and second side, and with the described upper surface of described first and second electrode of described first side contacts, and path between the definition electrode between across described first electrode of described insulating component and described second electrode, the path has by the defined path of described insulating component width between described electrode, wherein saidly lead bridge comprises storage medium in described first side active layer, it has at least two solid-state phases, and covers the heat insulator cover layer on the described storage medium; And
Electrical insulation material layer is positioned on the described heat insulator cover layer, and wherein said heat insulator cover layer thermal conductivity is lower than described electrical insulation material layer.
2. element as claimed in claim 1, wherein said electrical insulation material layer comprises silicon dioxide.
3. element as claimed in claim 1, the thickness of wherein said insulating component are about 50 nanometers or following, and the described active layer of described storage medium comprises film, and its thickness is about 50 nanometers or following.
4. element as claimed in claim 1, the thickness of wherein said insulating component are about 20 nanometers or following, and the described active layer of described storage medium comprises film, and its thickness is about 20 nanometers or following.
5. element as claimed in claim 1, the described active layer of wherein said storage medium comprises film, its thickness is about 10 nanometers or following.
6. element as claimed in claim 1, wherein said cover layer comprises the electrical insulating material barrier layer, it is between the described active layer and described heat insulator cover layer of described storage medium.
7. element as claimed in claim 1, wherein said cover layer comprises diffusion impervious layer, it is between the described active layer and described heat insulator cover layer of described storage medium.
8. element as claimed in claim 1, wherein said heat insulator comprises chalcogenide.
9. element as claimed in claim 1, wherein said heat insulator comprises pi.
10. element as claimed in claim 1, be generally amorphous phase and be generally crystalline phase wherein said at least two kinds of solid-state comprising mutually.
11. element as claimed in claim 1, the described thickness of wherein said insulating component is less than the minimum lithographic characteristic size of the photoetching process that is used to form described element.
12. element as claimed in claim 1, the described active layer of wherein said storage medium have certain thickness between described first side and described second side, less than the minimum lithographic characteristic size of the photoetching process that is used to form described element.
13. element as claimed in claim 1, wherein said storage medium comprise by the formed composition of germanium, antimony and tellurium.
14. element as claimed in claim 1, wherein said storage medium comprise the composition that two kinds or the above material that is selected from following cohort are formed: germanium (Ge), antimony (Sb), tellurium (Te), indium (In), titanium (Ti), gallium (Ga), bismuth (Bi), tin (Sn), copper (Cu), palladium (Pd), plumbous (Pb), silver (Ag), sulphur (S) and gold (Au).
15. a memory element comprises:
Substrate;
Electrode layer on described substrate, described electrode layer comprises electrode pair array, it has first electrode that upper surface is arranged, second electrode that upper surface is arranged and the insulating component between described first electrode and described second electrode;
Lead the bridge array, it is across the right described insulating component of its individual electrode, the described bridge of leading has separately first side and second side, and with the described upper surface of described first side contacts to its described first and second electrode of electrode pair separately, wherein saidly lead the active layer that each comfortable described first side of bridge comprises storage medium, it has at least two solid-state phases, and heat insulator covers the cover layer on the described storage medium;
Electrical insulation material layer is positioned at described leading on the bridge array, and wherein said heat insulator has the thermal conductivity that is lower than described electrical insulation material layer; And
Bit line on described electrical insulation material layer, the through hole and the described described bridge joint of leading in the bridge array that see through in the described electrical insulation material layer touch.
16. element as claimed in claim 15, the thickness of wherein said insulating component are about 50 nanometers or following, and the described active layer of described storage medium comprises film, its thickness is about 50 nanometers or following.
17. element as claimed in claim 15, the thickness of wherein said insulating component are about 20 nanometers or following, and the described active layer of described storage medium comprises film, its thickness is about 20 nanometers or following.
18. element as claimed in claim 15, the described active layer of wherein said storage medium comprises film, and its thickness is about 10 nanometers or following.
19. element as claimed in claim 15, wherein said cover layer comprises the electrical insulating material barrier layer, and it is between the described active layer and described heat insulator cover layer of described storage medium.
20. element as claimed in claim 15, wherein said cover layer comprises diffusion impervious layer, and it is between the described active layer and described heat insulator cover layer of described storage medium.
21. element as claimed in claim 15, wherein said heat insulator comprises chalcogenide.
22. element as claimed in claim 15, wherein said heat insulator comprises pi.
23. element as claimed in claim 15, be generally amorphous phase and be generally crystalline phase wherein said at least two kinds of solid-state comprising mutually.
24. element as claimed in claim 15, the described thickness of wherein said insulating component is less than the minimum lithographic characteristic size of the photoetching process that is used to form described element.
25. element as claimed in claim 15, the described active layer of wherein said storage medium has certain thickness, and it is between described first side and described second side, less than the minimum lithographic characteristic size of the photoetching process that is used to form described element.
26. element as claimed in claim 15, wherein said storage medium comprise by germanium, antimony, with the formed composition of tellurium.
27. element as claimed in claim 15, wherein said storage medium comprise the composition that two kinds or the above material that is selected from following cohort are formed: germanium (Ge), antimony (Sb), tellurium (Te), indium (In), titanium (Ti), gallium (Ga), bismuth (Bi), tin (Sn), copper (Cu), palladium (Pd), plumbous (Pb), silver (Ag), sulphur (S) and gold (Au).
28. a method of making memory element comprises:
Form electrode layer, described electrode layer comprises the insulating component of the upper surface of first electrode that a upper surface is arranged, second electrode that upper surface is arranged and the described electrode layer between described first electrode and described second electrode, described insulating component extends to forming insulation wall in the described upper surface of described electrode layer, and described insulating component has the width between described upper surface between described first electrode and described second electrode;
At described upper surface across the described electrode layer of described insulating component, the storage medium of bridge is led in formation, describedly lead the active layer that contacts with described first and second electrode that bridge has storage medium, and the thermal insulation cover layer on described active layer, and the described bridge path between the definition electrode between of leading across described first electrode of described insulating component and described second electrode, the path has by the defined path of described insulating component width between described electrode, and wherein said storage medium has at least two kinds of solid-state phases; And
Form dielectric material layer on the bridge described leading, wherein said thermal insulation cover layer comprises heat insulator, and it has the thermal conductivity that is lower than described dielectric substance.
29. method as claimed in claim 28, the thickness of wherein said insulating component are about 50 nanometers or following, and the described active layer of described storage medium comprises film, its thickness is about 50 nanometers or following.
30. method as claimed in claim 28, the thickness of wherein said insulating component are about 20 nanometers or following, and the described active layer of described storage medium comprises film, its thickness is about 20 nanometers or following.
31. method as claimed in claim 28, wherein said formation are led bridge and comprised the formation patch, its thickness is about 10 nanometers or following.
32. method as claimed in claim 28, wherein said formation electrode layer comprise how right first and second electrodes of definition, and insulating element to separate another of a pair of and described many centerings of described many centerings right.
33. method as claimed in claim 28, wherein said formation are led bridge and are comprised:
On the described upper surface of described electrode layer, form storage material layer;
On described storage material layer, form the heat insulator layer;
Described storage material layer of patterning and described heat insulator layer are to define the described bridge of leading.
34. method as claimed in claim 28, described first and second electrodes of wherein said formation comprise dual-damascene technics.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/466,421 | 2006-08-22 | ||
| US11/466,421 US7598512B2 (en) | 2005-06-17 | 2006-08-22 | Thin film fuse phase change cell with thermal isolation layer and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101132050A true CN101132050A (en) | 2008-02-27 |
| CN100502084C CN100502084C (en) | 2009-06-17 |
Family
ID=39129217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101364861A Active CN100502084C (en) | 2006-08-22 | 2007-07-13 | Thin film phase change cell with thermal isolation layer and manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100502084C (en) |
| TW (1) | TWI328873B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839919A (en) * | 2012-11-23 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for electrode, fuse device and manufacturing method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7897954B2 (en) * | 2008-10-10 | 2011-03-01 | Macronix International Co., Ltd. | Dielectric-sandwiched pillar memory device |
-
2007
- 2007-04-18 TW TW96113723A patent/TWI328873B/en active
- 2007-07-13 CN CNB2007101364861A patent/CN100502084C/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839919A (en) * | 2012-11-23 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for electrode, fuse device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI328873B (en) | 2010-08-11 |
| CN100502084C (en) | 2009-06-17 |
| TW200812073A (en) | 2008-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100481555C (en) | I-shaped phase change memory cell, manufacturing method thereof, and array including the same | |
| CN100563040C (en) | Phase change memory cell and manufacture method thereof | |
| CN100555699C (en) | The structure of bistable resistive random access memory and method | |
| CN101127386B (en) | Self-aligning structure and method for limiting resistance random access memorizer melting point | |
| US7598512B2 (en) | Thin film fuse phase change cell with thermal isolation layer and manufacturing method | |
| CN100524880C (en) | I type phase change storage unit with heat insulation structure | |
| CN100573898C (en) | The bottom electrode Ovonics unified memory and the manufacture method thereof of autoregistration and planarization | |
| CN102097587B (en) | Memory device having wide area phase change element and small electrode contact area | |
| CN100583484C (en) | Manufacturing method for pipe-shaped electrode phase change memory | |
| CN101872838B (en) | Memory cell having a buried phase change region and method for fabricating the same | |
| CN101252167B (en) | Programmable resistive memory cell with self-forming gap | |
| CN101197317B (en) | Phase change memory cell with thermal barrier and method for fabricating the same | |
| CN100544016C (en) | Thin film fuse phase change cell and manufacture method thereof with insulating liners | |
| CN100573952C (en) | Use the bridge resistance, random access memory device and the method for single contact structures | |
| CN102522374B (en) | Method for manufacturing a phase change memory device with pillar bottom electrode | |
| CN100593865C (en) | Thermal isolation for an active-sidewall phase change memory cell | |
| CN101252168B (en) | Phase change memory cell with heater and method for fabricating the same | |
| TWI397997B (en) | Memory cell having improved mechanical stability | |
| CN100543966C (en) | In order to make the method for memory element | |
| CN102013431A (en) | Mushroom type memory cell having self-aligned bottom electrode and diode access device | |
| CN100502084C (en) | Thin film phase change cell with thermal isolation layer and manufacturing method | |
| CN100573899C (en) | The embedded phase change ram of self-aligned and manufacture method thereof | |
| CN100583483C (en) | Phase change memory cell and manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |