SG36390G - A semiconductor integrated circuit - Google Patents

A semiconductor integrated circuit

Info

Publication number
SG36390G
SG36390G SG363/90A SG36390A SG36390G SG 36390 G SG36390 G SG 36390G SG 363/90 A SG363/90 A SG 363/90A SG 36390 A SG36390 A SG 36390A SG 36390 G SG36390 G SG 36390G
Authority
SG
Singapore
Prior art keywords
integrated circuit
semiconductor integrated
semiconductor
circuit
integrated
Prior art date
Application number
SG363/90A
Other languages
English (en)
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of SG36390G publication Critical patent/SG36390G/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
SG363/90A 1984-02-13 1990-05-24 A semiconductor integrated circuit SG36390G (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59022811A JPH0795395B2 (ja) 1984-02-13 1984-02-13 半導体集積回路

Publications (1)

Publication Number Publication Date
SG36390G true SG36390G (en) 1990-07-13

Family

ID=12093073

Family Applications (1)

Application Number Title Priority Date Filing Date
SG363/90A SG36390G (en) 1984-02-13 1990-05-24 A semiconductor integrated circuit

Country Status (7)

Country Link
US (6) US4713796A (ja)
JP (1) JPH0795395B2 (ja)
KR (5) KR930006841B1 (ja)
DE (1) DE3504930A1 (ja)
GB (3) GB2156616B (ja)
HK (3) HK42090A (ja)
SG (1) SG36390G (ja)

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JPH0795395B2 (ja) * 1984-02-13 1995-10-11 株式会社日立製作所 半導体集積回路
EP0152939B1 (en) * 1984-02-20 1993-07-28 Hitachi, Ltd. Arithmetic operation unit and arithmetic operation circuit
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JPS62117190A (ja) * 1985-11-15 1987-05-28 Hitachi Ltd 半導体記憶装置
US5229658A (en) * 1985-12-27 1993-07-20 Hitachi, Ltd. Switching circuit
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US5140550A (en) * 1987-03-16 1992-08-18 Hitachi Ltd. Semiconductor memory device
JPS63225991A (ja) * 1987-03-16 1988-09-20 Hitachi Ltd 半導体記憶装置
JPH0611111B2 (ja) * 1987-03-27 1994-02-09 株式会社東芝 ＢｉＭＯＳ論理回路
JP2629697B2 (ja) * 1987-03-27 1997-07-09 日本電気株式会社 半導体記憶装置
US6295241B1 (en) * 1987-03-30 2001-09-25 Kabushiki Kaisha Toshiba Dynamic random access memory device
JP2531671B2 (ja) * 1987-03-31 1996-09-04 株式会社東芝 半導体記憶装置
JP2585602B2 (ja) * 1987-06-10 1997-02-26 株式会社日立製作所 半導体記憶装置
JP2598412B2 (ja) * 1987-07-10 1997-04-09 株式会社日立製作所 半導体記憶装置
US5027323A (en) * 1988-01-14 1991-06-25 Hitachi, Ltd. Write pulse signal generating circuit for a semiconductor memory device
US5144163A (en) * 1988-03-14 1992-09-01 Matsushita Electric Industrial Co., Ltd. Dynamic BiCMOS logic gates
JPH01232826A (ja) * 1988-03-14 1989-09-18 Matsushita Electric Ind Co Ltd ダイナミック型論理回路
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US5175826A (en) * 1988-05-26 1992-12-29 Ibm Corporation Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385
KR910002034B1 (ko) * 1988-07-21 1991-03-30 삼성전자 주식회사 다분할형 메모리 어레이의 충전등화회로
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EP0426597B1 (en) * 1989-10-30 1995-11-08 International Business Machines Corporation Bit decode scheme for memory arrays
US5022010A (en) * 1989-10-30 1991-06-04 International Business Machines Corporation Word decoder for a memory array
US5030853A (en) * 1990-03-21 1991-07-09 Thunderbird Technologies, Inc. High speed logic and memory family using ring segment buffer
US5105105A (en) * 1990-03-21 1992-04-14 Thunderbird Technologies, Inc. High speed logic and memory family using ring segment buffer
CA2042432A1 (en) * 1990-05-31 1991-12-01 Robert M. Reinschmidt Memory selection circuit
US5222039A (en) * 1990-11-28 1993-06-22 Thunderbird Technologies, Inc. Static random access memory (SRAM) including Fermi-threshold field effect transistors
JP3109750B2 (ja) * 1991-06-27 2000-11-20 株式会社東芝 半導体記憶装置
US5239506A (en) * 1991-02-04 1993-08-24 International Business Machines Corporation Latch and data out driver for memory arrays
JP2717740B2 (ja) 1991-08-30 1998-02-25 三菱電機株式会社 半導体集積回路装置
KR930017033A (ko) * 1992-01-17 1993-08-30 가나이 스토무 반도체 기억장치
JPH06162782A (ja) * 1992-11-17 1994-06-10 Hitachi Ltd 半導体集積回路装置
US5612892A (en) * 1993-12-16 1997-03-18 Intel Corporation Method and structure for improving power consumption on a component while maintaining high operating frequency
DE69527814T2 (de) 1994-01-19 2002-12-12 Matsushita Electric Ind Co Ltd Integrierte Halbleiterschaltung mit zwei Versorgungsspannungen
TW305958B (ja) * 1995-05-26 1997-05-21 Matsushita Electric Ind Co Ltd
DE69518632T2 (de) * 1995-06-26 2001-05-03 St Microelectronics Srl Bitzeilen-Selektions-Dekodierer, insbesondere für elektronische Speicher
JP2800734B2 (ja) * 1995-09-06 1998-09-21 日本電気株式会社 半導体集積回路
US6175952B1 (en) * 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions

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Also Published As

Publication number Publication date
KR850006234A (ko) 1985-10-02
JPS60170090A (ja) 1985-09-03
US4713796A (en) 1987-12-15
DE3504930A1 (de) 1985-08-14
KR930000712B1 (ko) 1993-01-30
GB2189958B (en) 1988-04-27
KR910016236A (ko) 1991-09-30
GB2189958A (en) 1987-11-04
US5311482A (en) 1994-05-10
GB2156616B (en) 1988-04-27
GB8503310D0 (en) 1985-03-13
KR910016234A (ko) 1991-09-30
US5042010A (en) 1991-08-20
GB2189957B (en) 1988-04-27
HK44990A (en) 1990-06-15
KR930006842B1 (ko) 1993-07-24
GB8714910D0 (en) 1987-07-29
JPH0795395B2 (ja) 1995-10-11
KR910016235A (ko) 1991-09-30
GB2189957A (en) 1987-11-04
HK42090A (en) 1990-06-08
HK94890A (en) 1990-11-23
KR930006841B1 (ko) 1993-07-24
US4858189A (en) 1989-08-15
US5371713A (en) 1994-12-06
GB8714911D0 (en) 1987-07-29
GB2156616A (en) 1985-10-09
US4924439A (en) 1990-05-08
KR930006843B1 (ko) 1993-07-24

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