KR970067703A - 반도체 장치와 그의 제작 방법 - Google Patents

반도체 장치와 그의 제작 방법 Download PDF

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KR970067703A
KR970067703A KR1019970008129A KR19970008129A KR970067703A KR 970067703 A KR970067703 A KR 970067703A KR 1019970008129 A KR1019970008129 A KR 1019970008129A KR 19970008129 A KR19970008129 A KR 19970008129A KR 970067703 A KR970067703 A KR 970067703A
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film
silicon
amorphous carbon
silicon nitride
oxide film
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KR100308101B1 (ko
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요시시게 마츠모토
요시타케 오니시
가주히코 엔도
도루 다추미
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가네꼬 히사시
닛폰 덴키 주식회사
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Abstract

주 성분으로 탄소와 불소를 포함하는 비결정질 불화탄소막을 포함하는 절연막에 의해 배선층이 서로 전기적으로 고립되고, 배선층이 절연층을 통해 침투된 홀(hole)에 묻히는 전도 물질에 의해 전기적으로 연결되는 반도체 장치는 비결정질 불화탄소막을 선택적으로 에칭함으로서 제작된다. 더욱이, 산화실리콘막, 질화실리콘막, 또는 질산화실리콘막이 비결정질 불화탄소막 및 상기 홀의 측면 표면 모두에, 또는 비결정질 불화탄소막 및 측면 표면 중 하나에 형성된다.

Description

반도체 장치와 그의 제작 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 실시예에서 얻어진 완료된 다층 상호연결 구조를 도시하는 단면도

Claims (14)

  1. 반도체 장치의 제작 방법에 있어서, 주 성분으로 탄소와 불소를 포함하는 비결정질 불화탄소막이 실리콘형 레지스트(silicone type resist)를 에칭 마스크(etching mask)로 이용하여 선택적으로 에칭되어지는 것을 특징으로 하는 제작 방법.
  2. 제1항에 있어서, 상기 비결정질 불화탄소막이 산소 플라스마(plasma)를 이용해 선택적으로 에칭되는 것을 특징으로 하는 제작 방법.
  3. 제2항에 있어서, 에칭되는 샘플의 접지 전극에 음의 바이어스가 인가되고, 그에 의해 상기 비결정질 불화탄소막의 선택적으로 에칭이 실행되는 것을 특징으로 하는 제작 방법.
  4. 제1항, 제2항, 또는 제3항중 한 항에 있어서, 상기 비결정질 불화탄소막이 마스크로 실리콘형 레지스트를 이용해 선택적으로 에칭된 후, 불화수소산을 포함하는 액체가 상기 실리콘형 레지스트를 제거하는데 사용되는 것을 특징으로 하는 제작 방법.
  5. 제1항, 제2항, 또는 제3항중 한 항에 있어서, 상기 비결정질 불화탄소막이 마스크로 실리콘형 레지스트를 이용해 선택적으로 에칭된 후, 상기 실리콘형 레지스트를 제거하는 드라이 에칭(dry etching)이 불소를 포함하는 복합 기체에서 실행되는 것을 특징으로 하는 제작 방법.
  6. 제1항에 있어서, 상기 제작 방법이 최종점 검출 수단으로 상기 비결정질 불화탄소막에 형성된 산화막, 질화막, 및 질산화막 중 하나를 사용함으로서 상기 비결정질 불화탄소막 표면의 비평탄함을 평평하게 하도록 상기 비결정질 불화탄소막의 표면을 폴리싱(polishing)하는 단계를 구비하는 것을 특징으로 하는 제작 방법.
  7. 주성분으로 탄소와 불소를 포함하는 비결정질 불화탄소막을 포함하는 절연막에 의해 배선층이 서로 전기적으로 고립되고, 상기 배선층이 상기 절연막을 통해 침투된 홀(hole)에 묻히는 전도 물질에 의해 전기적으로 연결되는 것을 특징으로 하는 반도체 장치.
  8. 제7항에 있어서, 상기 절연막이 주 성분으로 탄소와 불소를 포함하는 비결정질 불화탄소막과, 상기 비결정질 불화탄소막의 주요 표면에 적어도 형성된 산화실리콘막, 질화실리콘막, 및 질산화실리콘막 중 하나를 구비하는 것을 특징으로 하는 반도체 장치.
  9. 제8항에 있어서, 적어도 상기 비결정질 불화탄소막과 접하는 상기 산화실리콘막, 상기 질화실리콘막, 및 상기 질산화실리콘막 중 하나의 인터페이스 부분의 화학량론 비율이 실리콘에 과도한 것을 특징으로 하는 반도체 장치.
  10. 제8항에 있어서, 상기 산화실리콘막, 상기 질화실리콘막, 및 상기 질산화실리콘막 중 하나와 접하는 상기 비결정질 불화탄소막의 적어도 인터페이스 부분이 수소를 포함하는 것을 특징으로 하는 반도체 장치.
  11. 제7항, 제8항, 제9항 또는 제10항중 한 항에 있어서, 산화실리콘막, 질화실리콘막, 및 질산화실리콘막 중 하나가 상기 절연막을 통해 침투된 상기 홀에서의 측면 표면 중 한 측면 표면에 노출된 상기 비결정질 불화탄소막과의 인터페이스에 적어도 형성되는 것을 특징으로 하는 반도체 장치.
  12. 제11항에 있어서, 상기 비결정질 불화탄소막과 접하는 상기 홀의 측면 표면에 형성된 상기 산화실리콘막, 상기 질화실리콘막, 및 상기 질산화실리콘막 중 하나의 적어도 인터페이스 부분의 화학량론 비율이 실리콘에 과도한 것을 특징으로 하는 반도체 장치.
  13. 제7항에 있어서, 상기 절연막이 주 성분으로 탄소와 불소를 포함하는 비결정질 불화탄소막과, 상기 비결정질 불화탄소막의 상단 표면에 적어도 형성된 산화실리콘막, 질화실리콘막, 및 질산화실리콘막 중 하나를 구비하고, 상기 비결정질 불화탄소막에서의 상기 홀의 개구 단면적이 상기 절연막의 상기 산화실리콘막, 상기 질화실리콘막, 및 상기 질산화실리콘막 중 하나에서의 상기 홀 보다 더 크고, 또한 산화실리콘막, 질화실리콘막, 및 질산화실리콘막 중 하나가 상기 절연막을 통해 침투된 상기 홀의 측면 표면 중 적어도 한 측면 표면에 노출된 상기 비결정질 불화탄소막과의 인터페이스에 형성되는 것을 특징으로 하는 반도체 장치.
  14. 제7항에 있어서, 상기 절연막이 주 성분으로 탄소와 불소를 포함하는 비결정질 불화탄소막과, 상기 비결정질 불화탄소막의 상단 표면에 적어도 형성된 산화실리콘막, 질화실리콘막, 및 질산화실리콘막 중 하나를 구비하고, 산화실리콘막, 질화실리콘막, 및 질산화실리콘막 중 하나가 상기 절연막을 통해 침투된 상기 홀의 측면 표면 중 한 측면 표면에 노출된 상기 비결정질 불화탄소막과의 인터페이스에 적어도 형성되고, 또한 상기 홀의 측면 표면에 형성된 상기 산화실리콘막, 상기 질화실리콘막, 및 상기 질산화실리콘막 중 하나의 두께가 상기 절연막의 산화실리콘막, 상기 질화실리콘막, 및 상기 질산화실리콘막 중 하나 보다 얇은 것을 특징으로 하는 반도체 장치.
KR1019970008129A 1996-03-07 1997-03-07 반도체장치와그의제조방법 KR100308101B1 (ko)

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