KR970003884A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR970003884A
KR970003884A KR1019960022704A KR19960022704A KR970003884A KR 970003884 A KR970003884 A KR 970003884A KR 1019960022704 A KR1019960022704 A KR 1019960022704A KR 19960022704 A KR19960022704 A KR 19960022704A KR 970003884 A KR970003884 A KR 970003884A
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South Korea
Prior art keywords
lead
chip
electrode pad
semiconductor device
offset portion
Prior art date
Application number
KR1019960022704A
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English (en)
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KR100473464B1 (ko
Inventor
에쯔오 야마다
Original Assignee
사와무라 시코
오끼뎅끼 고오교오 가부시끼가이샤
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Publication of KR970003884A publication Critical patent/KR970003884A/ko
Application granted granted Critical
Publication of KR100473464B1 publication Critical patent/KR100473464B1/ko

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

전극 패드(13)가 설치된 IC칩(11)의 표면의 측에서 테두리부 왼쪽에서 전극 패드(13)에 향하여 IC칩 표면에서 간격을 두고 신장하는 리드(12)와 리드(12)를 전극 패드(13)에 접속하는 본딩 와이어(16)를 포함한다. 리드(12)의 전극 패드의 근방 부분에 IC칩의 표면에 향하여 편의하는 오프 셋 부(12C)를 설치하고, 이 오프 셋부(12C) 본딩 와이어(16)를 리드(12)에 접속한다. 리드(12)의 오프셋 본딩 와이어(16)의 정부의 높이 위치의 저감을 도모하는 것이 되어, 반도체 장치(100의 한층의 박형화를 도모하는 것이 가능하게 된다.

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 관련하는 반도체 장치를 부분적으로 표시하는 횡단면도.

Claims (4)

  1. 표면에 전극 패드가 형성된 IC칩과 해당 IC칩의 상기 표면의 측에서 상기 IC칩의 테두리부 외쪽에서 상기 전극 패드에 향하여 상기 표면에서 간격을 두고 신장하는 리드와 해당 리드를 상기 전극 패드에 접속하는 본딩와이어를 포함하는 반도체 장치에 있어서, 상기 리드는 상기 전극 패드의 근방 부분이 상기 IC칩의 상기 표면에 향하여 편의하는 오프 셋 부를 가지고 해당 오프 셋 부에서 상기 본딩 와이어가 상기 리드에 접속되어 있는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 리드는 상기 절연성의 접착 수단을 통하여 상기 IC칩의 테두리 근방 부분에서 상기 표면에 고착되어 있어, 상기 오프 셋 부는 상기 리드의 상기 접착 수단에서 고착된 부분 보다도 상기 IC칩의 중앙부 측에 위치하는 단 부분에 형성되어 있는 것을 특징으로 하는 반도체 장치.
  3. 제2항에 있어서, 상기 전극 패드, 상기 오프 셋 부 및 상기 본딩 와이어는 절연성 수지 재료중에 매설되어 있어 상기 리드의 상기 오프 셋 부를 제거하는 부분의 표면과 상기 절연성 수지 재료의 표면은 거의 동일평면상에 있는 것을 특징으로 하는 반도체 장치.
  4. 제3항에 있어서, 상기 IC칩의 측면 및 이면은 노출되어 있는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960022704A 1995-06-21 1996-06-20 반도체장치 KR100473464B1 (ko)

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JP95-178296 1995-06-21
JP17829695 1995-06-21

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KR100473464B1 KR100473464B1 (ko) 2005-05-17

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283545A (ja) * 1996-04-10 1997-10-31 Oki Electric Ind Co Ltd 樹脂封止型半導体装置及びその製造方法
JP3427874B2 (ja) * 1996-05-16 2003-07-22 沖電気工業株式会社 樹脂封止型半導体装置とその製造方法
JPH10214933A (ja) * 1997-01-29 1998-08-11 Toshiba Corp 半導体装置とその製造方法
JP3638750B2 (ja) * 1997-03-25 2005-04-13 株式会社ルネサステクノロジ 半導体装置
JP3006546B2 (ja) * 1997-06-12 2000-02-07 日本電気株式会社 半導体装置及びリードフレーム
JP3085278B2 (ja) * 1998-05-01 2000-09-04 日本電気株式会社 半導体装置の製造方法および半導体製造装置
JP2001156237A (ja) * 1999-11-25 2001-06-08 Mitsubishi Electric Corp リードフレーム及びそれを用いた樹脂封止型半導体装置
US6664649B2 (en) * 2001-02-28 2003-12-16 Siliconware Precision Industries Co., Ltd. Lead-on-chip type of semiconductor package with embedded heat sink
US7294533B2 (en) * 2003-06-30 2007-11-13 Intel Corporation Mold compound cap in a flip chip multi-matrix array package and process of making same
US7495321B2 (en) 2006-07-24 2009-02-24 Stats Chippac, Ltd. Leaded stacked packages having elevated die paddle
TW200941669A (en) * 2008-03-28 2009-10-01 Powertech Technology Inc Semiconductor packing structure
US9645163B2 (en) 2011-08-24 2017-05-09 Continental Teves Ag & Co. Ohg Sensor with a single electrical carrier means

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854644A (ja) * 1981-09-28 1983-03-31 Nec Corp ボンデイング用樹脂基板
JPS5966157A (ja) * 1982-10-08 1984-04-14 Fujitsu Ltd 半導体装置及びその製造方法
KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
JP2895920B2 (ja) * 1990-06-11 1999-05-31 株式会社日立製作所 半導体装置及びその製造方法
KR100234824B1 (ko) * 1991-03-20 1999-12-15 윌리엄 비. 켐플러 반도체 장치
JPH04320390A (ja) * 1991-04-19 1992-11-11 Hitachi Ltd 表面実装型半導体部品の実装方法
US5221642A (en) * 1991-08-15 1993-06-22 Staktek Corporation Lead-on-chip integrated circuit fabrication method
JP2518569B2 (ja) * 1991-09-19 1996-07-24 三菱電機株式会社 半導体装置
JP2509422B2 (ja) * 1991-10-30 1996-06-19 三菱電機株式会社 半導体装置及びその製造方法
US5229639A (en) * 1991-10-31 1993-07-20 International Business Machines Corporation Low powder distribution inductance lead frame for semiconductor chips
KR940007757Y1 (ko) * 1991-11-14 1994-10-24 금성일렉트론 주식회사 반도체 패키지
JPH05152495A (ja) * 1991-11-26 1993-06-18 Hitachi Ltd 半導体装置
JP3410752B2 (ja) * 1992-04-14 2003-05-26 富士通株式会社 半導体装置及びその製造方法
JPH06132339A (ja) * 1992-10-19 1994-05-13 Mitsubishi Electric Corp 半導体装置
JP2934357B2 (ja) * 1992-10-20 1999-08-16 富士通株式会社 半導体装置
KR100269281B1 (ko) * 1992-12-17 2000-10-16 윤종용 반도체장치
JPH06216282A (ja) * 1993-01-19 1994-08-05 Hitachi Ltd 樹脂封止型半導体装置
JP2810626B2 (ja) * 1994-06-07 1998-10-15 日鉄セミコンダクター株式会社 半導体装置
US5545921A (en) * 1994-11-04 1996-08-13 International Business Machines, Corporation Personalized area leadframe coining or half etching for reduced mechanical stress at device edge

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KR100473464B1 (ko) 2005-05-17
TW314650B (ko) 1997-09-01
EP0750342A2 (en) 1996-12-27
US5874783A (en) 1999-02-23
EP0750342A3 (en) 1997-10-08
EP1396886A2 (en) 2004-03-10
EP1396886A3 (en) 2004-07-07

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