TW314650B - - Google Patents

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Publication number
TW314650B
TW314650B TW085107308A TW85107308A TW314650B TW 314650 B TW314650 B TW 314650B TW 085107308 A TW085107308 A TW 085107308A TW 85107308 A TW85107308 A TW 85107308A TW 314650 B TW314650 B TW 314650B
Authority
TW
Taiwan
Prior art keywords
semiconductor
main surface
wiring
contact pad
semiconductor wafer
Prior art date
Application number
TW085107308A
Other languages
English (en)
Original Assignee
Oki Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Oki Electric Ind Co Ltd filed Critical Oki Electric Ind Co Ltd
Application granted granted Critical
Publication of TW314650B publication Critical patent/TW314650B/zh

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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

經濟部中央榡準局員工消費合作社印裝 °^465〇 A7 五、發明説明(1 ) · 本發明係關於一種半導體元件,包含一片半導體晶 片’在其上面,電子電路係組成積體電路(1C),及一個把 半導體晶片包封到裏面的封裝。 置知技藝之妨诚 封裝的形式是以電絕緣合成樹脂壓模,把半導禮晶 片包封到哀面,具有小體積易於處理的優點。一種運用 在積體電路的合成樹脂封裝習知為薄小外排列封裝 (TSOP)。這薄小外排列封裝包括一片半導體晶片,其具 有一個主要表面,在其上面有接觸墊,而與此表面平行 的腳接線向外延伸,在靠近接觸墊的尾端部位以電絕緣 黏貼條片固定在主要表面上面。以焊接線連接接觸墊和 腳接線。烊接線及腳接線的連接部位係使用一個合成樹 脂封裝,連同整個半導體晶片密封住。構造在半導體晶 片上面的電子電路交互連接到接觸墊上面,其係以烊接 線電連接到腳接線。電子電路最後可以交互連接到和腳 接線耦合的一個應用元件》 上述之半導體元件形式’焊接線接合到接觸塾,其 係構造在半導體晶片的主要表面上面’並且腳接線的尾 端具有一段足夠的長度,使得接觸蟄和腳接線接合的尾 端之間形成一條旅線。腳接線接合的尾端部位距離半導 體晶片的主要表面有一個高度,此高度大致等於黏貼條 片的厚度及腳接線的厚度之和。焊接線成弧形的的部位 本纸張尺度適用中國國家標率(CNS ) A4規格(210X 297公楚) —~~ -4- (請先閲讀背面之注意事項再填寫本頁)
A7 五、發明説明(2 ) 伸展在此高度上。覆蓋住腳接線接合的尾端部位及接觸 墊之合成樹脂封裝部份,必須具有的厚度是比從半導體 晶片的主要表面到孤·線最高點更長的高度·》此條件妨礙 了縮小一個半導體元件的合成樹脂封裝之厚度,以及因 而妨礙製作一個精巧或薄的半導體元件。 發明摘要 因此’本發明之目的為,提供一個半導體元件,其 具有一個薄或扁平的封裝,以包覆住一片半導體晶片。 根據本發明,一個半導體元件含有腳接線,其具有 一個由一片半導體晶片的主要表面支撐住的偏置部位, 在晶片上面電子電路被組成一個積體電路。偏置部位被 置放在靠近用來連接電子電路的接觸墊的位置。腳接線 遠離接觸塾的其餘部位則以電絕緣材料作為襯整和主要 表面隔離。焊接線把腳接線連接到接觸整。 更明確地,根據本發明,一個半導體元件包含:一 片半導體晶片,具有一個主要平坦表面,在其部份的表 面上構造一個積體電路形式的電子電路,及相互電連接 電子電路的接觸墊;腳接線,沿著上述接觸墊到上述半 導體晶片的週邊方向延伸,用來連接上述接觸塾到一個 應用疋件;及焊接線,連接上述腳接線到上述接觸墊; 上述腳接、線,包含-個偏置部位,其由上述半導體晶片 的王要表面支撐住及被置放靠近上述接㈣,上述腳接 線遠離上述接觸墊的一段其餘部位,在垂直於上述半導 體晶片的主要表面的方向和上述半導體晶片的主要表面 w尺度適用中國 CNS) Λ4 規·-__________________ -5- 請 先 閱 面 之 注 意 事 項 再
頁 經 濟 部 k 樣 準 局 % X 消 ★· 合 作 社 印 製
A7 五、發明説明( 經濟部中央標準局員工消费合作社印製 隔離。 BA簡單說明 本發明之目的及特徵可經由參閱圏式所作的詳細描 述而變得更明確,其中: 圖一為本發明半物元件之-較佳IT侧的示意、 部份且為垂直截面視圖; 為一示意、部份且為垂直截面視圖,其與圖一 相似,表示本發明半導體元件之另一實施例; 亦為一示意視圖’表示本發明半導體元件之另 一實施例的部份垂直截面視囷; 為一示意俯視圖’表示發明半導體元件之另一 實施例; 示意圖四之實施例中,沿圖四之刻線A-A部份的 截面。 丝實施例之評诚 參閱圖一’本發明之半導體元件10的一個較佳實施 例,例如可被製作成一個16百萬位元的RAM(隨機存取記 憶體)。半導體元件1〇包括一片半導體晶片U,在其上面 電子電路被組在半導體基質上,而構造成一個薄小外排 列封裝(TSOP)形式的積體電路(iq。半導體元件1〇之俯視 圖的外排列可與圖四所示者類似,但稍有不同》回到圖 一,半導體元件10也含有腳接線12,簡化之故只在圖内 繪出其中的一支。半導體晶片11具有一個大致平坦的主 要表面11A,在其上面構造接觸墊13,用來連接腳接線到 圖 圖 圖四 圖五 本紙張尺度適用中國國家橾準(CNS ) Λ4現格(210Χ 297公釐) -6 - (請先閲讀背面之注意事項再填寫本1) -*" ,1Τ 經濟部中央標準局負工消费合作社印製 314650 A7 B7 五、發明説明(4 ) 内含在積體電路的電子電路。同樣為了簡化,只在圖内 繪出其中的一個接觸墊。除了設置接觸墊13的部位之 外,在晶片11的主要表面11A的部位,以電絕緣及保護層 14覆蓋住,材質為合成樹脂,如聚醢亞胺系列物質,厚 度例如5至15#m。 腳接線12由一條大致拉長的導電材質或金屬條片製 成,且大致從半導體晶片11的邊緣水平朝外延伸出去。 導電的腳接線12宜用彈性的材質製作。如圖一所示,脚 接線12有一個中央部位12A,其係以一條黏貼條片15固定 在主要表面11A上面。黏貼條片15含有一層由合成樹脂物 質’如聚酿亞胺系列製成的薄膜,並且在平坦的反背面 塗有一層黏貼劑,如合成樹脂,例如還氧或聚醯亞胺系 列。黏貼物質宜採用加熱能融化者。腳接線的中央部 位12A因此和保護層14的開放表面隔離,其主要間距等於 黏貼條片15的厚度。腳接線12的中央部位12a因此從接觸 墊13延伸出去’直到晶片u的邊緣。 本發明不限制僅使用黏貼條片15 «替代方式可運用 液態的黏貼劑,將其加熱後凝固。腳接線12的中央部位 12A宜沿著垂直於由半導體晶片u的主要表面nA所形成 的水平面方向,從保護層14的上表面以一個與電容有關 的預設間距隔開。就此意義,所述之黏貼條片15之型式 更為合適。 腳接線12另有一個部位ub ,從中央部位12A延續到 接觸塾η。如圖-料騎,部位版從黏貼條片15的内 (請先閲讀背面之注意事項再填寫本頁) -装. 訂 B7 五、發明説明(5 ) 緣沿伸,並在圖中向下弩曲或成曲形。由於部位12B這個 特別高起的形貌,就將之稱為一個步階部位。 雉續從腳接線12延續是一個偏置部位12C,其與絕緣 保護層14的部份平坦表面接觸,且其尾端終止於接觸整 13的前面,保持某個間距。偏置部位12C的偏置或移位是 對應到保護層14的開放表面的隔離大小,亦即黏貼條片 15的厚度》基於此事實’及因為導電的腳接線12具有彈 性’偏置部位12C在囷中朝下偏移,而中央部位12A的下 表面以黏貼條片15支撐在保護層14上面,而得以被擠壓 朝向絕緣保護廣14的上表面。絕緣保護層14作用為解除 或吸收由部位12B及12C的偏移所產生的壓力,及當焊接 線16 ’稍後將述及,被接附在偏置部位12C所施加的撞 擊,如此保護晶片11的主要表面免受損害。在偏置部位 12C的上表面鍍上銀,而形成一個銀層17。 腳接線12以烊接線16搞連到接觸整13,而在兩者之 間形成電連接》焊接線16有一端被連附在腳接線12的偏 置部位12C,其係以一個銀層17覆蓋。銀層17宜作為例如 使用超音波把焊接線16—端熱壓黏附到偏置部位He。烊 接線16有另一端被核連到接觸整13。 半導體晶片11的整個構造,其上面承載積體電路與 接觸墊13,連同腳接線12的部位12β和部位12C,及烊接 線16,如圖所示,係以一個模壓的封裝18包裹密封住。 封裝18宜使用電絕緣合成樹脂或塑膠材料製作,如還氧 系列,包括纖維矽化物,其具有例如約6〇_1〇〇以m的厚 I紙伕尺度適用t國國家標i^(CNS)糾仏(2|0><297公4)------_______ A7 B7 册· 6. U補先 ---- 五、發明説明(6 ) - t * - (請先閲讀背面之注意事項再填寫本頁) 度。一般而言,封裝18宜使用上下鑄模來壓模,未圖 示’這兩塊鑄模是相向緊靠在一起。在模壓的過程中, 兩塊鑄模相向緊壓而堅實地形成模壓的封裝18。黏貼條 片15,係設置在絕緣保護層14上,作用為吸收及緩衝在 模麼的過程中加在半導體晶片11的壓力和撞擊,否則可 能造成晶片的傷害或裂開。 另外,本發明也可應用其他形態的封裝,如陶瓷形 態的封裝和金屬形態的封裝,其内部被構成一個空腔, 以包裹住半導體晶片11及相關的組件。 - 腳接線12有另外的尾端部位12D,其由封裝18的週邊 向外延伸。腳接線12的尾端或接腳部位12D最後可以耗連 到一個應用元件,而一般在圖中是向下彎曲。為了便於 連接尾端部位12D ’由封裝18延伸出的尾端部位12D係以 金電鍍,而形成一層金層19。包含在半導體元件1〇的電 子電路則經由腳接線12、烊接線16及接觸塾13被搞連到 一個應用元件。 經濟部中央標準局貝工消費合作社印裝 如上根據圖一所示及解說的實施例,半導體元件1〇 具有焊接線16搞連到腳接線12的偏置部位12C。如先前所 述’腳接線12的偏置部位12C移位或從中央部位12A的水 平’朝向覆蓋住晶片11的主要表面11A的保護層14,以一 個高度偏移,高度大小和黏貼條片15的厚度相當。這樣 導致偏置部位12C的高度降低。 更特別指明,如圖一所示,’焊接線16具足夠的長 度’以在接觸墊13和腳接線12的偏置部位12c之間形成一 本紙張又度逋用中國國家標準(CNS ) A4規格(210X297公釐) -9- 經濟部中央標準局員工消費合作社印製 A7 __ B7 五、發明説明(7 ) 條恭線。·焊接線16的狐形部位之最高點因而即被降低一 個對應於黏貼條片15厚度的間距。如圖所示,焊接線16 弧線部位的最高點比腳接線12中央部位12A的上表面為 低,例如在保護層14的上表面大約0 225-0.25毫米的高 度》合成樹脂封裝18的上部位,係完全覆蓋住腳接線12 的中央部位12A和焊接線16,具有厚度η,其比在習知元 件内’從構造在半導體晶片11的保護層14的上表面算起 的弧線最高點的高度,是比中央部位12八的上表面的高度 有足夠大的長度。封裝18的上部位的厚度η與習知技藝比 較是大幅度被減小,因此封裝18的厚度τ隨之被縮減到約 一毫米。如此,達成一個更薄及扁平的半導髏元件1〇。 另外的方式為,偏置部位12C可以被定位在其他的地 方’例如在腳接線12中央部位12Α »然而,囷一之實施例 更為合宜,因為偏置部位12C係設置在腳接線12的末端部 位,靠近接觸塾13,也作為一個烊接塾之用’其更宜位 在接觸鳌13的附近,如此可以比設在腳接線長度的中 央更為縮短烊接線16的長度。偏置部位12C設在接線12的 末端而靠近塾13的方式也有利於封裝18所需材質的最小 參閱圖二,半導嫌元件10係根據本發明之另一實施 例,與圖一所示及說明相似,不同處在於,另一個主要 表面,或背面,11Β被暴露在大氣中,以強化由結合在元 件10内的積體電路所產生的熱量輻射。圖中,相同的組 件,以囷一所示之圖號表示。 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X297公釐) -10 - ----------衣------訂--*-----1 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標孪局Μ工消費合作社印製 A7 ___ B7 五、發明説明(8 ) 一般而言,在這型暴露半導體晶片背面的半導體元 件,合成樹脂封裝常有一層由模具擠出多餘的模壓物質 而產生的發亮層。這種發亮層常會降低輻射發散由積體 電路產生的多餘熱量的效率。 如圖二所示之實施例,合成樹脂封裝18包含一個上 半部18A,其在水平面的區域宜比半導體晶片η的主要表 面11A為小,以在壓’避免構成封裝上半部18A的塑膠材 料多餘的部份從背面11B的模具擴散過來。 另外,黏貼條片15從半導體晶片η的邊緣lie朝外延 伸或突出,或平躺,如圖所示。黏貼條片15是被加熱並 固定在保護層14上面,因而條片15的延伸部位被一條筋 排20黏住’其係由塗在條片15上的黏著劑之一部份形 成,並在被加熱時溢流出,以封住條片的背面15A和晶片 11的垂直邊11C之間的界面。筋排20也可作為防止晶片11 的邊緣部位11C破裂,其係由在完成半導體元件1〇後,測 試加諸的週期性溫度變化所導致。晶片11的周邊部位18B 以合成樹脂材料18B覆蓋,而形成封裝18。 如上述’圖二之實施例具有暴露在空氣中的背面 11B ’以提升由元件1〇内的積體電路所產生的熱量的輻 射。背面不以一層合成樹脂覆蓋,因此適合縮小封裝18 的整個厚度,及達成一個更薄及扁平的半導體元件。 參閱囷三,根據本發明另一實施例之半導體元件 1〇 ’係與囷二所示及說明相似,不同處在於,晶片^的 邊緣表面11C也是暴露在周圍的大氣,而不被封裝18的部 本紙張尺度適用中@國家縣(CNS) Λ4規格(21()>< 297公楚) ~ (請先閱讀背面之注意事項再填寫本頁) 訂--1. -11- 經濟部中央標準局負工消費合作社印袈 A7 B7 五、發明説明(9 ) 位所覆蓋,及封裝的半部18B有一個大致平坦的上表面 18C ’實際是位在與腳接線12中央部位12A的上表面相同 的水平上。未蓋住的表面11C,及同樣未蓋住的背面 11B ’係作為輻射發散一部份由被包含在元件10内的電子 電路所產生的熱量之用。 另外,封裝的半部18B的上表面18C實際是位在與腳 接線12中央部位12A的上表面相同的水平上》當然,步階 部位12B、與步階部位12B連接在一起的偏置部位12C、 焊接線16及接觸墊13,皆仍維持埋入在封裝18的合成樹 脂層内。這個結構允許半導體元件10的厚度T能被更加缩 小’以達成一個精小元件。 參閱圖四,仍是根據本發明的半導體元件之另一實 施例’與圖一、圖二及囷三所示及說明相似’不同處在 於’腳接線12缺少對應於尾端或接腳部位12D。腳接線12 的結構可由圖五而清楚理解。圖四及圖五之實施例1〇具 有腳接線12的中央部位12A,其係露出在封裝18外,並且 對準在雙排線上。腳接線12的鍍金層19的裸露表面係直 接用來耦連到一個應用元件’例如以碰撞型的接觸整來 搞合。 在圖四及圖五所示之實施例中,背面及邊緣表面11B 和11C因此不覆蓋,且露出在大氣中,其功能為輻射大部 份由含在元件10内的電子電路所產生的熱量。另外,腳 接線12被省略的部位’即為接腳部位12D向下延伸低於晶 片11的主要表面的水平,允許半導體元件10變得更薄, 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) -12· ------Γ-----^-士衣-- (請先閲讀背面之注意事項再填寫本頁)
.IT 經濟部中央標準局員工消费合作社印製 A7 _____ _B7 五、發明説明(10 ) 〜 以製得一個超薄的半導體元件,其厚度例如小於〇5 米。 、·毫 本發明雖然係參閱圖示之實施例加以說明,但不限 於這些實施例。值得一提的是,熟悉該項技術者能改變 或更動這些實施例的構造,但不偏離本發明的範疇及基 本原則。 本紙張尺度適用中國國家樣率(CNS ) A4規格(210X 297公釐) -13- f請先gf背面之注意事項再填寫本頁)

Claims (1)

  1. ABCD <>14650 申請專利範圍 1. 一種半導體元件,包含: 一片半導體晶片,具有一個主要平坦表面,在其部份的 表面上構造一個積體電路形式的電子電路,及相互電連 接電子電路的接觸墊; 腳接線,沿著上述接觸墊到上述半導體晶片的週邊方向 延伸,用來連接上述接觸墊到一個應用元件; 及烊接線,連接上述腳接線到上述接觸墊; 上述腳接線,包含一個偏置部位,其由上述半導體晶片 的主要表面支撐住及被置放靠近上述接觸墊,上述腳接 線遠離上述接觸墊的一段其餘部位,在垂直於上述半導 體晶片的主要表面的方向和上述半導體晶片的主要表面 隔離》 2. 根據申請專利範園第1項所述之半導體元件,另外‘含 由電絕緣材料製作的支撐組件,以在上述半導體晶片的 主要表面上面支撐上述腳接線; 上述支撐組件被置放在從上述接觸墊向外延伸出的方 向,而把上述偏置部位定位在上述接觸墊與上述支撐組 件之間,以構成上述腳接線的一個尾端。 3. 根據申請專利範園第2項所述之半導體元件,其中,上 述支撐組件是成一條條片的形式,在其平坦背面上塗上 一種膠黏劑》 4. 根據申請專利範園第丨項所述之半導體元件,另外包含 一個由電絕緣材料製作的封裝,以包裹膠封住上述半導 體晶片、上述接觸墊、上述腳接線的偏置部位及上述坪 、紙張尺度適用中國國家標準(CNS ) A4現格(210X297公釐) -14- (請先閲讀背面之注意事項再填寫本頁) 、1T 經濟部中央標率局员工消費合作社印製
    接線的至少一些部位β 經濟部中央標準局負工消费合作社印製
    5·根據申請專利範固第4項所述之半導體元件,其中,上 逑封裝具有-個大致平坦的表面,其係沿著垂直於上述 半導體晶片的主要表面的方向,位在上述腳接線剩餘部 位的一個上表面的水平之上。 6. 根據申請專利範園第4項所述之半導體元件,其中,上 述焊接線在垂直於上述半導體晶片的主要表面的方向具 有厂個頂點,頂點餘著垂直主要表面的方向,不位在 上述腳接線剩餘部位的一個上表面的水平之上。 7. 根據申請專利範固第6項所述之半導體元件,其中,上 述封裝具有—個大致平坦的表面,其絲著垂直於上述 半導體晶片的主要表面的方向,實際位在與上述腳接線 剩餘部位的一個上表面同樣的水平高度。 8. 根據申請專利範固第4項所述之半導體元件,其中,上 述半導體晶片具有-個背面,其係位於主要表面的反 面’從上述封裝暴露到大氣之中。 9. 根據申請專利範圍第4項所述之半導體元件,其中,上 述半導體晶片具有一個邊緣表面,其從上述射裝暴露到 大氣之中。 10. 根據申請專利範圍第1項所述之半導體元件,另外包含 一層由電絕緣材料製作的保護層,且形成在上述半導 雜晶片的主要表面上面; 上述腳接線的偏置部位被支揮在上述保護層上面。 11·根據申請專利範圍第1項所述之半導體元件,其中,上 本紙張尺度適用中國國家標準(CNS > Α4規格(210Χ297公釐) ' -- -15- Α8 Β8 C8 D8 申請專利耗圍 述脚接線具有-個步階部位,其從偏置部位延續過來 以偏移偏置部位,其係以逆向頂住半導禮晶片的主要 表面。 12.根據巾請柄範gj糾項·之半導體元件,其中, 上述腳接線是由一種彈性材料製作。 1丄根據巾請柄範圍幻衝狀半賴元件,其中,上 述腳接線具有一個接腳部位,以連接到應用元件3 14.根據申請專利範圍第4項所述之半導體元件,其中,上 述半導雜元件是屬於薄小外排列封裝(TS〇p)的形式。 (請先聞讀背面之注意事項再填寫本頁) -訂 -1*. 經濟部中央標準局員工消費合作社印製 本纸張尺度逋用中國國家榡準(CNS ) A4賴放ί 鮝) -16-
TW085107308A 1995-06-21 1996-06-17 TW314650B (zh)

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283545A (ja) * 1996-04-10 1997-10-31 Oki Electric Ind Co Ltd 樹脂封止型半導体装置及びその製造方法
JP3427874B2 (ja) * 1996-05-16 2003-07-22 沖電気工業株式会社 樹脂封止型半導体装置とその製造方法
JPH10214933A (ja) * 1997-01-29 1998-08-11 Toshiba Corp 半導体装置とその製造方法
JP3638750B2 (ja) * 1997-03-25 2005-04-13 株式会社ルネサステクノロジ 半導体装置
JP3006546B2 (ja) 1997-06-12 2000-02-07 日本電気株式会社 半導体装置及びリードフレーム
JP3085278B2 (ja) * 1998-05-01 2000-09-04 日本電気株式会社 半導体装置の製造方法および半導体製造装置
JP2001156237A (ja) * 1999-11-25 2001-06-08 Mitsubishi Electric Corp リードフレーム及びそれを用いた樹脂封止型半導体装置
US6664649B2 (en) * 2001-02-28 2003-12-16 Siliconware Precision Industries Co., Ltd. Lead-on-chip type of semiconductor package with embedded heat sink
US7294533B2 (en) * 2003-06-30 2007-11-13 Intel Corporation Mold compound cap in a flip chip multi-matrix array package and process of making same
US7495321B2 (en) * 2006-07-24 2009-02-24 Stats Chippac, Ltd. Leaded stacked packages having elevated die paddle
TW200941669A (en) * 2008-03-28 2009-10-01 Powertech Technology Inc Semiconductor packing structure
CN107954393B (zh) 2011-08-24 2021-06-22 大陆-特韦斯贸易合伙股份公司及两合公司 具有唯一的电支承件的传感器

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854644A (ja) * 1981-09-28 1983-03-31 Nec Corp ボンデイング用樹脂基板
JPS5966157A (ja) * 1982-10-08 1984-04-14 Fujitsu Ltd 半導体装置及びその製造方法
KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
JP2895920B2 (ja) * 1990-06-11 1999-05-31 株式会社日立製作所 半導体装置及びその製造方法
KR100234824B1 (ko) * 1991-03-20 1999-12-15 윌리엄 비. 켐플러 반도체 장치
JPH04320390A (ja) * 1991-04-19 1992-11-11 Hitachi Ltd 表面実装型半導体部品の実装方法
US5221642A (en) * 1991-08-15 1993-06-22 Staktek Corporation Lead-on-chip integrated circuit fabrication method
JP2518569B2 (ja) * 1991-09-19 1996-07-24 三菱電機株式会社 半導体装置
JP2509422B2 (ja) * 1991-10-30 1996-06-19 三菱電機株式会社 半導体装置及びその製造方法
US5229639A (en) * 1991-10-31 1993-07-20 International Business Machines Corporation Low powder distribution inductance lead frame for semiconductor chips
KR940007757Y1 (ko) * 1991-11-14 1994-10-24 금성일렉트론 주식회사 반도체 패키지
JPH05152495A (ja) * 1991-11-26 1993-06-18 Hitachi Ltd 半導体装置
JP3410752B2 (ja) * 1992-04-14 2003-05-26 富士通株式会社 半導体装置及びその製造方法
JPH06132339A (ja) * 1992-10-19 1994-05-13 Mitsubishi Electric Corp 半導体装置
JP2934357B2 (ja) * 1992-10-20 1999-08-16 富士通株式会社 半導体装置
KR100269281B1 (ko) * 1992-12-17 2000-10-16 윤종용 반도체장치
JPH06216282A (ja) * 1993-01-19 1994-08-05 Hitachi Ltd 樹脂封止型半導体装置
JP2810626B2 (ja) * 1994-06-07 1998-10-15 日鉄セミコンダクター株式会社 半導体装置
US5545921A (en) * 1994-11-04 1996-08-13 International Business Machines, Corporation Personalized area leadframe coining or half etching for reduced mechanical stress at device edge

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