KR950701769A - 반도체 장치(Semiconductor device) - Google Patents

반도체 장치(Semiconductor device)

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Publication number
KR950701769A
KR950701769A KR1019940704091A KR19940704091A KR950701769A KR 950701769 A KR950701769 A KR 950701769A KR 1019940704091 A KR1019940704091 A KR 1019940704091A KR 19940704091 A KR19940704091 A KR 19940704091A KR 950701769 A KR950701769 A KR 950701769A
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semiconductor chip
circuit board
semiconductor device
overlapping
hole
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KR1019940704091A
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KR100296834B1 (ko
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요시다까 이이지마
시게아끼 세끼
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야스가와 히데아끼
세이꼬 엡슨 가부시끼가이샤
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Publication of KR100296834B1 publication Critical patent/KR100296834B1/ko

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Abstract

절연성의 가요성 기재(21)를 구비하는 회로기판(2)에 대해서는 그 디바이스 홀(23)에 반도체 칩(3)이 배치되어 있다.
반도체 칩(3)의 범프(31)는 도체 패턴(22)중에 디바이스 홀(23)내로 돌출하는 리드부분(221)에 싱글 포인트 본딩법에 의해 접합되어 있다. 회로 기판(2)에는 디바이스 홀(23)의 네모서리부분에 반도체 칩(3)과 겹쳐 합쳐지는 기재(21)의 중첩부(211)를 가지는 동시에 디바이스 홀(23)을 4개의 구멍(231 내지 234)으로 분할하는 중첩부(212)도 가진다. 이들 중첩부(211,212)와 겹쳐지는 반도체 칩(2)의 면상에는 도체 패턴(22)과 접합되지 않고 회로기판(2)과 반도체 칩(3) 사이에 개재하여 거기에서 소정의 간극을 확보하는 더미 범프(32)를 갖는다. 또한, 중첩부(212)에는 구벙(231 내지 234)에서 몰드재를 주입한 때에 공기를 빼기 위한 관통 구멍(230)이 형성되어 있다.

Description

반도체 장치(Semiconductor device)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체 장치의 구성을 도시하는 평면도,
제2A도는 제1도의 I-Ⅱ선을 따라 취한 종단면도,
제2A도는 제1도의 I-Ⅲ선을 따라 취한 종단면도,
제3A도는 본 발명의 제1실시예에 따른 반도체 장치의 구조를 본딩전의 상태에서 모식적으로 도시하는 종단면도,
제3B도는 본 발명의 제1실시예에 다른 반도체 장치의 구조를 본딩후의 상태에서 모식적으로 도시하는 종단면도.

Claims (11)

  1. 절연성의 기재에 도체 패턴이 형성된 회로 기판과, 이 회로 기판의 디바이스 홀에 배치된 반도체 칩을 가지며, 상기 도체 패턴중에서 상기 디바이스 홀내로 돌출하는 리드부분과 상기 반도체 칩의 범프가 접합되어 있는 반도체 장치에 있어서, 상기 회로기판은 상기 반도체 칩과 겹쳐 합쳐지는 중첩부를 가지고, 이 중첩부및 그것과 겹쳐지는 상기 반도체 칩면상의 적어도 한쪽측에는 상기 리드부분과 상기 범프의 접합 공정 전후에 두께가 변화하지 않는 스페이서부가 형성되고, 이 스페이서부가 상기 회로 기판과 상기 반도체 칩과의 사이에 개재하여 거기에 소정의 간극을 확보할 수 있는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 스페이서부는 상기 중첩부가 겹쳐지는 상기 반도체 칩의 면상에서 상기 도체 패턴과 접합되지 않고, 상기 회로기판과 상기 반도체 칩과의 사이에 개재하여 거기에서 소정의 간극을 확보하는 더미 범프인 것을 특징으로 하는 반도체 장치.
  3. 제2항에 있어서, 상기 중첩부에는 상기 도체 패턴이 상기 더미 범프에 겹쳐지고 있는 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 상기 스페이서부는 상기 중첩부측에서 상기 접합용 전극과 접합되지 않고, 상기 회로기판과 상기 반도체 칩과의 사이에 개재하여 거기에서 소정의 간극을 확보하는 상기 도체 패턴의 돌기인 것을 특징으로 하는 반도체 장치.
  5. 제4항에 있어서, 상기 반도체 칩은 상기 접합용 전극으로서의 범프를 가지고, 상기 돌기와 겹쳐지는 위치에는 그것과 접합하지 않는 더미 범프를 가지는 것을 특징으로 하는 반도체 장치.
  6. 제4항에 있어서, 상기 반도체 칩은 상기 접합용 전극으로서의 패드를 가지고, 상기 돌기와 겹쳐지는 위치에는 그것과 접합하지 않는 더미 패드를 가지는 것을 특징으로 하는 반도체 장치.
  7. 제1항 내지 제6항중 어느 한 항에 있어서, 상기 디바이스 홀은 대략 사각형의 윤곽을 가지고 그 네모서리에 상기 중첩부가 있는 것을 특징으로 하는 반도체 장치.
  8. 제7항에 있어서, 상기 중첩부는 상기 디바이스 홀의 각 변부분에도 있는 것을 특징으로 하는 반도체 장치.
  9. 제1항 내지 제8항중 어느 한 항에 있어서, 상기 중첩부는 상기 디바이스 홀 내측에 까지 형성되어 상기 디바이스 홀을 복수의 구멍으로 분할하고 있는 것을 특징으로 하는 반도체 장치.
  10. 제9항에 있어서, 상기 중첩부는 상기 디바이스 홀의 대략 중심 위치를 관통하고, 상기 디바이스 홀을 복수의 구멍으로 분할해두며, 그 중심 위치에 대응하는 부분에는 상기 중첩부에 관통 구멍이 형성되어 있는 것을 특징으로 하는 반도체 장치.
  11. 제9항 또는 제10항에 있어서, 상기 도체 패턴은 상기 구멍을 횡절단하는 크로스 오버부를 갖는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940704091A 1993-04-08 1994-04-04 반도체장치 KR100296834B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP93-82207 1993-04-08
JP08220793A JP3269171B2 (ja) 1993-04-08 1993-04-08 半導体装置およびそれを有した時計
PCT/JP1994/000551 WO1994024698A1 (en) 1993-04-08 1994-04-04 Semiconductor device

Publications (2)

Publication Number Publication Date
KR950701769A true KR950701769A (ko) 1995-04-28
KR100296834B1 KR100296834B1 (ko) 2001-10-24

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EP0645806B1 (en) 2004-02-11
CN1047470C (zh) 1999-12-15
TW301793B (ko) 1997-04-01
KR100296834B1 (ko) 2001-10-24
JP3269171B2 (ja) 2002-03-25
JPH06295939A (ja) 1994-10-21
DE69433543D1 (de) 2004-03-18
US5563445A (en) 1996-10-08
HK1014612A1 (en) 1999-09-30
DE69433543T2 (de) 2004-12-23
WO1994024698A1 (en) 1994-10-27
EP0645806A4 (en) 1995-10-11
EP0645806A1 (en) 1995-03-29
CN1104415A (zh) 1995-06-28

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