WO1994024698A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- WO1994024698A1 WO1994024698A1 PCT/JP1994/000551 JP9400551W WO9424698A1 WO 1994024698 A1 WO1994024698 A1 WO 1994024698A1 JP 9400551 W JP9400551 W JP 9400551W WO 9424698 A1 WO9424698 A1 WO 9424698A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor chip
- overlapping
- semiconductor device
- bump
- circuit board
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 183
- 239000004020 conductor Substances 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 35
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 238000005304 joining Methods 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000012778 molding material Substances 0.000 description 19
- 230000008569 process Effects 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/45644—Gold (Au) as principal constituent
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- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions
- the present invention relates to a semiconductor device, and more particularly, to a structure suitable for mounting a semiconductor chip having a relatively large chip size and a structure suitable for mounting a semiconductor chip on a flexible substrate frequently used in a quartz watch or the like.
- the present invention relates to a semiconductor device provided. Background art
- a trap which is electrically insulated from the internal circuit is provided on the semiconductor chip 54 side.
- a method of increasing the bonding strength between the semiconductor chip 54 and the circuit board 52 can be considered by providing overuse bumps and making the bonding portions as small as the number of bumps.
- forming the bumps requires forming processing on them as well.
- a solder bump 62 formed on a semiconductor chip 61 is heated while applying pressure to the solder bump 62.
- the solder bumps 62 and the conductor patterns 64 of the circuit board 63 are joined.
- the circuit board 63 has a portion that overlaps with the active surface of the conductor chip 61, the conductor pattern 64 can be formed also in this overlap portion. Therefore, since the degree of freedom in pattern design is high, it is suitable for thinning semiconductor devices.
- the manufacturing process of the solder bump 62 is complicated, there is a problem that the manufacturing cost is high.
- solder bumps 62 In such a mounting structure using the solder bumps 62, in order to prevent a short circuit between the circuit board 63 and the semiconductor chip 61, the force for thickening the solder bumps 62, Or a method of forming a blank solder bump is conceivable. You. However, as long as solder bumps are used, there are manufacturing problems described above.
- the present invention provides a circuit board having a conductor pattern formed on an insulating base material, and a semiconductor chip disposed in a device hole of the circuit board.
- a semiconductor device in which a lead portion protruding into a device hole and a bump of a semiconductor chip are joined, a superimposed portion overlapping with the semiconductor chip is formed on a circuit board.
- a spacer portion On the side of the overlapping portion or on the surface of the semiconductor chip overlapping therewith, a spacer portion whose thickness does not change before and after the bonding step between the conductor pattern and the bump is formed.
- the semiconductor device is characterized in that the semiconductor portion is interposed between the circuit board and the semiconductor chip and a predetermined gap is secured there.
- a spacer portion that is not bonded to the conductor pattern but is interposed between the circuit board and the semiconductor chip to secure a predetermined gap.
- the gap between the circuit board and the semiconductor chip is automatically secured by the thick bump which is not crushed by the joining process but remains thick. There is no short between the edge and the conductor pattern. Therefore, single point bonding Even when the method or the gear bonding method is used, it is not necessary to form the lead portion. Also, there is no need to use solder bumps that are difficult to reduce cost. Therefore, a semiconductor device which has higher reliability than conventional semiconductor devices and can achieve a reduction in thickness and cost can be realized.
- the size of the gap is determined by the initial thickness of the spacer portion such as a dummy bump set in advance, the reliability is high.
- the dummy bump can be formed simultaneously with the bonding bump, the cost of the semiconductor chip does not increase.
- dummy means that it is unnecessary in an electric circuit, and that the above-mentioned dummy bump or a later-described dummy pad is electrically insulated from a circuit in a semiconductor chip.
- a bump means a thick electrode protruding from an active surface of a semiconductor chip or the like, and a pad means an electrode which does not protrude from an active surface of the semiconductor chip.
- unnecessary conductor patterns on the circuit board that are not required to be connected to other electric circuits and that are unnecessary on the electric circuit may be used as spacers. It can be.
- the conductor pattern overlaps the dummy bump in the overlapping portion. This is because the gap between the semiconductor chip edge and the conductor pattern can be more reliably secured if the dummy bump overlaps the conductor pattern itself.
- a predetermined gap is provided between the circuit board and the semiconductor chip without being bonded to the bonding electrode at the overlapping portion of the circuit board overlapping with the semiconductor chip. It is characterized in that the projection of the conductor pattern as a spacer part is formed. Even in this case, the gap between the circuit board and the semiconductor chip is automatically secured by the projection of the conductor pattern which is not crushed by the joining process but is initially thick. Therefore, even when the single point bonding method or the gear bonding method is used, the forming process is not required.
- a bump as a bonding electrode is formed on the side of the semiconductor chip, and a dummy bump not bonded to the bump is formed at a position overlapping the protrusion. This is because the dimension of the gap can be expanded by a dimension corresponding to the thickness of the bump.
- a pad as a bonding electrode may be formed on the side of the semiconductor chip, and a dummy pad which is not bonded to the projection may be formed at a position overlapping the protrusion.
- the device hole has a substantially quadrangular outline
- an overlapping portion is formed at the four corners. Further, it is preferable that the overlapping portion is formed on each side portion of the device hole. This is because a gap can be secured between the circuit board and the semiconductor chip in a stable state.
- the overlapping portion is formed to the inside of the device hole, and the device hole is divided into a plurality of holes by the overlapping portion. This is because when the molding material is injected into the device hole, the molding material can be spread easily if it is injected from each hole.
- the overlapping portion is divided into a plurality of holes through the approximate center position of the device hole, and a through hole is formed in the overlapping portion at a portion corresponding to the approximate center position. It is preferable to form it. This is because air can escape from the through holes when the molding material is injected.
- the device hole is divided into multiple holes, it is possible to form a conductor pattern with a crossover section that crosses the hole even when wiring is performed on the active surface side of the semiconductor chip. You.
- Such a cross bar portion is supported by the overlapping portion and is in a reinforced state, and therefore has high strength. Therefore, freedom of wiring pattern design is maintained while maintaining high reliability. The degree can be increased.
- FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention.
- FIG. 1 A first figure.
- FIG. 2A is a longitudinal sectional view taken along the line I-II in FIG. 1
- FIG. 2B is a longitudinal sectional view taken along the line I-111 in FIG.
- FIG. 3A is a longitudinal sectional view schematically showing the structure of the semiconductor device according to the first embodiment of the present invention before the soldering
- FIG. 3 is a first embodiment of the present invention
- FIG. 4 is a longitudinal sectional view schematically showing a structure of a semiconductor device according to an example in a state after bonding.
- FIG. 4A is a longitudinal sectional view schematically showing a structure of a semiconductor device according to a second embodiment of the present invention before bonding
- FIG. FIG. 4 is a longitudinal sectional view schematically showing the structure of the semiconductor device according to the second embodiment in a state after bonding.
- FIG. 5A is a longitudinal sectional view schematically showing the structure of a semiconductor device according to a third embodiment of the present invention before bonding
- FIGS. 5A and 5B show the third embodiment of the present invention
- FIG. 1 is a longitudinal sectional view schematically showing the structure of a semiconductor device according to an example in a state after bonding.
- FIG. 6 is a cross-sectional view schematically showing a bonding process using a gang bonding method in a semiconductor device according to a first embodiment as another embodiment of the present invention.
- FIG. 7 is a longitudinal sectional view showing the configuration of a conventional semiconductor device.
- FIG. 8 is a longitudinal sectional view showing the configuration of another conventional semiconductor device. BEST MODE FOR CARRYING OUT THE INVENTION
- BEST MODE FOR CARRYING OUT THE INVENTION a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
- FIG. 1 is a plan view showing the configuration of a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 (a) is a longitudinal sectional view taken along the line I-II
- FIG. 3 is a vertical sectional view taken along line I-III.
- the semiconductor device 1 of the present example is a device used as a circuit block of an analog multifunction electronic timepiece, and includes a circuit board 2 and a CPU. And a semiconductor chip 3.
- the active surface 30 of the semiconductor chip 3 has a size of about 5 mm ⁇ about 5 mm, and is formed with 36 bumps 31 which require bonding.
- a semiconductor chip used in a quartz watch has a size of about 2 mm ⁇ about 2 mm and the number of bumps is about 10 or more, so the semiconductor chip 3 in this example is a normal semiconductor chip. It has about 6 times the area and has more than twice the bonding area.
- the circuit board 2 includes a flexible base material 21 made of a polyimide resin tape material having a thickness of about 130, and a conductor pattern 22 (bonded to the base material 21). Line).
- the conductor pattern 22 is a conductive member in which a copper foil adhered to the base material 21 is formed in a predetermined pattern, and the surface thereof is provided with a metal plating having a thickness of about 1 / m. It has been.
- a portion of the base material 21 corresponding to the arrangement position of the semiconductor chip 3 is removed to form a device hole 23 having a rectangular outline.
- the semiconductor chip 3 is arranged and fixed to the device hole 23.
- the fixing structure includes a lead portion 221, which protrudes inside the device hole 23 of the conductor pattern 22, and a semiconductor chip.
- the structure is such that the bumps 31 of the chip 3 are joined one by one by a single point bonding method, and then the molding material 4 is filled inside the device holes 23.
- the width of the lead portion 22 1 is narrower than the width of the other conductor pattern 22, which facilitates bonding with the bump 31.
- the bump 31 is crushed and thinned at the time of joining with the lead portion 221, and the side of the lead portion 21 is slightly bent downward.
- the four corner regions A, B, C, and D of the device hole 23 are provided with the circuit board 2 overlapping the corners of the semiconductor chip 3.
- a superimposed portion 2 1 1 is formed.
- Dummy bumps 32 a spacer portions are formed at four positions on the active surface 30 of the semiconductor chip 3 overlapping with the superimposed portion 2 11.
- the Damino pump 32 a overlaps with the extended portion 20 of the conductor pattern 2 whose width is increased. This is to ensure that even if the position of the semiconductor chip 3 is slightly displaced, the dummy bump 32 a is overlapped with the conductor pattern 2.
- the dummy bump 32 a since the dummy bump 32 a is not electrically connected to any circuit inside the semiconductor chip 3, it does not cause a malfunction of the semiconductor device 1.
- the dummy bump 3 2 a overlaps the conductor pattern 2 (lead portion 2 2 1), but is not bonded, so the dummy bump 3 2 a differs from the bump 31. It is not crushed and the initial thickness is maintained.
- a superimposed portion 211 of the circuit board 2 overlapping the semiconductor chip 3 is also formed inside the device hole 23.
- the superimposed portion 2 12 passes through substantially the center of the device hole 23 and is in contact with the approximate center of each of the four sides.
- Dummy bumps 33b spacer portions are formed at four places on the active surface 30 of the semiconductor chip 3 overlapping with the superimposed portion 212.
- the dummy bumps 33 b are also formed inside the semiconductor chip 3. Are not electrically connected to any of the circuits. Also, since the dummy bump 33b is not bonded to the conductor pattern 22 (lead portion 2211), unlike the bump 31 it is not crushed and the initial thickness is maintained. Have been.
- the dimension of the gap t 1 is set to the predetermined value of the dummy bump 3 2. Is determined by the initial thickness dimension of Further, since the dummy bumps 32 overlap the conductor patterns 22, a gap t 1 is reliably secured between the conductor patterns 22 and the semiconductor chip 3. Therefore, the semiconductor device 1 has high reliability. In addition, since the dummy bumps 32 can be formed simultaneously with the bonding bumps 31, the cost of the semiconductor chip 3 does not increase.
- the active surface 30 of the semiconductor chip 3 is provided with bumps 31 and a gap t1 necessary for an electric circuit, as schematically shown in a longitudinal section before the bonding step.
- the dummy bumps 3 2 necessary for the operation free dummy bumps 3 4 and 3 5 which are unnecessary in the electric circuit and are not used for securing the gap t 1 are formed.
- the dummy bumps 34 of the free are located in the formation regions of the device holes 23.
- the dummy bumps 35 of the free are located in the formation region of the overlapping portion 212, the conductor pattern 22 is not formed there.
- the device hole 23 is divided into four holes 2 3 1, 2 3 2, 2 3 3, and 2 3 4 by the overlapping section 2 12. Therefore, even if it is formed so as to cross the device hole 23 as in the crossover portion 2 2 2 of the conductor pattern 2 2, the crossover portion 2 2 2 only needs to straddle one hole 2 3 2. It is often in a state where it is reinforced by the superimposed portion 212. Similarly, the crossover bar portion 2 23 of the conductor pattern 22 has its leading end supported by the overlapping portion 2 12 across only one hole 2 32. Therefore, wiring can be freely performed at a position facing the active surface 30 of the semiconductor chip 3, and the strength of the conductive pattern formed there is high. In addition, the circuit board 2 can be strengthened by leaving the superimposed portion 2 1 1 1 2 1 2 inside the device hole 23, so that unnecessary deformation of the flexible circuit board 2 can be prevented.
- the lead portion 211 is vertically and horizontally facing the drawing. It can be projected in any of the directions. Therefore, for example, as in the case of the lead portion 211a, it is possible to protrude along the inner peripheral edge of the device hole 23.
- the flexibility of wiring pattern design is high, such as the formation of lead portions 211a and 211b protruding in the direction in which the wiring pattern is formed. Therefore, the semiconductor device 1 of this example has high reliability and a high degree of freedom in design, and can be used for a wide range of applications.
- the superimposed portion 2 1 2 is formed so as to divide the device hole 23 through a substantially central portion of the device hole 23, and to form the central portion of the device hole 23, that is, the semiconductor chip 3.
- a through hole 230 is formed in the overlapping portion 212 at a portion corresponding to a substantially central portion of the hole. Therefore, as described below, there is an advantage that productivity in the mounting process is high.
- the semiconductor chip 3 is positioned with respect to the device hole 23 of the circuit board 2. In this state, the superimposed portion 211 overlaps with the semiconductor chip 3.
- the thickness of the dummy bump 32 changes before and after the joining step between the bump 31 and the lead portion 22 1. Without maintaining the initial thickness. For this reason, a gap t1 between the circuit board 2 and the semiconductor chip 3 according to the initial thickness of the dummy bump 32 is secured.
- the molding material 4 is filled in the device holes 23.
- the device hole 2 3 is divided into four holes 2 3 1, 2 3 2 ′, and the molding material 4 is injected from each of the holes 2 3 1, 2 3 2. . Therefore, the wrap around of the molding material 4 is smooth.
- the through hole 230 is formed in a region corresponding to the center of the device hole 23 in the superimposed portions 2 1 1 and 2 1 2, when the molding material 4 is injected, Since the air escapes from the through hole 230, the molding Lumber 4 is smoothly wrapped around. Therefore, the productivity in the mounting process is high.
- the dummy bump 32 overlaps the conductive pattern 22 formed on the overlapping portion 211 of the circuit board 2, but the rigidity of the base 21 is relatively large.
- a structure is adopted in which the dummy bump 32 directly overlaps the base material 21 of the overlapping portion 211. You may. Second embodiment
- the semiconductor device of this example has a basic configuration similar to that of the semiconductor device according to the first embodiment. Therefore, portions having common functions are denoted by the same reference numerals, and detailed description thereof is omitted. I do.
- Fig. 4 (a) is a vertical cross-sectional view schematically showing a state before the semiconductor chip is mounted on the circuit board in the semiconductor device of this example
- Fig. 4 (b) is a semiconductor device mounted on the circuit board. It is a longitudinal cross-sectional view which shows the state afterward typically.
- the active surface 30 of the semiconductor chip 3 has bumps 3 1 (joint) required on an electric circuit. Electrodes and a dummy bump 32 (spacer part) that is unnecessary in the electrical circuit.
- a device hole 23 is formed on the circuit board 2 side, and a lead portion 22 1 of the conductor pattern 22 protrudes toward the inside.
- the circuit board 2 has an overlapping portion 2 1 1 overlapping the semiconductor chip 3 with the semiconductor chip 3 positioned with respect to the device hole 2 3.
- the overlapping portion 2 1 1 also has a conductive pattern 2 2. Are formed.
- the conductor pattern 2 2 formed on the superimposed portion 2 1 1 When the semiconductor chip 3 is positioned with respect to the circuit board 2, a protrusion 222 (a spacer portion) protruding from the conductive pattern 22 is formed in a portion overlapping the dummy bump 32.
- the projections 224 are bumps transferred to the circuit board 2 side.
- the dummy bump 32 is not bonded to the conductive pattern 22 (projection 222), so that the dummy bump 32 is not deformed, and the lead portion 222 and the bump 31 are not deformed.
- the initial thickness is maintained even after the bonding process.
- the protrusions 2 2 4 are not deformed and maintain the initial thickness. Therefore, between the circuit board 2 and the semiconductor chip 3, the thickness of the dummy bumps 32 and the protrusions 2 2 4 Since a gap t2 having a size corresponding to the sum of the thickness of the semiconductor chip 3 and the thickness of the semiconductor chip 3 is ensured, no short-circuit occurs between the circuit board 2 and the edge of the semiconductor chip 3 without forming.
- the dimension of the gap t2 is determined by the thickness of the dummy bump 32 and the thickness of the projection 222, it is not necessary to set the dimension unnecessarily large. Therefore, even with the semiconductor device 11 employing the structure joined by the single point bonding method, the thickness can be reduced and the reliability is high.
- the dummy bumps 32 can be formed simultaneously with the bonding bumps 31, the cost of the semiconductor chip 3 does not increase.
- the semiconductor device 1 of the present embodiment also has the same planar structure as the semiconductor device of the first embodiment shown in FIG. 1, so that the molding material 4 is provided in the device hole 23.
- the molding material 4 can be injected from the respective holes 2 3 1, 2 3 2 ⁇ .
- the mold When the material 4 is injected, air escapes from the through hole 230. Therefore, the surrounding of the injected molding material 4 is smooth.
- the projections 2 24 of the conductive pattern 22 are arranged to overlap the dummy bumps 32 of the semiconductor chip 3.However, if the projections 2 24 are sufficiently thick, an insulation coating is applied.
- the active surface 30 of the semiconductor chip 3 may be overlapped with the active surface 30 itself.
- the semiconductor device of the present embodiment also has the same basic configuration as the semiconductor device according to the first embodiment. Therefore, portions having common functions are denoted by the same reference numerals, and detailed description thereof is omitted. I do.
- Fig. 5 (a) is a vertical cross-sectional view schematically showing a state before the semiconductor chip is mounted on the circuit board in the semiconductor device of this example, and Fig. 5 (b) shows a semiconductor device mounted on the circuit board. It is a longitudinal cross-sectional view schematically showing a later state.
- a device hole 23 is formed on the circuit board 2 side, and a lead portion 2 of the conductor pattern 22 is formed toward the inside thereof. 2 1 is sticking out.
- the conductor pattern 22 is composed of a gold-plated lead wire.
- an aluminum pad 38 is formed on the semiconductor chip 3, and a lead portion 221 is bonded to only the aluminum pad 38a (joining electrode).
- the aluminum pad 38a is a necessary pad for an electric circuit, but the aluminum pad 38b is electrically connected to any circuit formed inside the semiconductor chip 3. It is unnecessary pad on the electric circuit.
- the semiconductor chip 3 is inexpensive.
- a portion overlapping the aluminum pad 38 b is a projection 2 25 (spacer portion) protruding from other portions of the conductor pattern 22.
- the projections 225 are portions where the etching of the portions where the projections 225 are to be formed is stopped by hammering when the conductor pattern 222 is formed by etching, and the projections 225 are thicker than the other portions.
- the portion located around the semiconductor chip 22 is made thinner, and the projections 225 are made thicker than this portion.
- ultrasonic vibration is applied to the lead portion 221, so that the lead portion 221 and the aluminum pad 38a are formed by a single point bonding method.
- the lead portion 22 1 bends downward, but the protrusion 2 25 is not bonded to the semiconductor chip 3 side. 2 2 5 is not crushed.
- a gap t3 is provided between the circuit board 2 and the semiconductor chip 3 according to the initial thickness of the projections 2 25. No short-circuit occurs between them.
- the thickness of the projection 2 25 does not change before and after the joining process between the lead portion 2 21 and the aluminum pad 38 a, and the dimension of the gap t 3 is set in advance.
- the gap t3 which is determined by the initial thickness dimension of the projections 225, does not have to be set unnecessarily large. Therefore, the semiconductor device 21 of the present example can be reduced in thickness and has high reliability. Also, since the projections 222 use a part of the conductive pattern 22, the cost of the circuit board 3 does not rise.
- the semiconductor device 12 of the present embodiment also has the same planar structure as the semiconductor device of the first embodiment shown in FIG. Therefore, when filling the molding material 4 with the device holes 23, the respective holes 2 3 1 Mold material 4 can be injected from 2 3 2. Further, when the molding material 4 is injected, air escapes from the through hole 230. Therefore, the surroundings of the molding material 4 are smooth.
- the projections 22 of the conductive pattern 22 overlap the aluminum pad 38 b of the semiconductor chip 3, but are insulated from the circuit of the semiconductor chip 3. For example, it may overlap the active surface 30 itself provided with the insulating coating.
- the projections 22 of the conductive pattern 22 overlap the aluminum pad 38 b of the semiconductor chip 3, but are insulated from the circuit of the semiconductor chip 3.
- it may overlap the active surface 30 itself provided with the insulating coating.
- a superimposed portion overlapping the semiconductor chip is formed on the circuit board, and a conductor pattern is formed on the superimposed portion or the surface of the semiconductor chip overlapping therewith. If a spacer portion whose thickness does not change before and after the bonding process between the semiconductor chip and the bumps is formed, for example, from the protrusion of the base material constituting the circuit board or from the active surface itself of the semiconductor chip Protrude
- Insulating protrusions may be used.
- the bottom surface of the bonding tool T is not a plane, but a bond T1 etc. is formed so as to avoid the overlapping portions 2 1 1 and 2 1 2 and the crossover portions 2 2 2 and 2 Tool T may be used.
- the superimposed portion of the semiconductor chip disposed in the device hole is formed on the circuit board side.
- a predetermined gap is ensured by a spacer portion such as a formed dummy bump or a protrusion formed on a conductor pattern of a superimposed portion. Therefore, according to the present invention, in the single point bonding method or the like, a predetermined gap can be secured between the superimposed portion and the semiconductor chip without forming the lead portion of the circuit board.
- shorts at the edge of the semiconductor chip can be prevented while keeping the semiconductor device thin, and the reliability is high.
- the productivity is improved.
- a conductive pattern can be formed in the superimposed area, and wiring can be applied to the area facing the active surface of the semiconductor chip. This increases the degree of freedom in pattern design and increases the versatility of the semiconductor chip. Become.
- a dummy bump is formed on the side of the semiconductor chip and a projection of the conductor pattern is formed on the overlapping portion of the circuit board, the dummy bump formed on the side of the semiconductor chip is provided between the circuit board and the semiconductor chip.
- a wide gap corresponding to the sum of the thicknesses of the projections can be easily formed.
- a uniform gap can be ensured even for a semiconductor chip having a large chip size. Further, when the overlapping portion is also formed on the side portion of the device hole, a more uniform gap can be ensured even for a semiconductor chip having a larger chip size.
- the molding material can be injected from each hole, so that the molding material can be smoothly wrapped around.
- the crossover part is reinforced by the superimposed part, so the freedom of circuit pattern design can be maintained while maintaining high reliability. Is improved.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940704091A KR100296834B1 (ko) | 1993-04-08 | 1994-04-04 | 반도체장치 |
US08/351,383 US5563445A (en) | 1993-04-08 | 1994-04-04 | Semiconductor device |
DE69433543T DE69433543T2 (de) | 1993-04-08 | 1994-04-04 | Halbleitervorrichtung. |
EP94910595A EP0645806B1 (en) | 1993-04-08 | 1994-04-04 | Semiconductor device |
HK98115925A HK1014612A1 (en) | 1993-04-08 | 1998-12-28 | Semiconductor device. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP08220793A JP3269171B2 (ja) | 1993-04-08 | 1993-04-08 | 半導体装置およびそれを有した時計 |
JP5/82207 | 1993-04-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1994024698A1 true WO1994024698A1 (en) | 1994-10-27 |
Family
ID=13767983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1994/000551 WO1994024698A1 (en) | 1993-04-08 | 1994-04-04 | Semiconductor device |
Country Status (9)
Country | Link |
---|---|
US (1) | US5563445A (ja) |
EP (1) | EP0645806B1 (ja) |
JP (1) | JP3269171B2 (ja) |
KR (1) | KR100296834B1 (ja) |
CN (1) | CN1047470C (ja) |
DE (1) | DE69433543T2 (ja) |
HK (1) | HK1014612A1 (ja) |
TW (1) | TW301793B (ja) |
WO (1) | WO1994024698A1 (ja) |
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US5834339A (en) | 1996-03-07 | 1998-11-10 | Tessera, Inc. | Methods for providing void-free layers for semiconductor assemblies |
US6232152B1 (en) | 1994-05-19 | 2001-05-15 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
US6359335B1 (en) | 1994-05-19 | 2002-03-19 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
US5706174A (en) * | 1994-07-07 | 1998-01-06 | Tessera, Inc. | Compliant microelectrionic mounting device |
US6169328B1 (en) | 1994-09-20 | 2001-01-02 | Tessera, Inc | Semiconductor chip assembly |
US5915170A (en) * | 1994-09-20 | 1999-06-22 | Tessera, Inc. | Multiple part compliant interface for packaging of a semiconductor chip and method therefor |
US6870272B2 (en) | 1994-09-20 | 2005-03-22 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
US6046076A (en) * | 1994-12-29 | 2000-04-04 | Tessera, Inc. | Vacuum dispense method for dispensing an encapsulant and machine therefor |
JP3643640B2 (ja) * | 1995-06-05 | 2005-04-27 | 株式会社東芝 | 表示装置及びこれに使用されるicチップ |
JP3270807B2 (ja) * | 1995-06-29 | 2002-04-02 | シャープ株式会社 | テープキャリアパッケージ |
US6284563B1 (en) * | 1995-10-31 | 2001-09-04 | Tessera, Inc. | Method of making compliant microelectronic assemblies |
US6211572B1 (en) | 1995-10-31 | 2001-04-03 | Tessera, Inc. | Semiconductor chip package with fan-in leads |
US6686015B2 (en) | 1996-12-13 | 2004-02-03 | Tessera, Inc. | Transferable resilient element for packaging of a semiconductor chip and method therefor |
JPH11260863A (ja) * | 1998-03-09 | 1999-09-24 | Sumitomo Electric Ind Ltd | 半導体装置用接続端子とその製造方法 |
FR2778475B1 (fr) * | 1998-05-11 | 2001-11-23 | Schlumberger Systems & Service | Carte a memoire du type sans contact, et procede de fabrication d'une telle carte |
KR20000012074A (ko) * | 1998-07-31 | 2000-02-25 | 야스카와 히데아키 | 반도체 장치 및 그 제조 방법, 반도체 장치의 제조 장치, 회로기판 및 전자 기기 |
JP3919972B2 (ja) | 1998-07-31 | 2007-05-30 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US6214640B1 (en) | 1999-02-10 | 2001-04-10 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages |
US6146984A (en) * | 1999-10-08 | 2000-11-14 | Agilent Technologies Inc. | Method and structure for uniform height solder bumps on a semiconductor wafer |
US6096649A (en) * | 1999-10-25 | 2000-08-01 | Taiwan Semiconductor Manufacturing Company | Top metal and passivation procedures for copper damascene structures |
US6833557B1 (en) * | 2000-06-27 | 2004-12-21 | Agere Systems Inc. | Integrated circuit and a method of manufacturing an integrated circuit |
JP3490987B2 (ja) * | 2001-07-19 | 2004-01-26 | 沖電気工業株式会社 | 半導体パッケージおよびその製造方法 |
JP4099673B2 (ja) * | 2004-12-21 | 2008-06-11 | セイコーエプソン株式会社 | 半導体装置 |
KR101357765B1 (ko) * | 2005-02-25 | 2014-02-11 | 테세라, 인코포레이티드 | 유연성을 갖는 마이크로 전자회로 조립체 |
TWI310983B (en) * | 2006-10-24 | 2009-06-11 | Au Optronics Corp | Integrated circuit structure, display module, and inspection method thereof |
US7749886B2 (en) | 2006-12-20 | 2010-07-06 | Tessera, Inc. | Microelectronic assemblies having compliancy and methods therefor |
US8045333B2 (en) * | 2008-01-14 | 2011-10-25 | Rosemount Inc. | Intrinsically safe compliant circuit element spacing |
TWI429000B (zh) * | 2010-07-08 | 2014-03-01 | Novatek Microelectronics Corp | 晶片線路扇出方法及薄膜晶片裝置 |
US9691686B2 (en) | 2014-05-28 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact pad for semiconductor device |
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-
1994
- 1994-04-02 TW TW083102942A patent/TW301793B/zh not_active IP Right Cessation
- 1994-04-04 KR KR1019940704091A patent/KR100296834B1/ko not_active IP Right Cessation
- 1994-04-04 EP EP94910595A patent/EP0645806B1/en not_active Expired - Lifetime
- 1994-04-04 US US08/351,383 patent/US5563445A/en not_active Expired - Lifetime
- 1994-04-04 CN CN94190177A patent/CN1047470C/zh not_active Expired - Lifetime
- 1994-04-04 WO PCT/JP1994/000551 patent/WO1994024698A1/ja active IP Right Grant
- 1994-04-04 DE DE69433543T patent/DE69433543T2/de not_active Expired - Lifetime
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1998
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JPS53123074A (en) * | 1977-04-01 | 1978-10-27 | Nec Corp | Semiconductor device |
JPS6031244A (ja) * | 1983-08-01 | 1985-02-18 | Oki Electric Ind Co Ltd | 半導体装置 |
JPS6395639A (ja) * | 1986-10-09 | 1988-04-26 | Mitsubishi Electric Corp | テ−プキヤリア |
JPH03126237A (ja) * | 1989-10-12 | 1991-05-29 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0645806A4 (en) | 1995-10-11 |
KR950701769A (ko) | 1995-04-28 |
EP0645806B1 (en) | 2004-02-11 |
JP3269171B2 (ja) | 2002-03-25 |
US5563445A (en) | 1996-10-08 |
DE69433543T2 (de) | 2004-12-23 |
EP0645806A1 (en) | 1995-03-29 |
KR100296834B1 (ko) | 2001-10-24 |
JPH06295939A (ja) | 1994-10-21 |
CN1047470C (zh) | 1999-12-15 |
HK1014612A1 (en) | 1999-09-30 |
DE69433543D1 (de) | 2004-03-18 |
TW301793B (ja) | 1997-04-01 |
CN1104415A (zh) | 1995-06-28 |
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