KR950034591A - 반도체 장치의 제조 방법 - Google Patents

반도체 장치의 제조 방법 Download PDF

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Publication number
KR950034591A
KR950034591A KR1019950011278A KR19950011278A KR950034591A KR 950034591 A KR950034591 A KR 950034591A KR 1019950011278 A KR1019950011278 A KR 1019950011278A KR 19950011278 A KR19950011278 A KR 19950011278A KR 950034591 A KR950034591 A KR 950034591A
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South Korea
Prior art keywords
forming
semiconductor substrate
film
temperature
introducing
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KR1019950011278A
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English (en)
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KR0175430B1 (ko
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분지 미즈노
겐지 오까다
이찌로 나까야마
Original Assignee
모리시다 요이치
마쯔시다 덴기 산교 가부시끼가이샤
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Publication of KR950034591A publication Critical patent/KR950034591A/ko
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Publication of KR0175430B1 publication Critical patent/KR0175430B1/ko

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    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract

반도체 기판상에 250℃ 이하의 온도하에서 전리방사선 또는 광선을 조사하면서 적당한 기능성 가스를 도입하는 것에 의해 반도체 기판상에 P형 불순물층, 실리콘 단결정막, 실리콘 산화막, 실리콘막을 순차 형성한다. 250℃ 이하의 온도하에 있어서, 실리콘막상에 포토레지스트를 형성한 후, 포토레지스트를 마스크로서 에칭하여 실리콘 산화막으로 되는 게이트 전극 B 및 실리콘 산화막으로 되는 게이트 절연막을 형성하고, 그 후, 게이트 전극을 마스크로서 에칭하는 것에 의해 P형 불순물층으로 되는 채널영역을 형성한다. 반도체 기판상에 250℃ 이하의 온도하에서 전리방사선 또는 광선을 조사하면서 적당한 기능성 가스를 도입하는 것에 의해 반도체 기판상에서의 게이트 전극의 측방에 소스.드레인 전극을 형성한다.

Description

반도체 장치의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 각 실시예에 사용하는 반도체 장치의 제조장치의 단면도, 제2도 (b)는 본 발명의 제3실시예에 관한 반도체 장치의 제조 방법의 각 공정을 표시하는 단면도.

Claims (8)

  1. 불순물층을 가지는 반도체 기판상에 250℃ 이상의 온도하에서 전리방사선 또는 광선을 조사하면서 기능성 가스를 도입하는 것에 의해 상기 반도체 기판상에 막을 형성하는 막형성 공정을 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  2. 제1항에 있어서, 상기 막형성 공정은 반도체 기판상에 기능성 가스를 도입하면서 반도체 기판의 표면에 전자선을 노광하는 것에 의해 반도체 기판상에 패턴화된 막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  3. 반도체 기판상에 250℃ 이상의 온도하에서 전리방사선 또는 광선을 조사하면서 기능성 가스를 도입하는 것에 의해 상기 반도체 기판상에 반도체 기판의 주성분과 다른 원자 또는 분자로 되는 층을 형성하는 층 형성 공정을 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  4. 제3항에 있어서, 상기 층 형성공정은 반도체 기판상에 기능성 가스를 도입하면서 반도체 기판의 표면에 전자선을 노광하는 것에 의해 반도체 기판상에 패턴화된 층을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  5. 반도체 기판상에 250℃ 이하의 온도하에서 전리방사선 또는 광선을 조사하면서 기능성 가스를 도입하는 것에 의해 반도체 기판상에 채널 영역으로 되는 불순물층을 형성하는 공정과, 반도체 기판상에 250℃ 이하의 온도하에서 전리방사선 또는 광선을 조사하면서 기능성 가스를 도입하는 것에 의해 상기 불순물층상에 게이트 절연막으로 되는 절연층을 형성하는 공정과, 반도체 기판상에 250℃ 이하의 온도하에서 전리방사선 또는 광선을 조사하면서 기능성 가스를 도입하는 것에 의해 상기 절연층상에 게이트 전극으로 되는 도전층을 형성하는 공정과, 250℃ 이하의 온도하에서 상기 도전층상에 게이트 전극 형성영역을 덮는 레지스트 패턴을 형성하는 공정과, 250℃ 이하의 온도하에서 상기 레지스트 패턴을 마스크로서 상기 도전층에 대하여 에칭을 행하는 것에 의해 상기 도전층으로 되는 게이트 전극 및 상기 절연층으로 되는 게이트 절연막을 형성하는 공정과, 250℃ 이하의 온도하에서 상기 게이트 전극을 마스크로서 상기 불순물층에 대하여 에칭을 행하는 것에 의해 상기 불순물층으로 되는 채널 영역을 형성하는 공정과, 반도체 기판상에 250℃ 이하의 온도하에서 전리방사선 또는 광선을 조사하면서 기능성 가스를 도입하는 것에 의해 반도체 기판상에서의 상기 채널 영역의 양측에 소스 전극 및 드레인 전극을 형성하는 공정을 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  6. 반도체 기판상에 레지스트 패턴을 형성하는 레지스트 패턴 형성공정과, 반도체 기판상에 250℃ 이하의 온도하에서 전리방사선 또는 광선을 조사하면서 기능성 가스를 도입하는 것에 의해 반도체 기판상에 에피택셜 성장막을 형성하는 성장막 형성 공정과, 상기 레지스트 패턴을 제거하는 것에 의해 상기 에피택셜 성장막으로 되는 패턴화된 성장막을 형성하는 성장막 패턴 형성공정을 구비하고 있는 것을 특징으로 하는 반도체 장치의 제조방법.
  7. 제6항에 있어서, 상기 성장막 형성 공정은 전면에서의 성장인 블랭킷 성장법에 의해 상기 에피택셜 성장막을 형성하는 공정을 포함하고, 상기 성장막 패턴 형성공정은 상기 레지스트 패턴을 제거하여 상기 레지스트 패턴상의 퇴적물을 제거하는 것에 의해 상기 레지스트 패턴이 형성되어 있지 않았던 영역에 패턴화된 성장막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  8. 제6항에 있어서, 상기 성장막 형성 공정은 선택성장법에 의해 상기 레지스트 패턴이 형성되어 있지 않았던 영역에 상기 에피택셜 성장막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950011278A 1994-05-16 1995-05-09 반도체 장치의 제조 방법 KR0175430B1 (ko)

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