CN1088911C - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
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- CN1088911C CN1088911C CN95106027A CN95106027A CN1088911C CN 1088911 C CN1088911 C CN 1088911C CN 95106027 A CN95106027 A CN 95106027A CN 95106027 A CN95106027 A CN 95106027A CN 1088911 C CN1088911 C CN 1088911C
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Abstract
通过在低于250℃的温度下一边向半导体基片1照射电离射线或光线一边导入适当的功能性气体,在半导体基片上依次形成P型杂质层、硅单晶层、硅氧化膜和硅膜。在低于250℃的温度下,以硅膜上形成的光刻胶为掩模进行刻蚀形成由硅氧化膜构成的棚电极B和栅极绝缘膜。之后以栅电极为掩模进行刻蚀,形成由P型杂质层构成的沟道区域。通过在低于250℃的温度下边照射电离射线或光线边导入适当的气体,在栅极侧面上形成源、漏电极。
Description
本发明涉及半导体装置的制造方法,特别是涉及可以在大约250℃以下的低温下实现在现有技术中在高温下进行的伴有热处理的膜形成工序的半导体装置的制造方法。
图7示出了现有的半导体装置制造方法中所采用的制造装置的概略断面构造。如图7所示,半导体装置制造设备包括:内部保持真空状态的真空室50、设于真空室50内放置并保持半导体基片的基片保持台52、排除真空室内气体的排气系统54以及向基片保持台52照射所需的离子56的离子枪58。
以下,参照图7和图8对现有技术的半导体装置(例如MOS晶体管)的制造方法的大致情况进行说明。
首先,向保持在基片保持台52上边的比如说由硅形成的半导体基片60的表面上喷射所需的离子56。用这种办法在半导体基片60的表面上形成所希望的杂质层62之后,在该杂质层62上边生长硅层64。
接着将半导体基片60移入图中没有画出的电炉并将半导体基片60在高温下保持在指定的氧化气氛中。用这种办法,如图8所示,在硅层64的表面部分形成硅氧化膜。之后,将半导体基片移往图中没有画出的CVD装置,在硅氧化膜66上形成例如栅极电极68以完成MOS晶体管。
然而,在现有技术中,在电炉中形成硅氧化膜66时,半导体基片60被暴露在高温之中,故存在着破坏前面工序中制作的杂质层62的分布(比如说陡峻的杂质分布)的问题。就是说,在制造半导体装置的时候,对例如纯的硅单晶形成的半导体基片中的指定部位掺入规定量的指定的杂质,之后还需要进行若干个高温工艺,例如在单晶膜上进行外延生长的工艺。
图9示出了在向半导体基板中掺入了杂质的情况下杂质在深度方向上的陡峻分布,在之后的工序中,希望杂质的陡峻分布不发生变化。然而,在后部工序的膜形成工艺中处理温度高的时候,存在着使已设定好了的杂质分布状态发生变化(比如说破坏陡峻的杂质分布)的问题。
可是,当降低后部工序中膜形成工艺的处理温度时,又存在着不能形成良好的膜的问题。
此外,在高温下的膜形成工艺中,除去会使杂质层的分布状态发生变化之外,还存在着对例如前部工序形成的氧化物层、氮化物层或者碳化物层等化合物层的分布产生不良影响的问题。
鉴于上述问题,本发明的目的是使得现有技术中在高温下进行的膜形成工艺可以在低温下完成。
本发明所涉及的第1种半导体装置的制造方法是基于这一发现得到的:通过一边用电离放射 线或光线照射一边导入功能性气体的办法形成膜,就可以形成与现有技术在高温下形成的膜一样好的薄膜。
第1种半导体装置的制造方法具备有在有杂质层的半导体基片上,通过一边在低于250℃的温度下照射电离放射线或光线一边导入功能性气体而在上述半导体基片上形成膜的膜形成工序。
当向半导体基片上一边照射电离放射线或光线一边导入功能性气体时,由于电离放射线或光线把能量给予功能性气体,在低于250℃的低温下,功能性气体与半导体基片的主要成分进行反应。
另外,由于膜是在低于250℃的低温下形成的,故不会把半导体基片置于高温之下,所以可以形成不影响半导体基片中杂质分布的膜。
因此,可以在半导体基片上良好地形成不影响半导体基片中杂质分布的膜。
在第1种半导体装置的制造方法中,膜形成工序可以包括通过采用一边向半导体基片中导入功能性气体一边对半导体基片的表面进行电子束曝光的办法在半导体基片上形成图形化膜的工序。
由于在半导体基片的表面中,功能性气体仅仅在被电子束曝光的区域与半导体基片的主要成分进行反应,故不需进行刻蚀工序就可以在半导体基片上形成图形化了的膜,所以,可以在半导体基片上形成可微细地进行控制的图形。
本发明所涉及的第2种半导体装置的制造方法,具有通过在低于250℃的温度下把电离放射线或光线照射到半导体基片上的同时把功能性气体导入半导体基片中去,在半导体基片上形成由与半导体基片的主要成分不同的原子或分子组成的层的层形成工序。
在照射电离放射线或光线的同时把功能性气体导入半导体基板之后,电离放射线或光线把能量传给功能性气体,故即便是在低于250℃的低温下,功能性气体也能与半导体基片的主要成分进行反应,所以可以良好地形成由与半导体基片主要成分不同的原子或分子组成的层。
此外,由于膜是在低于250℃的低温下形成的,故不会把半导体基片置于高温之下,功能性气体的成分难于扩散到半导体基片中去。所以,可以形成不影响半导体基片的晶体构造的层。
因此,可以在半导体基片上良好地形成由与该半导体基片的主要成分不同的原子或分子组成的层而不影响半导体基板的晶体构造。
在第2种半导体装置的制造方法中,层形成工序可以包括通过在向半导体基片中导入功能气体的同时对半导体基片的表面进行电子束曝光而在半导体基片上形成图形化层的工序。
这样一来,由于可以在半导体基片上形成图形化层而不需进行刻蚀工序,故可以在半导体基片上形成可进行微细控制的图形。所以得以在半导体基片上形成可以微细地进行控制的图形。
本发明所涉及的第3种半导体装置的制造方法是将上述知识应用于制造MOS晶体管的一种方法,它包括下列工序:1)杂质层形成工序,通过在低于250℃的温度下在照射电离射线或光线的同时把功能性气体导入半导体基片中去而在半导体基片上形成将成为沟道区域的杂质层;2)绝缘层形成工序,通过在低于250℃的温度下在照射电离射线或光线的同时把功能性气体导入半导体基片中去而在杂质层上边形成将成为栅极绝缘膜的绝缘层:3)形成导电层的工序,通过在低于250℃的温度下在照射电离射线或光线的同时把功能性气体导入半导体基片中去,以此在绝缘层的上边形成将构成栅极电极的导电层;4)形成光刻胶图形的工序,在低于250℃的温度下在导电层上形成覆盖栅极电极区域的光刻胶图形;5)形成栅电极和栅绝缘膜的工序,在低于250℃的温度下,通过以光刻胶图形作为掩模对导电层进行刻蚀的办法形成由导电层构成的栅极电极和由绝缘膜构成的栅绝缘膜;6)形成沟道区的工序,在低于250℃的温度下以上述栅极电极作为掩模对杂质进行刻蚀以形成由杂质层形成的沟道区;7)源电极和漏电极形成工序,通过在250℃的温度下在照射电离射线或光线的同时把功能性气体导入半导体基片中去而在半导体基片上的沟道区的两侧形成源电极和漏电极。
如此,由于形成构成沟道区的杂质层的工序,形成构成栅极绝缘膜的绝缘层形成工序、构成栅极电极的导电层的形成工序、光刻胶图形形成工序、栅极电极和栅极绝缘膜的形成工序、沟道区的形成工序以及源极电极和漏极电极的形成工序等,任一道工序都是在低于250℃的温度下进行的,故可以在不影响各自的杂质分布的情况下形成杂质层、绝缘层和导电层。为此,得以在不影响各自的杂质分布的情况下形成构成MOS晶体管的由杂质构成的沟道区、由绝缘层构成的栅数绝缘膜和由导电层构成的栅极电极。所以可以按设计所要求制造出能够高精度地进行控制的MOS晶体管。
本发明所涉及的第4种半导体装置的制造方法是基于这一发现得到的:若一边照射电离射线或光线一边进行外延生长,则在低温下也可以良好地形成外延生长薄膜。
第4种半导体装置的制造方法包括下列工序:1)光刻胶图形形成工序,在半导体基片上形成光刻胶图形;2)生长膜形成工序,通过在低于250℃的温度下在照射电离射线或光线的同时把功能性气体导入半导体基片上,在半导体基片上形成外延生长薄膜;3)生长膜图形形成工序,通过除去光刻胶形成由外延生长薄膜构成的经图形化的生长膜。
第4种半导体装置的制造方法由于在向半导体基片上照射电离射线或光线的同时导入功能性气体,故电离射线或光线把能量传给功能性气体,固此可在低于250℃的低温下进行外延生长,因而可以在不给光刻胶图形带来损伤的情况下形成外延生长膜。因此,可以实现在现有技术中不可能进行的仅在半导体基片上的指定区域进行外延生长的工艺。
在第4种半导体装置制造方法中,理想的是在生长膜形成工序中包含通过在整个面上进行生长的覆盖(blanket)外延生长法形成外延生长膜的工序、在生长膜图形形成工序中包含通过先除去光刻胶图形、然后除去该光刻胶图形上的堆积物而在未形成该光刻胶图形的区域上形成图形化生长膜的工序。
在用覆盖生长法形成外生长膜之后,在除掉光刻胶图形时,由于附着于光刻胶图形上的堆积物也将被除掉,故可以仅仅在半导体基片上未形成光刻胶图形的区域上形成图形化的生长膜。
在第4种半导体装置制造方法中,理想的是在生长膜形成工序中包含用选择生长法在上述未形成光刻胶图形的区域形成外延生长膜的工序。
在用选择生长法进行外延生长时,由于可以仅仅在半导体基片上未形成光刻胶图形的区域上形成外延生长膜,故不再需要除去光刻胶图形上的堆积物的工序。
图1是本发明的各实施例所用的半导体装置的制造设备的剖面图。
图2(a),(b)剖面图给出了本发明的第3实施例所涉及的半导体装置的制造方法的各个工序。
图3(a),(b)的剖面图示出了本发明的第3实施例所涉及的半导体装置的制造方法的各个制造工序。
图4(a),(b)的剖面图示出了本发明的第4实施例所涉及的半导体装置的制造方法的各个制造工序。
图5(a)-(c)的各剖面图示出了本发明的第5实施例所涉及的半导体装置的制造方法的各个工序。
图6(a)的剖面图示出了本发明的第6实施例所涉及的半导体装置的制造方法的工序,图6(b)的平面图示出了上述第6实施例所涉及的半导体装置的制造方法的工序。
图7是现有技术的半导体装置的制造设备的剖面图。
图8的剖面图示出了现有技术的半导体装置的制作方法。
图9示出了在半导体基片中形成的杂质层在深度方向上的杂质分布。
以下对本发明进行详细说明。
图1示出了本发明的各个实施例所使用的制造设备的剖面构造。如图1所示,该设备具有真空室10、基片保持台14和排气系统16。真空室10用不锈钢或玻璃材料构成,用于使内部保持真空状态。基片保持台14设置于真空室10之内,用于放置保持半导体基片1。排气系统16用于排除真空室10内部的气体。排气系统16也可以用于使载置于基片保持台14上的半导体基片1保持低温,还可用于使真空室内形成真空。
在图1中,18是一种温度控制装置,用于把保持于基片保持台14上的半导体基片1控制在从低温(约低于250℃的温度)到极低温(低于-269℃的温度)的温度范围之内。该温度控制装置18具有氦贮存槽20、氮贮存槽22和加热器24。氦贮存槽20用于贮存液氦,它放在基片保持台14的正下方,用于冷却基片保持台14。氦贮存槽22设于上述氦贮存槽20的周围,用于贮存液氮,液氮用于使氦贮存槽20与外部来的热隔断开。加热器24用于使基片保持台14升温。此外,为了获得良好的热传导,氦贮存槽20的顶部由例如铟等热良导体制造。
此外,真空室10里还设有电离射线导入部件26和气体导入部件28。电离射线导入部件26用于向真空室10内导入由X线、γ射线、光线(包括红外线、可见光、紫外线、真空紫外线等)或电子射线等组成的电离射线或光线。气体导入部分28用于向真空室10内导入各种功能性气体。
以下,参照图1对本发明的第1实施例所涉及的半导体装置的制造方法进行说明。
首先,用和现有技术相同的方法,把由例如其内部形成具有指定分布状态的杂质层的硅单晶构成的半导体基片1放置在保持为约-170℃的低温下的基片保持台14上。这时,真空室10内的真空度保持在10-6-10-9乇。
下边,对应用上述制造设备在形成了杂质层的半导体基片1上用外延生长法或淀积法形成指定薄膜的工序进行说明。
作为一个例子,对在由硅形成的半导体基片1上外延生长硅单晶膜的方法进行说明。在真空室10内部的真空度保持为10-9乇、基片保持台14的温度保持为约-170℃的状态下,在从气体导入部件对导入Si2H6作为功能性气体的同时,照射紫外线(比如波长为185nm)作为电离射线。这样,在半导体基片1的上边1分钟同质外延生长层厚约100nm的硅。
另外,真空室10的真空度、基片保持台14的温度、进行照射的电离射线或光线的种类和照射强度等等可以由半导体基片1的物理性质和杂质层分布状态的保持程度的设定等等进行适当的变更。
这样,在低温下,例如在大约-170℃,在半导体基片1上外延生长单晶膜时,由于半导体基片1中的杂质难于向半导体基片1中扩散,故杂质层中的原始杂质分布(比如说陡峻的杂质分布)就可以维持不变。
此外,作为另一例子,在由硅单晶形成的半导体基片1的表面上形成氧化膜的情况下,在真空室10的内部真空度保持为10-9乇、基片保持台14的温度保持为约-170℃的状态下,在作为功能性气体从气体导入部件28导入O2气体、N2O气体、O2和N2O的混合气体或者O3气体的同时,用同步加速器辐射以50mW/cm2的强度照射波长约100nm的X射线。
还有,作为另一个例子,在由硅形成的半导体基片1的表面上形成氮化膜的情况下,在真空室10的内部真空度保持为10-9乇、基片保持台14的温度保持为约-170℃的状态下,作为气体导入N2气体或者NH4气体。在由硅形成的半导体基片1的表面形成碳化膜时,在真空室10的内部真空度保持为10-9乇、基片保持台的温度保持为约-170℃的状态下,作为功能性气体,导入CH4气体或者C2H6气体。
还有,作为电离射线或光线,不用X射线代之以用γ射线、光线(可见光线、红外光线、紫外光线、真空紫外光线)或者电子射线进行照射也可获得同样的效果。
下边,对本发明的第2实施例所涉及的半导体装置的制造方法进行说明。
在制造半导体装置的情况下,比如说有必要在由纯半导体单晶形成的半导体基片的表面上,形成组成与半导体基片的主要成分不同的膜而不影响半导体基片的晶体结构。第2实施例讲的就是这样一种方法:在半导体基片的表面上形成由与半导体基片的主要成分不同的成分构成的膜(例如杂质层、氧化膜或者电极)而不影响半导体基片的晶体结构。
把半导体基片1置于保持为大约-170℃的低温的基片保持台14上、并把真空室10内部的真空度保持10-6-10-9乇的状态下,一边从气体导入部件28导入功能性气体一边照射电离射线或者光线。这样,就将在半导体基片1上边异质外延生长由功能性气体中所含的原子或分子组成的薄膜。因此,在半导体基片1上形成了由与该半导体基片1的主要成分不同的原子或分子组成的薄膜。在这种情况下,由于一边照射电离射线或光线一边导入功能性气体,故尽管是在大约-170℃的低温下,也能在半导体基片1的上边外延生成由功能性气体中所含的分子或原子组成的膜。另外,由于是在低温下进行外延生长,故可以在半导体基片1上形成由与该半导体基片1的主要成分不同的成分组成的膜而不影响半导体基片1的单晶结构,这是因为功能性气体中所含的原子或分子不向半导体基片1中扩散。
作为一个例子,对在由硅单晶构成的半导体基片1上边外延生长由硼构成的杂质层的情况进行说明。将真空室10内部的真空度保持为10-9乇、基片保持台14的温度保持为大约-170℃的状态下,作为功能性气体从气体导入部件28导入B2H6的同时,照射作为电离射线的紫外线(例如波长185nm)。真空室10的真空度、基片保持台14的温度、进行照射的电离射线或光线的种类或照射强度等等可根据半导体基片1的物理性质以及杂质层的分布状态的保持程度的设定等进行适当的变更。
上述第2实施例是在整个半导体基片上整个面地形成薄膜的情况,但是代之以在半导体基片上形成网格状的薄膜时,本发明也可以应用。
在半导体基片上形成网格状的薄膜的情况下,在把真空室10内部的真空度保持在10-9乇、基片保持台14的温度保持在大约-170℃的状态下,从气体导入部件28向真空室10内导入低浓度的功能性气体。这样,由于在半导体基片1的上边排列上数量受限定的原子或分子,故可以使半导体基片1的晶格排列不是以密密地埋入的形式而是以跳过若干个晶格位置的网格状的形式在半导体基片1的上边形成网格格状的薄膜。
其次,对在形成于半导体基片1表面上的杂质层之上外延生长由半导体单晶构成的膜而不影响该杂质层状态的工序进行说明。这样的工序在MOSFET等的制造工艺中是必要的,采用降低这一制造工艺的温度的办法,在半导体基片1的上边就可以形成外延生长膜而不影响半导体基片1的晶体结构和在半导体基片1上形成的杂质层的分布。
作为一个例子,对在半导体基片1上的杂质层上外延生长由硅单晶组成的硅膜的情况进行说明。在真空室10的内部真空度保持在10-9乇、基片保持台14的温度保持在大约-170℃的状态下,作为功能性气体从气体导入部件28导入Si2H6的同时照射作为电离射线的紫外线(例如波长185nm)。这样,在杂质层上边由硅单晶组成的硅膜以每分钟约100nm进行异质外延生长。此外,真空室10的真空度、基片保持台14的温度、进行照射的电离射线或光线的种类和照射强度等可以根据半导体基片1的物理性质和杂质层的分布状态的保持程度的设定进行适当的变更。
接下来,对在硅膜的表面部上形成氧化膜而不影响半导体基片1的晶体结构以及在该半导体基片1表面上形成的杂质层的分布的工序进行说明。
在真空室10的内部真空度保持在10-9乇、基片保持台14的温度保持在约-170℃的状态下,作为功能性气体,从气体导入部件28导入O2气体、N2O气体、O2和N2O的混合气体或者O3气体的同时,通过同步加速器辐射以50mW/cm2的强度照射波长约100nm左右的X射线。
此外,在上述杂质层之上不形成硅氧化膜而代之以形成硅氧化膜或者硅碳化膜的情况下,在真空室10的内部真空度保持在10-9乇、基片保持台14的温度保持在约-170℃的状态下,导入作为功能性能气体的N2气体或者NH4气体,或导入作为功能性气体的CH4气体或者C2H6气体。
还有,作为电离射线或光线,不用X射线而用γ射线、光线(可见光线、红外光线、紫外光线、真空紫外光线)进行照射,或者用电子射线进行照射也可得到同样的效果。
以下,说明本发明的第3实施例所涉及的半导体装置的制造方法。通过应用上述第1或第2实施例,可以制造各种先进的器件比如说MOS晶体管。第3实施例是一种MOS晶体管的制造方法,这种方法不影响在半导体基片中已形成的杂质层的分布。
首先把由硅单晶组成的半导体基片1置于保持在约-170℃的低温下的基片保持台14上。这时,真空室10内保持10-6-10-9乇的真空度。
其次,在真空室10内的真空度保持为10-9乇、基片保持台14的温度保持为约-170℃的状态下,从气体导入部件28导入作为功能性气体的B2H6的同时,照射以作为电离射线的紫外线(例如波长为185nm)。这样,如图2(a)所示,硼就在半导体基片1的表面上进行异质外延生长而形成P型杂质层30A。
接着,在真空室10内的真空度保持为10-9乇、保持基片保持台14的温度为约-170℃的状态下,在从气体导入部件28导入Si2H6作为功能性气体的同时,把紫外线(例如波长为185nm)用作电离射线进行照射。这样,就在P型杂质层30A的上边外延生长硅单晶膜31A而不影响该P型杂质层30A的分布状态。
在保持真空室10内的真空度为10-9乇、保持基片保持台14的温度为约-170℃的状态下,从气体导入部件28导入O2气体、N2O气体、O2和N2O的混合气体或者O3气体作为功能性气体,同时,通过同步加速器辐射以50mW/cm2的强度照射波长约100nm左右的X射线。这样一来,就把单晶膜31A氧化、在硅单晶膜31A的表面部分形成了硅氧化膜32A而不影响P型杂质层30A的排列状态。此外,在不形成硅氧化膜32A而形成硅氮化膜的情况下,则导入N2或NH4作为功能性气体;而在要形成碳化硅膜的情况下,则导入CH4或C2H6作为功能性气体。再有,不用X射线而用γ射线、光线(可见光、红外光、紫外光、真空紫外光)或者电子射线110进行照射,也可以获得同样的效果。
接着,在保持真空室10内的真空度为10-9乇、保持基片保持台14的温度约为-170℃的状态下,从气体导入部件28导入SiH4气体作为功能气体,同时把紫外线(例如波长185nm)作为电离气体进行照射。这样一来,就在硅氧化膜32A上淀积上丁硅膜33A。
其次,在保持真空室10内的真空度为10-4乇、保持基片保持台14的温度为约-170℃的状态下,向硅膜33A中离子注入杂质(例如磷),使硅膜33A具有导电性。
接着,在保持基片保持台14的温度为约-170℃的状态下,在硅膜33A上边形成光刻胶34之后,以该光刻胶34为掩模对硅膜33A和硅氧化膜32A进行干法刻蚀。以此,如图2(b)所示,形成栅极电极33B和栅极绝缘膜32B。之后,以栅极电极33B为掩模对硅单晶膜31A和P型杂质层30A进行干法刻蚀,用这种办法,如图3(a)所示,形成本征层31B和沟道层30B。
其后,在保持真空室10内的真空度为10-9乇、保持基片保持台14的温度为约-170℃的状态下,从气体导入部件28导入Si2H6作为功能性气体,同时把紫外线(例如波长185nm)作为电离射线进行照射从而生长出硅单晶膜,之后,从气体导入部件28导入O2气体、N2O气体、O2和N2O气体的混合气体或者O3气体作为功能性气体,同时通过同步加速器辐射以50mW/cm2的强度照射波长约为100nm左右的X射线,使上述硅单晶膜氧化形成硅氧化膜。之后,通过对硅氧化膜进行干法腐蚀,如图3(b)所示,在栅极电极33B的各个侧面上形成侧壁35。
此后,在保持真空室10内的真空度为10-9乇、保持基片保持台14的温度为约-170℃的状态下,从气体导入部件28导入SiH4气体作为功能性气体,同时把紫外线(例如波长185nm)用作电离射线进行照射,在半导体基片1上边淀积硅膜之后,向该硅膜离子注入杂质(例如磷),以便硅膜具有导电性,如图3(b)所示,在形成源、漏极电极36后就制得了MOS晶体管。
再者,在源、漏极电极36由例如含硅的铝等金属膜形成时,通过一边在低温下照射适当的电离射线或光线一边导入含有所需金属元素的气体管(包括金属的蒸气)。如以上说明的那样,若采用第3实施例的办法,由于一直是在低温下制造MOS晶体管,故可获得高精度的MOS晶体管而不影响由P型杂质层30A形成的沟道层30B、由硅氧化膜32A形成的栅极绝缘膜32B以及由硅膜33A形成的栅极电极33B的排列状态。
下边,对本发明的第4或第5实施例所涉及的半导体装置的制造方法进行说明。由于一般说来感光性光刻胶耐热性低,故现有技术不可能利用在半导体基片上形成的光刻胶在半导体基片上进行外延生长。然而,如果一边照射电离射线或光线一边进行外延生长,则即使在低温下,例如在低于250℃的低温下,也可以良好地进行外延生长。以下,对在第4实施例中用在整个面上进行外延生长的覆盖生长法形成外延膜的情况进行说明,并对在第5实施例中用选择生长法形成外延膜的情况进行说明。
首先第4和第5实施例中所用的光刻胶材料。在上述两实施例中所用的光刻胶材料以酚醛树脂、亚硝基系树脂、苯酚系树脂、苯乙烯系树脂、苯乙烯顺丁烯二酸系树脂、或者四甲基铵氢化氧化物(tetra-methyl-anmonium-hydro-oxide)等树脂为基料,再给该基料配以感光剂。
以下,参照图4对本发明的第4实施例所涉及的半导体装置的制造方法进行说明。而且,在第4实施例中,真空室10内的真空度、基片保持台14的温度以及从气体导入部件28导入的功能性气体的种类和第1-第3实施例基本相同,故略去对它们的说明。
首先,如图4所示,在真空和低温下,于半导体基片1上形成由上述光刻胶材料组成且在指定区域有开口部位40a的光刻胶40。
接着,在真空和低温下对半导体基片1照射电离射线或者光线,同时在半导体基片1上进行覆盖外延生长。这样一来,就在面对半导体基片1上光刻胶40的开口部位40a的区域上形成了由所需单晶组成的外延生长膜41,但是在光刻胶40的上边却并不生长单晶,而是附着有由功能性气体中所含成分形成的淀积物。
接着,用CMP、化学机械研磨而除掉光刻胶40上边的淀积物42。如此,如图4(c)所示,光刻胶40就露了出来,故用例如氧等离子体把露出来的光刻胶灰化后除掉。这样,如图4(d)所示,仅仅在面对半导体基片1上的光刻胶40的开口部位40a的区域上留下了外延生长膜。因此,若应用第4实施例,就可以把光刻胶40用作选择工艺的掩模材料,在低温下选择性地外延生长单晶。
再有,在把X射线或伽玛射线用作电离射线或者光线的情况下,理想的情况是把具有与进行照射的能量相对应的吸收端的金属混入光刻胶材料中使之发挥掩模效果。
下边,参照图5对本发明的第5实施例所涉及的半导体装置的制造方法进行说明。在第5实施例中,真空室10内的真空度、基片保持台14的温度以及从气体导入部件28导入的功能性气体的种类等和第1-第3实施例基本上相同,故免予说明。
首先,如图5(a)所示,在半导体基片1的上边形成由上述光刻胶材料组成且在指定区域上具有开口部位40a的光刻胶40之后,一边在真空和低温下照射电离射线或光线,一边在半导体基片1上选择性地进行外延生长。这样,如图5(b)所示,就仅仅在面对半导体基片1上的光刻胶40的开口部位40a的区域上形成了由单晶组成的外延生长膜41。
接着,在用例如氧等离子体灰化除掉光刻胶40后,如图5(c)所示,就仅在面对半导体基片1上边的光刻胶40的开口部位40a的区域上留下了外延生长膜41。于是,若应用第5实施例的方法,就可以把光刻胶40用作选择工序的掩模材料并在低温下选择性地生长单晶。
下边,参照图6对本发明的第6实施例所涉及的半导体装置的制造方法进行说明。
还有,在第6实施例中,真空室10内的真空度、基片保持台14的温度以及从气体导入部件28导入的功能性气体的种类基本上和第1-第3实施例相同,故免予说明。
首先,如图6a所示,在真空和低温下一边照射电离射线或光线一边导入工艺所需的功能性气体45,同时,对在半导体基片1上将要形成杂质层、氧化膜或者电极的区域用电子束(EB)曝光机照射电子束46。这样,仅在半导体基片1的表面上被电子束照射过的区域上发生构成半导体基片1的材料和功能性气体45的成分的反应,并如图6(b)所示,形成了所希望的杂质层、氧化膜或者电极图形47。
在第6实施例中,由于用电子束46对半导体基片1进行局部性地激励,所以可在低温下形成膜,在低温下形成膜是本发明的特征。
Claims (6)
1.半导体装置的制造方法,包括:
图形化膜形成工序,用于在低于250℃的温度下通过一边在有杂质层的半导体基片上照射电子束一边导入功能性气体,在上述半导体基片上形成图象化膜。
2.半导体装置的制造方法,包括:
图形化层形成工序,用于通过在低于250℃的温度下一边向半导体基片上照射电子束一边导入功能性气体,在半导体基片上形成由与半导体基片的主要成分不同的原子或分子组成的图形化层。
3.半导体装置的制造方法,包括下列步骤:
通过在低于250℃的温度下一边向半导体基片照射电离射线或光线、一边导入功能性气体而在半导体基片上形成将成为沟道区的杂质层的工序;
通过在低于250℃的温度下一边向半导体基片照射电离射线或光线、一边导入功能性气体而在上述杂质层上边形成将成为栅极绝缘膜的绝缘层的工序;
通过在低于250℃的温度下一边向半导体基片照射电离射线或光线、一边导入功能性气体而在上述绝缘层上形成将成为栅极电极的导电层的工序;
在低于250℃的温度下,在上述导电层的上边形成覆盖栅极形成区的光刻胶图形的工序;
在低于250℃的温度下,通过以上述光刻胶图形为掩模对上述导电层进行刻蚀形成由上述导电层构成的栅极电极和由上述绝缘层构成的栅极绝缘膜的工序;
在低于250℃的温度下,通过以上述栅极电极为掩模对上述杂质层进行刻蚀形成由上述杂质层构成的沟道区的工序;和
在低于250℃的温度下,通过一边向半导体基片照射电离射线或光线一边导入功能性气体而在半导体基片上的上述沟道区两侧形成源极电极和漏极电极的工序。
4.半导体装置的制造方法,包括下述工序:
在半导体基片上形成光刻胶图形的光刻胶图形形成工序;
在低于250℃的温度下,通过一边向半导体基片照射X射线或γ射线一边导入功能性气体而在未形成上述光刻胶图形区域处的半导体基片上形成外延生长膜的生长膜形成工序;
通过除去上述光刻胶图形形成由上述外延生长膜构成的图形化生长膜的生长膜图形形成工序。
5.半导体装置的制造方法,包括下述步骤:
在低于250℃的温度下,通过一边向有杂质层的半导体基片照射X射线或γ射线一边在上述半导体基片上导入功能性气体而在上述半导体基片上形成膜。
6.半导体装置的制造方法,包括下述工序:
在低于250℃的温度下,通过一边向半导体基片照射X射线或γ射线一边在上述半导体基片上导入功能性气体而在上述半导体基片上形成层。
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EP (1) | EP0684632B1 (zh) |
JP (1) | JP2771472B2 (zh) |
KR (1) | KR0175430B1 (zh) |
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JP2771472B2 (ja) * | 1994-05-16 | 1998-07-02 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP3599290B2 (ja) | 1994-09-19 | 2004-12-08 | 株式会社ルネサステクノロジ | 半導体装置 |
KR100368318B1 (ko) * | 2000-12-29 | 2003-01-24 | 주식회사 하이닉스반도체 | 반도체 소자의 선택적 에피택셜 성장법 |
US8563410B2 (en) * | 2009-11-25 | 2013-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | End-cut first approach for critical dimension control |
CN102651312B (zh) * | 2011-02-24 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | 栅极的形成方法 |
US10755913B2 (en) | 2017-07-18 | 2020-08-25 | Duke University | Package comprising an ion-trap and method of fabrication |
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- 1995-05-16 EP EP95107485A patent/EP0684632B1/en not_active Expired - Lifetime
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US6169004B1 (en) | 2001-01-02 |
US5817559A (en) | 1998-10-06 |
CN1121260A (zh) | 1996-04-24 |
EP0684632A3 (en) | 1998-04-15 |
EP0684632B1 (en) | 2007-12-12 |
JPH0837159A (ja) | 1996-02-06 |
KR0175430B1 (ko) | 1999-04-01 |
DE69535661D1 (de) | 2008-01-24 |
JP2771472B2 (ja) | 1998-07-02 |
EP0684632A2 (en) | 1995-11-29 |
KR950034591A (ko) | 1995-12-28 |
DE69535661T2 (de) | 2008-05-21 |
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