KR950025961A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

Info

Publication number
KR950025961A
KR950025961A KR1019950002335A KR19950002335A KR950025961A KR 950025961 A KR950025961 A KR 950025961A KR 1019950002335 A KR1019950002335 A KR 1019950002335A KR 19950002335 A KR19950002335 A KR 19950002335A KR 950025961 A KR950025961 A KR 950025961A
Authority
KR
South Korea
Prior art keywords
semiconductor device
chip
base
circuit board
thin film
Prior art date
Application number
KR1019950002335A
Other languages
English (en)
Other versions
KR0169187B1 (ko
Inventor
시게하루 츠노다
준이치 사에키
이사무 요시다
가즈야 오오지
미치하루 혼다
마코토 기타노
나에 요네다
슈지 에구치
구니히코 니시
이치로 안죠
겐이치 오츠카
Original Assignee
가나이 쓰토무
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가나이 쓰토무
Publication of KR950025961A publication Critical patent/KR950025961A/ko
Application granted granted Critical
Publication of KR0169187B1 publication Critical patent/KR0169187B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Abstract

반도체 플라스틱 페케지, 특히 바람직한 페케지 구조와 BGA 페케지의 제조방법에 관한 것이다. 반도체부 즉, IC칩, 회로기판 또는 회로박막을 고정 지지하는 지지프레임은 외부단자의 각각에 해당하는 위치에서 하나에 복수의 돌출부를 가지는 하부 금형하프와 상부 금형하프로 구성되는 금형을 사용하는 수지로 밀봉되는 수지밀봉 BGA페케지가 있다. 금형은 분할소자 사이의 환기구를 가지는 분할 구조로 되어 있다.

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 제1실시예에의 BGA 페케지 구조의 일단 파단 사시도,
제2A도는지지 리이드 프레임과 IC칩 및 회로기판 의 다층셋트를 조립하기 위한 프로세스를 나타낸는 플로워 차트이고, 제2B도는 조립프로세스와 그결과 생기는 페케지를 나타내는 도면.

Claims (34)

  1. IC칩과, 상기 IC칩에 실장되고 접촉되는 베이스와, 외부로 상기 IC칩을 접속하기 위하여 상기 베이스 상에 배열된 복수의 단자와, 사기 복수단자의 각각에 하나씩 형성되는 복수의 금속 범프와, 상기 베이스 또는 상기 IC칩을 고정되게 지지하기 위한 지지프레임을 구비하고, 상기 베이스는 회로기판 또는 절연베이스상에 형성된 회로 패턴을 가지는 회로박막을 포함하는 반도체 장치.
  2. 제1항에 있어서, 상기 지지프레임은 금속재로 만들어진 반도체 장치.
  3. 제2항에 있어서, 상기 지지프레임은 외부림과, 상기 IC칩과 기판을 지지하기 위하여 상기 외부림과 분리되고 상기 외부림의 내부에 배열되는 지지부와, 상기 외부림과 지지부를 접속하기 위한 복수의 접속부를 구비하는 반도체장치.
  4. 제3항에 있어서, 상기 외부림은 방열기로 사용되는 반도체 장치.
  5. 제3항에 있어서, 상기 지지프레임의 상기 복수의 접속부는 상기 외부림이 잘려질 때 잘려지게 되는 절단부를 구성하는 반도체 장치.
  6. 제1항에 있어서, 상기 베이스는 본딩와이어를 통해서 상기 IC칩에 접속되는 회로기판을 구비하는 반도체 장치.
  7. 제1항에 있어서, 상기 베이스는 상기 회로박막을 구비하고, 상기 회로박막은 상기IC칩으로 금속이나 도전성 지에 의해 접속되도록 한 반도체 장치.
  8. 제1항에 있어서, 상기 반도체장치는 유기재로 부분적으로 밀봉되는 반도체 장치.
  9. 제8항에 있어서, 상기 베이스는 회로기판을 구비하는 반도체 장치.
  10. 제9항에 있어서, 상기 IC칩과, 상기 IC칩이 실장되고 전기적으로 접속되는 상기 회로기판의 표면과, 상기 회로기판의 측부와, 상기 금속범프가 배열되는 상기 회로기판의 표면을 포함하는 상기 반도체 장치의 전체는 상기 복수의 단자를 제외하고는 수지로 밀봉되는 반도체 장치.
  11. 제9항에 있어서, 상기 IC칩과, 상기 IC칩이 실장되고 전기적으로 접속되는 상기 회로기판의 표면과, 상기 회로기판의 측부를 포함하는 상기 반도체 장치의 전체는 상기 복수의 단자와 상기 복수의 단자가 배열된 상기 회로기판의 표면을 제외하고는 수지로 밀봉되는 반도체 장치.
  12. 제9항에 있어서, 상기 IC칩과, 상기 IC칩이 전기적으로 접속되는 상기 회로기판의 표면과을 포함하는 상기 반도체 장치의 전체는 상기 복수의 단자와, 상기 복수의 단자상에 배열된 상기 기판의 표면 및 상기 회로기판의 측부를 제외하고는 수지로 밀봉되는 반도체 장치.
  13. 제1항에 있어서, 상기 베이스 회로박막을 구비하는 반도체장치.
  14. 제13항에 있어서, 상기 IC칩과, 상기 IC칩이 전기적으로 접속되는 상기 박막의 표면과, 상기 복수의 단자에 배열된 상기 박막의 표면을 포함하는 상기 반도체 장치의 전체는 상기 복수의 단자를 제외하고는 수지로 밀봉되는 반도체 장치.
  15. 제13항에 있어서, 상기 IC칩과, 상기 IC칩이 전기적으로 접속되는 상기 회로박막과 상기 IC칩이 서로 접합되는 부분을 포함하는 상기 반도체 장치의 전체는 상기 복수의 단자와 상기 복수의 단자에 배열된 상기 회로박막의 표면을 제외하고는 수지로 밀봉되는 반도체 장치.
  16. IC칩과, 상기 IC칩과 대향하고, 상기 IC칩으로 복수의 전기 접속부를 가지는 제1면과, 복수의 단자가 배열되고 각 단자는 와이어 도선을 통하여 상기 복수의 전기접속부의 상응하는 하나와 접속되는 제2면과, 측면을 가지는 베이스와, 상기 복수 단자 각각에 형성되는 복수의 금속범프와, 상기 베이스 또는 상기 IC칩을 고정 지지하는 지지프레임과, 적어도 상기 IC칩과 상기 베이스의 제1면을 밀봉하는 밀봉재를 구비하고, 적어도 상기 금속 범프가 밀봉되지 않게 노출되도록 한 반도체 장치.
  17. 제16항에 있어서, 상기 베이스는 회로기판 또는 회로박막으로 만들어지는 반도체 장치.
  18. 제16항에 있어서, 상기 지지프레임은 금속재로 만들어지는 반도체 장치.
  19. 제18항에 있어서, 상기 지지프레임은 림과, 상기 베이스 및 상기 IC칩 중 적어도 하나를 지지하기 위하여 상기 외부림과 분리되고 내측에 배열된 지지부와, 상기 외부림과 지지부를 접속하기 위한 복수의 접속부를 구비하여 일체로 형성된 구조부재인 반도체 장치.
  20. 제19항에 있어서, 상기 외부림은 노출되어 있고 방열기로 작동하게한 반도체 장치.
  21. 제19항에 있어서, 상기 지지프레임의 상기 복수의 접속부는 상기 외부림이 절단될 때 절단되도록 한 절단부를 구성하는 반도체 장치.
  22. 제16항에 있어서, 상기 베이스는 본딩와이어를 통해서 상기 IC칩에 접속되는 회로기판을 구비하는 반도체 장치.
  23. 제16항에 있어서, 상기 베이스는 상기 IC칩에 금속 또는 도전성 수지에 의해 접속되는 회로박막을 구비하는 반도체 장치.
  24. 제16항에 있어서, 상기 밀봉재는 유기재료를 구비하는 반도체 장치.
  25. 제16항에 있어서, 상기 베이스는 회로기판을 구비하며, 상기 밀봉재료는 상기 회로기판의 제2면과 노출되어 있는 상기 범프와 같이 상기 회로기판을 그 측부에 까지 밀봉되도록 한 반도체 장치.
  26. 제16항에 있어서, 상기 베이스는 회로기판을 구비하며, 상기 밀봉재료는 상기 노출되어 있는 상기 범프와 같이 상기 회로기판의 상기 제2면 까지 밀봉되도록 한 반도체 장치
  27. 제16항에 있어서, 상기 베이스는 회로박막 구비하며, 상기 밀봉재료는 상기 IC칩과 상기 회로박막의 제1면과 상기 IC칩이 접합하는 부분을, 상기 회로박막의 상기 제2면과 노출되어 있는 상기 범프와 같이 밀봉하도록 한 반도체 장치.
  28. 제27항에 있어서, 상기 밀봉재료는 상기 노출되어 있는 범프와 같이 상기 회로박막의 상기 제2면까지 밀봉하도록 한 반도체 장치.
  29. 지지프레임상에 IC칩과 회로기판이나 회로박막을 포함하는 베이스를 실징하는 스텝과, 접속장치의 수단에의해 IC칩과 베이스를 전기적으로 접속하는 스텝과, IC칩과, 베이스 및 지지프레임의 조립체의 소정 부분을 유기 수지로 충전 및 밀봉하는 스텝과, 베이스 상에 배열된 복수 외부접속단자의 각 단자에 복수의 솔더범프의 하나를 각각 형성하는 스텝을 구비하는 반도체장치의 제조방법.
  30. 제29항에 있어서, 충전 및 밀봉스텝은 금형으로 행해지는 반도체장치의 제조방법.
  31. 제30항에 있어서, 금형은 상부 금형과 하부금형으로 구성되며, 상기 하부 및 상부 금형이 그들 사이에 조립체를 보지할 때, 수지가 캐비티안으로 흘러가도록 캐비티가 IC칩의 측부와 외부접속단자의 측부상의 조립체위에 형성되는 리세스를 상기 하부 및 상부금형 각각이 가지도록 하고, 상기 밀봉단계는 ; IC칩과 베이스가 실장되는 지지프레임을 상부 및 하부 금형 사이에 보지하는 스텝과, 수지를 캐비티내로 주입시키는 스텝을 구비하고, 하부금형은 복수의 외부접속단자에 수지가 부착되는 것을 피하고 금속범프의 각각을 위한 공간을 확보하도록 상기 리세스 내에, 복수의 외부접속단자의 각각에 대하여 하나씩 해당되게, 복수개의 돌출부를 가지도록 한 반도체 장치의 제조방법.
  32. 제31항에 있어서, 돌출부가 배열된 하부 금형의 일부는 서로 겹치는 복수의 블록을 포함하고, 각 블록은 어느 두 개의 블럭이 인접하는 적어도 하나의 경계에 형성되는 환기구와 함께 외부 접속단자에 상당하는 돌출부를 가지도록 한 반도체 장치의 제조방법.
  33. 제31항에 있어서, 하부금형 내에 설치된 돌출부의 각 상면이 탄성 플라스틱재료에 의해 덮혀지도록 한 반도체 장치의 제조방법.
  34. 제31항에 있어서, 하부 금형내에 설치된 돌출부의 각 상면이 금형 방출제에 의해 덮혀지도록 한 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950002335A 1994-02-10 1995-02-09 반도체장치 및 그 제조방법 KR0169187B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1610594 1994-02-10
JP94-16105 1994-02-10

Publications (2)

Publication Number Publication Date
KR950025961A true KR950025961A (ko) 1995-09-18
KR0169187B1 KR0169187B1 (ko) 1999-01-15

Family

ID=11907244

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950002335A KR0169187B1 (ko) 1994-02-10 1995-02-09 반도체장치 및 그 제조방법

Country Status (5)

Country Link
US (2) US5914531A (ko)
KR (1) KR0169187B1 (ko)
CN (2) CN1132236C (ko)
MY (1) MY115170A (ko)
TW (1) TW344109B (ko)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686226B1 (en) 1994-02-10 2004-02-03 Hitachi, Ltd. Method of manufacturing a semiconductor device a ball grid array package structure using a supporting frame
TW344109B (en) * 1994-02-10 1998-11-01 Hitachi Ltd Methods of making semiconductor devices
US20040061220A1 (en) * 1996-03-22 2004-04-01 Chuichi Miyazaki Semiconductor device and manufacturing method thereof
JP2891665B2 (ja) * 1996-03-22 1999-05-17 株式会社日立製作所 半導体集積回路装置およびその製造方法
US5738531A (en) * 1996-09-09 1998-04-14 International Business Machines Corporation Self-alligning low profile socket for connecting ball grid array devices through a dendritic interposer
JP2924840B2 (ja) * 1997-02-13 1999-07-26 日本電気株式会社 Ｔａｐｅ−ＢＧＡタイプの半導体装置
US6001672A (en) 1997-02-25 1999-12-14 Micron Technology, Inc. Method for transfer molding encapsulation of a semiconductor die with attached heat sink
JP3532395B2 (ja) * 1997-10-03 2004-05-31 株式会社ルネサステクノロジ 半導体装置の製造方法、プレス金型、ガイドレール
JP3310617B2 (ja) * 1998-05-29 2002-08-05 シャープ株式会社 樹脂封止型半導体装置及びその製造方法
JPH11354689A (ja) * 1998-06-04 1999-12-24 Oki Electric Ind Co Ltd フレーム状基板とその製造方法及び半導体装置の製造方法
JP3842447B2 (ja) * 1998-08-17 2006-11-08 シチズン時計株式会社 Ｉｃの実装構造
JP3492212B2 (ja) * 1998-08-26 2004-02-03 新光電気工業株式会社 半導体装置用パッケージ及びその製造方法
US6034425A (en) * 1999-03-17 2000-03-07 Chipmos Technologies Inc. Flat multiple-chip module micro ball grid array packaging
US6329220B1 (en) 1999-11-23 2001-12-11 Micron Technology, Inc. Packages for semiconductor die
US6949822B2 (en) * 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
US6856006B2 (en) * 2002-03-28 2005-02-15 Siliconix Taiwan Ltd Encapsulation method and leadframe for leadless semiconductor packages
JP4329235B2 (ja) * 2000-06-27 2009-09-09 セイコーエプソン株式会社 半導体装置及びその製造方法
IT1318257B1 (it) * 2000-07-27 2003-07-28 St Microelectronics Srl Lead-frame per dispositivi a semiconduttore.
US6559537B1 (en) * 2000-08-31 2003-05-06 Micron Technology, Inc. Ball grid array packages with thermally conductive containers
US6838319B1 (en) * 2000-08-31 2005-01-04 Micron Technology, Inc. Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically
JP3619773B2 (ja) * 2000-12-20 2005-02-16 株式会社ルネサステクノロジ 半導体装置の製造方法
FR2820240B1 (fr) * 2001-01-26 2004-07-16 St Microelectronics Sa Substrat support de puce a circuits integres adapte pour etre place dans un moule
JP4626919B2 (ja) * 2001-03-27 2011-02-09 ルネサスエレクトロニクス株式会社 半導体装置
US7220615B2 (en) * 2001-06-11 2007-05-22 Micron Technology, Inc. Alternative method used to package multimedia card by transfer molding
JP3456983B2 (ja) * 2001-06-27 2003-10-14 松下電器産業株式会社 リードフレームおよび樹脂封止型半導体装置の製造方法
CN100532059C (zh) * 2001-08-22 2009-08-26 索尼公司 用于形成模块化电子器件的方法和装置以及模块化电子器件
US6891276B1 (en) * 2002-01-09 2005-05-10 Bridge Semiconductor Corporation Semiconductor package device
JP2004055480A (ja) * 2002-07-24 2004-02-19 Pioneer Electronic Corp フラットディスプレイパネル
WO2004097896A2 (en) * 2003-04-26 2004-11-11 Freescale Semiconductor, Inc. A packaged integrated circuit having a heat spreader and method therefor
DE10323296A1 (de) * 2003-05-21 2005-01-05 Infineon Technologies Ag Anordnung zur Stress-Reduzierung bei substratbasierten Chip-Packages
US7144538B2 (en) * 2003-06-26 2006-12-05 Semiconductor Components Industries, Llc Method for making a direct chip attach device and structure
KR100765604B1 (ko) * 2004-11-26 2007-10-09 산요덴키가부시키가이샤 회로 장치 및 그 제조 방법
BRPI0419216A (pt) * 2004-11-30 2007-12-18 Ap Moeller Maersk As método e sistema para redução de consumo de combustìvel em um motor a diesel
JP2007081232A (ja) * 2005-09-15 2007-03-29 Renesas Technology Corp 半導体装置の製造方法
JP2007179176A (ja) * 2005-12-27 2007-07-12 Disco Abrasive Syst Ltd 配線基板及びメモリーカードの製造方法
US7440282B2 (en) * 2006-05-16 2008-10-21 Delphi Technologies, Inc. Heat sink electronic package having compliant pedestal
TWI309879B (en) * 2006-08-21 2009-05-11 Advanced Semiconductor Eng Reinforced package and the stiffener thereof
JP5259197B2 (ja) * 2008-01-09 2013-08-07 ソニー株式会社 半導体装置及びその製造方法
TWI466242B (zh) * 2009-01-05 2014-12-21 Nanya Technology Corp 具有護桿的半導體封裝體結構
US8072764B2 (en) * 2009-03-09 2011-12-06 Apple Inc. Multi-part substrate assemblies for low profile portable electronic devices
CN102148175A (zh) * 2011-01-05 2011-08-10 无锡市玉祁红光电子有限公司 半导体芯片模板结构
JP5484529B2 (ja) * 2012-08-07 2014-05-07 ホシデン株式会社 部品モジュール及び部品モジュールの製造方法
US9067342B2 (en) * 2012-09-26 2015-06-30 Intel Corporation Mold chase for integrated circuit package assembly and associated techniques and configurations
TWI688054B (zh) * 2017-06-05 2020-03-11 日月光半導體製造股份有限公司 封裝模具及半導體封裝製程
JP2020004840A (ja) * 2018-06-28 2020-01-09 アルパイン株式会社 電子ユニットおよびその製造方法
CN111465169A (zh) * 2020-03-25 2020-07-28 万安裕维电子有限公司 一种防翘曲pcb板
CN111465312A (zh) * 2020-04-14 2020-07-28 杭州洛微科技有限公司 基于周期性阵列排布的光电产品封装生产方法
US11387213B2 (en) * 2020-06-05 2022-07-12 Advanced Semiconductor Engineering, Inc. Method for manufacturing a semiconductor package

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6146049A (ja) * 1984-08-10 1986-03-06 Hitachi Ltd 半導体装置
JPS62277753A (ja) * 1986-05-27 1987-12-02 Sumitomo Electric Ind Ltd 半導体パツケ−ジ
US4899207A (en) * 1986-08-27 1990-02-06 Digital Equipment Corporation Outer lead tape automated bonding
US4891687A (en) * 1987-01-12 1990-01-02 Intel Corporation Multi-layer molded plastic IC package
JPH0732215B2 (ja) * 1988-10-25 1995-04-10 三菱電機株式会社 半導体装置
JPH02309660A (ja) * 1989-05-24 1990-12-25 Shinko Electric Ind Co Ltd リードフレーム
JP2875334B2 (ja) * 1990-04-06 1999-03-31 株式会社日立製作所 半導体装置
US5293072A (en) * 1990-06-25 1994-03-08 Fujitsu Limited Semiconductor device having spherical terminals attached to the lead frame embedded within the package body
US5148265A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
JP2977889B2 (ja) * 1990-11-20 1999-11-15 シチズン時計株式会社 Ｉｃの樹脂封止方法
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5332864A (en) * 1991-12-27 1994-07-26 Vlsi Technology, Inc. Integrated circuit package having an interposer
JP3572628B2 (ja) * 1992-06-03 2004-10-06 セイコーエプソン株式会社 半導体装置及びその製造方法
JP2670408B2 (ja) * 1992-10-27 1997-10-29 株式会社東芝 樹脂封止型半導体装置及びその製造方法
JPH06146049A (ja) * 1992-10-30 1994-05-27 Kobe Steel Ltd チタン等の高融点な活性金属の溶融塩電解採取方法
US5294827A (en) * 1992-12-14 1994-03-15 Motorola, Inc. Semiconductor device having thin package body and method for making the same
US5360991A (en) * 1993-07-29 1994-11-01 At&T Bell Laboratories Integrated circuit devices with solderable lead frame
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
US5991156A (en) * 1993-12-20 1999-11-23 Stmicroelectronics, Inc. Ball grid array integrated circuit package with high thermal conductivity
TW344109B (en) * 1994-02-10 1998-11-01 Hitachi Ltd Methods of making semiconductor devices
US5541450A (en) * 1994-11-02 1996-07-30 Motorola, Inc. Low-profile ball-grid array semiconductor package

Also Published As

Publication number Publication date
US6114192A (en) 2000-09-05
CN1290165C (zh) 2006-12-13
KR0169187B1 (ko) 1999-01-15
US5914531A (en) 1999-06-22
TW344109B (en) 1998-11-01
MY115170A (en) 2003-04-30
CN1489192A (zh) 2004-04-14
CN1113035A (zh) 1995-12-06
CN1132236C (zh) 2003-12-24

Similar Documents

Publication Publication Date Title
KR950025961A (ko) 반도체장치 및 그 제조방법
US5650593A (en) Thermally enhanced chip carrier package
US4079511A (en) Method for packaging hermetically sealed integrated circuit chips on lead frames
KR100190981B1 (ko) 편면수지 봉지형 반도체장치의 제조방법 및 이에 사용되는 캐리어 프레임
EP0333374B1 (en) Edge-mounted, surface-mount package for semiconductor integrated circuit devices
CA1040747A (en) Integrated circuit package utilizing novel heat sink structure
US5275975A (en) Method of making a relatively flat semiconductor package having a semiconductor chip encapsulated in molded material
US5483740A (en) Method of making homogeneous thermoplastic semi-conductor chip carrier package
CA1266725A (en) Integrated circuit chips mounting and packaging assembly
JP3672280B2 (ja) スルーホール電極付き電子部品の製造方法
GB2286084A (en) Electronic package with thermally conductive support
KR980006193A (ko) 열적 개량된 플립 칩 패키지 및 그 제조 방법
KR950004467A (ko) 반도체장치 및 그 제조방법
JPH01315166A (ja) プラスチック封入材を用いた集積回路パッケージ
KR970067788A (ko) 반도체장치와 그 제조방법 및 기판프레임
JPH02122557A (ja) ピン格子配列集積回路パッケージ
KR910003542B1 (ko) 수지밀폐형소자 및 그 제조방법
JPH1174420A (ja) 表面実装型チップ部品及びその製造方法
KR940027140A (ko) 플라스틱 성형 회로 패키지
JP4334335B2 (ja) 混成集積回路装置の製造方法
US5445995A (en) Method for manufacturing plastic-encapsulated semiconductor devices with exposed metal heat sink
JP2005191147A (ja) 混成集積回路装置の製造方法
KR100237895B1 (ko) 저가 수지 몰드 반도체 장치
JPH03280453A (ja) 半導体装置及びその製造方法
JP2002100710A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101007

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee