FR2820240B1 - Substrat support de puce a circuits integres adapte pour etre place dans un moule - Google Patents

Substrat support de puce a circuits integres adapte pour etre place dans un moule

Info

Publication number
FR2820240B1
FR2820240B1 FR0101096A FR0101096A FR2820240B1 FR 2820240 B1 FR2820240 B1 FR 2820240B1 FR 0101096 A FR0101096 A FR 0101096A FR 0101096 A FR0101096 A FR 0101096A FR 2820240 B1 FR2820240 B1 FR 2820240B1
Authority
FR
France
Prior art keywords
placement
mold
integrated circuits
support substrate
chip support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0101096A
Other languages
English (en)
Other versions
FR2820240A1 (fr
Inventor
Christophe Prior
Laurent Herard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0101096A priority Critical patent/FR2820240B1/fr
Priority to PCT/FR2002/000297 priority patent/WO2002059959A1/fr
Priority to US10/470,320 priority patent/US7288843B2/en
Publication of FR2820240A1 publication Critical patent/FR2820240A1/fr
Application granted granted Critical
Publication of FR2820240B1 publication Critical patent/FR2820240B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
FR0101096A 2001-01-26 2001-01-26 Substrat support de puce a circuits integres adapte pour etre place dans un moule Expired - Fee Related FR2820240B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0101096A FR2820240B1 (fr) 2001-01-26 2001-01-26 Substrat support de puce a circuits integres adapte pour etre place dans un moule
PCT/FR2002/000297 WO2002059959A1 (fr) 2001-01-26 2002-01-24 Substrat support de puce a circuits integres adapte pour etre place dans un moule
US10/470,320 US7288843B2 (en) 2001-01-26 2002-01-24 Integrated circuit chip support substrate for placing in a mold, and associated method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0101096A FR2820240B1 (fr) 2001-01-26 2001-01-26 Substrat support de puce a circuits integres adapte pour etre place dans un moule

Publications (2)

Publication Number Publication Date
FR2820240A1 FR2820240A1 (fr) 2002-08-02
FR2820240B1 true FR2820240B1 (fr) 2004-07-16

Family

ID=8859292

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0101096A Expired - Fee Related FR2820240B1 (fr) 2001-01-26 2001-01-26 Substrat support de puce a circuits integres adapte pour etre place dans un moule

Country Status (3)

Country Link
US (1) US7288843B2 (fr)
FR (1) FR2820240B1 (fr)
WO (1) WO2002059959A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2820240B1 (fr) 2001-01-26 2004-07-16 St Microelectronics Sa Substrat support de puce a circuits integres adapte pour etre place dans un moule
US7618249B2 (en) * 2006-09-22 2009-11-17 Asm Technology Singapore Pte Ltd. Memory card molding apparatus and process
US7732937B2 (en) * 2008-03-04 2010-06-08 Infineon Technologies Ag Semiconductor package with mold lock vent
US9129978B1 (en) 2014-06-24 2015-09-08 Stats Chippac Ltd. Integrated circuit packaging system with void prevention mechanism and method of manufacture thereof
CN108987292B (zh) * 2017-06-05 2022-07-08 日月光半导体制造股份有限公司 封装模具和半导体封装制程

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
TW344109B (en) * 1994-02-10 1998-11-01 Hitachi Ltd Methods of making semiconductor devices
FR2764111A1 (fr) * 1997-06-03 1998-12-04 Sgs Thomson Microelectronics Procede de fabrication de boitiers semi-conducteurs comprenant un circuit integre
US6081997A (en) * 1997-08-14 2000-07-04 Lsi Logic Corporation System and method for packaging an integrated circuit using encapsulant injection
JPH11121488A (ja) * 1997-10-15 1999-04-30 Toshiba Corp 半導体装置の製造方法及び樹脂封止装置
JP2954148B1 (ja) * 1998-03-25 1999-09-27 松下電子工業株式会社 樹脂封止型半導体装置の製造方法およびその製造装置
JPH11297921A (ja) * 1998-04-14 1999-10-29 Mitsubishi Electric Corp 半導体装置用フレームおよびその製造方法並びに半導体装置用フレームを用いた半導体装置の製造方法
US6413801B1 (en) * 2000-05-02 2002-07-02 Advanced Semiconductor Engineering, Inc. Method of molding semiconductor device and molding die for use therein
FR2809228B1 (fr) * 2000-05-22 2003-10-17 St Microelectronics Sa Moule d'injection pour la fabrication d'un boitier semi- conducteur optique et boitier semi-conducteur optique
US6838319B1 (en) * 2000-08-31 2005-01-04 Micron Technology, Inc. Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically
US6632704B2 (en) * 2000-12-19 2003-10-14 Intel Corporation Molded flip chip package
FR2820240B1 (fr) 2001-01-26 2004-07-16 St Microelectronics Sa Substrat support de puce a circuits integres adapte pour etre place dans un moule
TW486793B (en) * 2001-05-29 2002-05-11 Siliconware Precision Industries Co Ltd Packaging method for preventing a low viscosity encapsulant from flashing
JP3456983B2 (ja) * 2001-06-27 2003-10-14 松下電器産業株式会社 リードフレームおよび樹脂封止型半導体装置の製造方法
JP2003077946A (ja) * 2001-08-31 2003-03-14 Hitachi Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
US20040075191A1 (en) 2004-04-22
US7288843B2 (en) 2007-10-30
WO2002059959A1 (fr) 2002-08-01
FR2820240A1 (fr) 2002-08-02

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20070930