FI20010401A - Monikerroksinen integroitu substraatti ja menetelmä monikerroksisen keraamisen elementin valmistamiseksi - Google Patents

Monikerroksinen integroitu substraatti ja menetelmä monikerroksisen keraamisen elementin valmistamiseksi Download PDF

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Publication number
FI20010401A
FI20010401A FI20010401A FI20010401A FI20010401A FI 20010401 A FI20010401 A FI 20010401A FI 20010401 A FI20010401 A FI 20010401A FI 20010401 A FI20010401 A FI 20010401A FI 20010401 A FI20010401 A FI 20010401A
Authority
FI
Finland
Prior art keywords
multilayer
manufacturing process
ceramic element
integrated substrate
multilayer ceramic
Prior art date
Application number
FI20010401A
Other languages
English (en)
Swedish (sv)
Other versions
FI118623B (fi
FI20010401A0 (fi
Inventor
Norio Sakai
Kazuhiro Iida
Original Assignee
Murata Manufacturing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co filed Critical Murata Manufacturing Co
Publication of FI20010401A0 publication Critical patent/FI20010401A0/fi
Publication of FI20010401A publication Critical patent/FI20010401A/fi
Application granted granted Critical
Publication of FI118623B publication Critical patent/FI118623B/fi

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/0909—Preformed cutting or breaking line
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/302—Bending a rigid substrate; Breaking rigid substrates by bending
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49789—Obtaining plural product pieces from unitary workpiece
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49789—Obtaining plural product pieces from unitary workpiece
    • Y10T29/4979—Breaking through weakened portion

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
FI20010401A 2000-03-03 2001-02-28 Integroitu monikerrossubstraatti ja menetelmä keraamisen monikerroselementin ja keraamisen elementin valmistamiseksi FI118623B (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000058600 2000-03-03
JP2000058600A JP3700524B2 (ja) 2000-03-03 2000-03-03 多層集合基板および多層セラミック部品の製造方法

Publications (3)

Publication Number Publication Date
FI20010401A0 FI20010401A0 (fi) 2001-02-28
FI20010401A true FI20010401A (fi) 2001-09-04
FI118623B FI118623B (fi) 2008-01-15

Family

ID=18579175

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20010401A FI118623B (fi) 2000-03-03 2001-02-28 Integroitu monikerrossubstraatti ja menetelmä keraamisen monikerroselementin ja keraamisen elementin valmistamiseksi

Country Status (5)

Country Link
US (2) US6621010B2 (fi)
JP (1) JP3700524B2 (fi)
CN (1) CN1165209C (fi)
FI (1) FI118623B (fi)
SE (1) SE524327C2 (fi)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4664564B2 (ja) * 2000-03-06 2011-04-06 アカディア ファーマシューティカルズ，インコーポレーテッド セロトニン関連疾患の治療に使用する含窒素環式化合物
JP2003110238A (ja) * 2001-09-28 2003-04-11 Murata Mfg Co Ltd ガラスセラミック多層基板の製造方法
JP4792726B2 (ja) * 2003-10-30 2011-10-12 日亜化学工業株式会社 半導体素子用支持体の製造方法
US7446827B2 (en) * 2004-10-15 2008-11-04 3M Innovative Properties Company Direct-lit liquid crystal displays with laminated diffuser plates
CN100455162C (zh) * 2004-11-05 2009-01-21 日月光半导体制造股份有限公司 电路板的制造方法
JP2007324277A (ja) * 2006-05-31 2007-12-13 Sumitomo Metal Electronics Devices Inc セラミック回路基板集合体
WO2008066133A1 (en) * 2006-11-30 2008-06-05 Tokuyama Corporation Method for manufacturing metallized ceramic substrate chip
JP5169086B2 (ja) * 2007-09-10 2013-03-27 山一電機株式会社 プローブコンタクトの製造方法
EP2357877B1 (en) * 2008-10-31 2018-06-27 Taiyo Yuden Co., Ltd. Method for manufacturing a printed wiring board
JP5567445B2 (ja) * 2010-10-08 2014-08-06 スタンレー電気株式会社 セラミック多層配線基板の製造方法
JP2013207065A (ja) * 2012-03-28 2013-10-07 Denso Corp セラミック基板の製造方法
EP3217428B1 (de) * 2016-03-07 2022-09-07 Infineon Technologies AG Mehrfachsubstrat sowie verfahren zu dessen herstellung

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS569008B2 (fi) 1973-06-25 1981-02-26
JPS60172357A (ja) 1984-02-18 1985-09-05 大西　久俊 ベストサンド
JPS61229389A (ja) * 1985-04-03 1986-10-13 イビデン株式会社 セラミツク配線板およびその製造方法
US5045141A (en) * 1988-07-01 1991-09-03 Amoco Corporation Method of making solderable printed circuits formed without plating
US5128737A (en) * 1990-03-02 1992-07-07 Silicon Dynamics, Inc. Semiconductor integrated circuit fabrication yield improvements
JPH09117910A (ja) 1995-10-25 1997-05-06 Murata Mfg Co Ltd 電子部品用基板の製造方法
US5994762A (en) * 1996-07-26 1999-11-30 Hitachi, Ltd. Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof
JPH1131881A (ja) 1997-07-11 1999-02-02 Sumitomo Kinzoku Electro Device:Kk セラミック多層基板
US6235612B1 (en) * 1998-06-10 2001-05-22 Texas Instruments Incorporated Edge bond pads on integrated circuits

Also Published As

Publication number Publication date
JP2001251024A (ja) 2001-09-14
US7162794B2 (en) 2007-01-16
SE0100413D0 (sv) 2001-02-09
CN1165209C (zh) 2004-09-01
US6621010B2 (en) 2003-09-16
SE0100413L (sv) 2001-09-04
FI118623B (fi) 2008-01-15
US20010018983A1 (en) 2001-09-06
SE524327C2 (sv) 2004-07-27
JP3700524B2 (ja) 2005-09-28
FI20010401A0 (fi) 2001-02-28
CN1322105A (zh) 2001-11-14
US20030167629A1 (en) 2003-09-11

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