DE60227890D1 - Umgossene Leiterplatte mit unterfülltem oberflächenmontierten Bauelement und Herstellungsverfahren - Google Patents
Umgossene Leiterplatte mit unterfülltem oberflächenmontierten Bauelement und HerstellungsverfahrenInfo
- Publication number
- DE60227890D1 DE60227890D1 DE60227890T DE60227890T DE60227890D1 DE 60227890 D1 DE60227890 D1 DE 60227890D1 DE 60227890 T DE60227890 T DE 60227890T DE 60227890 T DE60227890 T DE 60227890T DE 60227890 D1 DE60227890 D1 DE 60227890D1
- Authority
- DE
- Germany
- Prior art keywords
- underfilled
- circuit board
- printed circuit
- manufacturing process
- mounted device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/948,147 US6693239B2 (en) | 2001-09-06 | 2001-09-06 | Overmolded circuit board with underfilled surface-mount component and method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60227890D1 true DE60227890D1 (de) | 2008-09-11 |
Family
ID=25487359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60227890T Expired - Lifetime DE60227890D1 (de) | 2001-09-06 | 2002-08-21 | Umgossene Leiterplatte mit unterfülltem oberflächenmontierten Bauelement und Herstellungsverfahren |
Country Status (3)
Country | Link |
---|---|
US (1) | US6693239B2 (de) |
EP (1) | EP1291912B1 (de) |
DE (1) | DE60227890D1 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7339276B2 (en) * | 2002-11-04 | 2008-03-04 | Intel Corporation | Underfilling process in a molded matrix array package using flow front modifying solder resist |
US6991969B2 (en) * | 2003-02-19 | 2006-01-31 | Octavian Scientific, Inc. | Methods and apparatus for addition of electrical conductors to previously fabricated device |
US20050011672A1 (en) * | 2003-07-17 | 2005-01-20 | Alawani Ashish D. | Overmolded MCM with increased surface mount component reliability |
US7553680B2 (en) * | 2004-08-09 | 2009-06-30 | Delphi Technologies, Inc. | Methods to provide and expose a diagnostic connector on overmolded electronic packages |
US7230829B2 (en) * | 2005-01-28 | 2007-06-12 | Delphi Technologies, Inc. | Overmolded electronic assembly with insert molded heat sinks |
US7422448B2 (en) * | 2005-07-28 | 2008-09-09 | Delphi Technologies, Inc. | Surface mount connector |
WO2007015683A1 (en) * | 2005-08-04 | 2007-02-08 | Infineon Technologies Ag | An integrated circuit package and a method for forming an integrated circuit package |
US7579215B2 (en) * | 2007-03-30 | 2009-08-25 | Motorola, Inc. | Method for fabricating a low cost integrated circuit (IC) package |
US20100066395A1 (en) | 2008-03-13 | 2010-03-18 | Johnson Morgan T | Wafer Prober Integrated With Full-Wafer Contacter |
US8342228B2 (en) * | 2008-11-24 | 2013-01-01 | Apple Inc. | Systems and methods for insert-molding |
US7999197B1 (en) * | 2009-04-20 | 2011-08-16 | Rf Micro Devices, Inc. | Dual sided electronic module |
KR101934917B1 (ko) * | 2012-08-06 | 2019-01-04 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
JP6044473B2 (ja) * | 2013-06-28 | 2016-12-14 | 株式会社デンソー | 電子装置およびその電子装置の製造方法 |
JP7135293B2 (ja) * | 2017-10-25 | 2022-09-13 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US10971439B2 (en) | 2018-02-22 | 2021-04-06 | Hamilton Sundstrand Corporation | Ball grid array underfilling systems |
US11152295B2 (en) * | 2018-04-13 | 2021-10-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and method for manufacturing the same |
DE102019215696A1 (de) * | 2019-10-11 | 2021-04-15 | Continental Teves Ag & Co. Ohg | Elektronikeinheit mit verbesserter Kühlung |
CN113394118B (zh) * | 2020-03-13 | 2022-03-18 | 长鑫存储技术有限公司 | 封装结构及其形成方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5612576A (en) * | 1992-10-13 | 1997-03-18 | Motorola | Self-opening vent hole in an overmolded semiconductor device |
US5385869A (en) * | 1993-07-22 | 1995-01-31 | Motorola, Inc. | Semiconductor chip bonded to a substrate and method of making |
US5710071A (en) * | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
US6038136A (en) * | 1997-10-29 | 2000-03-14 | Hestia Technologies, Inc. | Chip package with molded underfill |
JP2000150730A (ja) * | 1998-11-17 | 2000-05-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6490166B1 (en) * | 1999-06-11 | 2002-12-03 | Intel Corporation | Integrated circuit package having a substrate vent hole |
JP2001044137A (ja) * | 1999-08-04 | 2001-02-16 | Hitachi Ltd | 電子装置及びその製造方法 |
US6519844B1 (en) * | 2001-08-27 | 2003-02-18 | Lsi Logic Corporation | Overmold integrated circuit package |
-
2001
- 2001-09-06 US US09/948,147 patent/US6693239B2/en not_active Expired - Lifetime
-
2002
- 2002-08-21 DE DE60227890T patent/DE60227890D1/de not_active Expired - Lifetime
- 2002-08-21 EP EP02078469A patent/EP1291912B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1291912B1 (de) | 2008-07-30 |
EP1291912A3 (de) | 2005-01-12 |
US6693239B2 (en) | 2004-02-17 |
US20030042035A1 (en) | 2003-03-06 |
EP1291912A2 (de) | 2003-03-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |