US7288843B2 - Integrated circuit chip support substrate for placing in a mold, and associated method - Google Patents
Integrated circuit chip support substrate for placing in a mold, and associated method Download PDFInfo
- Publication number
- US7288843B2 US7288843B2 US10/470,320 US47032003A US7288843B2 US 7288843 B2 US7288843 B2 US 7288843B2 US 47032003 A US47032003 A US 47032003A US 7288843 B2 US7288843 B2 US 7288843B2
- Authority
- US
- United States
- Prior art keywords
- substrate
- integrated circuit
- metal layer
- mounting face
- injection mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title description 3
- 239000002184 metal Substances 0.000 claims abstract description 35
- 238000002347 injection Methods 0.000 claims abstract description 22
- 239000007924 injection Substances 0.000 claims abstract description 22
- 238000005538 encapsulation Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 12
- 239000007789 gas Substances 0.000 claims abstract description 11
- 238000013022 venting Methods 0.000 claims abstract description 9
- 238000000465 moulding Methods 0.000 claims abstract description 3
- 239000002966 varnish Substances 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000011368 organic material Substances 0.000 claims 1
- 238000001746 injection moulding Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a substrate, and in particular, to an organic substrate supporting at least one integrated circuit chip (IC chip) and which is suitable for placing in an injection mold to encapsulate the IC chip in encapsulation material.
- IC chip integrated circuit chip
- rows of IC chips are mounted on a common substrate and encapsulated in a block of encapsulation material. The entire assembly is then cut to form individual packages. Each individual package contains an IC chip.
- the injection molds include vents made by slots above the face for mounting the IC chips on the substrates.
- the vents serve for venting the gases formed during injection of the encapsulation material.
- the width of the slots is determined by the encapsulation material to be injected, and more particularly, according to the dimensions of the filler particles in the encapsulation material. The tendency is to provide slots with narrower and narrower widths.
- the venting of gases during the injection of the encapsulation material is becoming more difficult, especially when the mounting face of the substrates is covered with a varnish layer.
- An object of the present invention is to improve the venting of gases during injection of the encapsulation material while simultaneously reducing the width of the gas venting slots.
- the substrate in particular, a multilayer organic substrate comprising a mounting and electrical-connection support, includes a mounting face for mounting at least one IC chip.
- the substrate including the IC chip is capable of being placed in the injection mold comprising two parts.
- the two parts of the injection mold surround the periphery of the substrate.
- One part of the injection mold may create a cavity for molding the encapsulation material to encapsulate the IC chip and may include a bearing face for bearing on the IC mounting face. At least one recess is preferably formed in the bearing face for defining a slot for venting gases.
- the mounting face of the substrate preferably includes a region on which a metal outer layer is provided.
- the metal outer layer may extend along the recess and onto the bearing face on both sides of the recess.
- the metal outer layer preferably comprises a strip which at least covers the recess.
- the metal outer layer also preferably extends without interruption.
- the metal outer layer may be added onto the region.
- the metal outer layer may also be integrated into the region.
- the substrate mounting face may advantageously be covered with a varnish layer which does not cover the metal outer layer.
- the metal outer layer preferably extends outside of the region covered by the IC chip.
- the substrate may be suitable for mounting at least one row of spaced-apart IC chips.
- the metal outer layer extends along the at least one row of IC chips.
- FIG. 1 shows a top view of a substrate including rows of IC chips, in accordance with the present invention
- FIG. 2 shows an enlarged cross-sectional view taken along line II-II as shown in FIG. 1 ;
- FIG. 3 shows a cross-sectional view of an injection mold suitable for accommodating the substrate including the IC chips, in accordance with the present invention.
- FIG. 4 shows a cross-sectional view taken along line IV-IV as shown in FIG. 3 .
- a substrate 1 shaped as a rectangular plate is shown.
- an organic substrate in the form of a multilayer strip that includes a mounting face 2 for mounting a plurality of IC chips 3 is illustrated.
- the IC chips 3 are grouped together forming four spaced-apart packets 4 and distributed over the length of the substrate 1 .
- Each packet 4 comprises a matrix of sixteen IC chips spaced apart and distributed to form longitudinal rows and transverse rows.
- the IC chips 3 are attached to the mounting face 2 via metal balls 3 a that furthermore connect the IC chips and an integrated connection network (not shown) on the substrate 1 .
- the substrate 1 includes, on the mounting face 2 and between a longitudinal edge 5 and a first longitudinal row of IC chips 3 placed a certain distance from the longitudinal edge 5 , four regions including metal outer layers 6 .
- the metal outer layers 6 form longitudinal rectangular strips extending, respectively, over the approximate length of the packets 4 and outside of the region covered by the IC chips 3 .
- the metal outer layers 6 may be added onto the mounting face 6 before the IC chips 3 are attached. In another embodiment, the metal outer layers 6 may be formed during the process of fabricating the multilayer substrate 1 .
- the mounting face 2 of the substrate 1 is covered with an oxidation-resistant varnish layer 7 .
- the varnish layer 7 does not cover the surface of the metal outer layers 6 .
- FIGS. 3 and 4 show an injection mold 8 comprising a lower part 9 and an upper part 10 which are suitable for bearing against each other.
- Each part 9 , 10 includes a bearing face 11 , 12 to bear against each other.
- the lower part 9 includes a cavity 13 which is hollowed out in its bearing face 11 and has dimensions to accommodate the substrate 1 with the IC chips 3 .
- the IC chips 3 are placed face-up and the metal outer layers 6 of the substrate 1 run along the longitudinal edge 14 of the cavity 13 and are also positioned face-up.
- the upper part 10 of the mold 8 has four flat cavities 15 hollowed out in its bearing face 12 .
- the four flat cavities are formed so that when the upper part 10 of the mold 8 bears on the lower part 9 of the mold, the cavities 15 define injection molding chambers.
- the injection molding chambers surround, some distance away, the packets 4 of IC chips 3 .
- the bearing face 12 of the upper part 10 of the mold 1 bears on the peripheral region of the mounting face 2 of the substrate 1 and between the packets 4 of IC chips 3 .
- the bearing face 12 of the upper part 10 of the mold 8 has a plurality of recesses 16 , 18 which define, above the mounting face 2 of the substrate 1 , slots 17 forming vents for venting gases.
- the slots are positioned transverse to the substrate 1 , and open into the cavities 15 on one side and open outside the cavity 15 on the opposite side.
- the recesses 16 define the transverse slots 17 .
- the metal outer layers 6 carried by the substrate 1 are respectively placed so that the metal outer layers 6 extend along the recesses 16 and at least cover the recess 16 so that the metal outer layers 6 extend over the bearing faces 11 , 12 on either side of the slots 17 .
- the metal outer layers 6 slightly extend into the cavities 15 .
- the varnish layer 7 which covers the mounting face 2 of the substrate 1 , projects slightly over the surface of the metal outer layers 6 , the varnish layer 7 will not reach the slots 17 .
- the bearing face 12 of the upper part 10 of the mold 8 includes a plurality of recesses 18 .
- the recesses 18 define, above the mounting face 2 of the substrate 1 , injection slots 19 .
- the injection slots 19 open into the side of the cavities 14 on one side, and are connected to a device for injecting the encapsulation material on the other side.
- the gases may be vented because the gas venting slots 17 are perfectly defined.
- the slots 17 are formed by the recesses 16 created in the bearing face 12 of the upper part 10 of the mold 8 and by the metal outer layers 6 located on the mounting face 2 of the substrate 1 .
- the metal outer layers 6 are provided on the mounting face 2 of the substrate 1 independent of the surface finish of the mounting face 2 of the substrate 1 in its other regions and independent of the varnish layer 7 .
- the metal outer layer 6 is a relatively rigid plate that is held in place on either side of the respective recess 16 defining the slot 17 .
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0101096 | 2001-01-26 | ||
FR0101096A FR2820240B1 (fr) | 2001-01-26 | 2001-01-26 | Substrat support de puce a circuits integres adapte pour etre place dans un moule |
PCT/FR2002/000297 WO2002059959A1 (fr) | 2001-01-26 | 2002-01-24 | Substrat support de puce a circuits integres adapte pour etre place dans un moule |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040075191A1 US20040075191A1 (en) | 2004-04-22 |
US7288843B2 true US7288843B2 (en) | 2007-10-30 |
Family
ID=8859292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/470,320 Expired - Lifetime US7288843B2 (en) | 2001-01-26 | 2002-01-24 | Integrated circuit chip support substrate for placing in a mold, and associated method |
Country Status (3)
Country | Link |
---|---|
US (1) | US7288843B2 (fr) |
FR (1) | FR2820240B1 (fr) |
WO (1) | WO2002059959A1 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090224382A1 (en) * | 2008-03-04 | 2009-09-10 | Infineon Technologies Ag | Semiconductor package with mold lock vent |
US9129978B1 (en) | 2014-06-24 | 2015-09-08 | Stats Chippac Ltd. | Integrated circuit packaging system with void prevention mechanism and method of manufacture thereof |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2820240B1 (fr) | 2001-01-26 | 2004-07-16 | St Microelectronics Sa | Substrat support de puce a circuits integres adapte pour etre place dans un moule |
US7618249B2 (en) * | 2006-09-22 | 2009-11-17 | Asm Technology Singapore Pte Ltd. | Memory card molding apparatus and process |
CN207398072U (zh) * | 2017-06-05 | 2018-05-22 | 日月光半导体制造股份有限公司 | 用于半导体封装制程的封装模具 |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5612576A (en) | 1992-10-13 | 1997-03-18 | Motorola | Self-opening vent hole in an overmolded semiconductor device |
US5998243A (en) | 1997-10-15 | 1999-12-07 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device and apparatus for resin-encapsulating |
US6081997A (en) | 1997-08-14 | 2000-07-04 | Lsi Logic Corporation | System and method for packaging an integrated circuit using encapsulant injection |
US6087202A (en) * | 1997-06-03 | 2000-07-11 | Stmicroelectronics S.A. | Process for manufacturing semiconductor packages comprising an integrated circuit |
US6114192A (en) | 1994-02-10 | 2000-09-05 | Hitachi, Ltd. | Method of manufacturing a semiconductor device having a ball grid array package structure using a supporting frame |
US6413801B1 (en) * | 2000-05-02 | 2002-07-02 | Advanced Semiconductor Engineering, Inc. | Method of molding semiconductor device and molding die for use therein |
WO2002059959A1 (fr) | 2001-01-26 | 2002-08-01 | Stmicroelectronics Sa | Substrat support de puce a circuits integres adapte pour etre place dans un moule |
US6632704B2 (en) * | 2000-12-19 | 2003-10-14 | Intel Corporation | Molded flip chip package |
US6645792B2 (en) * | 2001-06-27 | 2003-11-11 | Matsushita Electric Industrial Co., Ltd. | Lead frame and method for fabricating resin-encapsulated semiconductor device |
US6767767B2 (en) * | 2001-08-31 | 2004-07-27 | Renesas Technology Corp. | Method of manufacturing a semiconductor device in which a block molding package utilizes air vents in a substrate |
US6830954B2 (en) * | 2000-08-31 | 2004-12-14 | Micron Technology, Inc. | Transfer molding and underfilling method and apparatus |
US6858933B2 (en) * | 2000-05-22 | 2005-02-22 | Stmicroelectronics S.A. | Injection mold for an optical semiconductor package and corresponding optical semiconductor package |
US6867487B2 (en) * | 2001-05-29 | 2005-03-15 | Siliconware Precision Industries Co., Ltd. | Flash-preventing semiconductor package |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2954148B1 (ja) * | 1998-03-25 | 1999-09-27 | 松下電子工業株式会社 | 樹脂封止型半導体装置の製造方法およびその製造装置 |
JPH11297921A (ja) * | 1998-04-14 | 1999-10-29 | Mitsubishi Electric Corp | 半導体装置用フレームおよびその製造方法並びに半導体装置用フレームを用いた半導体装置の製造方法 |
-
2001
- 2001-01-26 FR FR0101096A patent/FR2820240B1/fr not_active Expired - Fee Related
-
2002
- 2002-01-24 WO PCT/FR2002/000297 patent/WO2002059959A1/fr not_active Application Discontinuation
- 2002-01-24 US US10/470,320 patent/US7288843B2/en not_active Expired - Lifetime
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5612576A (en) | 1992-10-13 | 1997-03-18 | Motorola | Self-opening vent hole in an overmolded semiconductor device |
US6114192A (en) | 1994-02-10 | 2000-09-05 | Hitachi, Ltd. | Method of manufacturing a semiconductor device having a ball grid array package structure using a supporting frame |
US6087202A (en) * | 1997-06-03 | 2000-07-11 | Stmicroelectronics S.A. | Process for manufacturing semiconductor packages comprising an integrated circuit |
US6081997A (en) | 1997-08-14 | 2000-07-04 | Lsi Logic Corporation | System and method for packaging an integrated circuit using encapsulant injection |
US5998243A (en) | 1997-10-15 | 1999-12-07 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device and apparatus for resin-encapsulating |
US6413801B1 (en) * | 2000-05-02 | 2002-07-02 | Advanced Semiconductor Engineering, Inc. | Method of molding semiconductor device and molding die for use therein |
US6858933B2 (en) * | 2000-05-22 | 2005-02-22 | Stmicroelectronics S.A. | Injection mold for an optical semiconductor package and corresponding optical semiconductor package |
US6838319B1 (en) * | 2000-08-31 | 2005-01-04 | Micron Technology, Inc. | Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically |
US6830954B2 (en) * | 2000-08-31 | 2004-12-14 | Micron Technology, Inc. | Transfer molding and underfilling method and apparatus |
US6863516B2 (en) * | 2000-08-31 | 2005-03-08 | Micron Technology, Inc. | Transfer molding and underfilling apparatus |
US6838313B2 (en) * | 2000-12-19 | 2005-01-04 | Intel Corporation | Molded flip chip package |
US6632704B2 (en) * | 2000-12-19 | 2003-10-14 | Intel Corporation | Molded flip chip package |
WO2002059959A1 (fr) | 2001-01-26 | 2002-08-01 | Stmicroelectronics Sa | Substrat support de puce a circuits integres adapte pour etre place dans un moule |
US6867487B2 (en) * | 2001-05-29 | 2005-03-15 | Siliconware Precision Industries Co., Ltd. | Flash-preventing semiconductor package |
US6645792B2 (en) * | 2001-06-27 | 2003-11-11 | Matsushita Electric Industrial Co., Ltd. | Lead frame and method for fabricating resin-encapsulated semiconductor device |
US6767767B2 (en) * | 2001-08-31 | 2004-07-27 | Renesas Technology Corp. | Method of manufacturing a semiconductor device in which a block molding package utilizes air vents in a substrate |
Non-Patent Citations (2)
Title |
---|
Patent Abstracts of Japan, Inventor: Sawai Akiyoshi, "Frame for Semiconductor Device and Manufacture Thereof, and Manufacture of Semiconductor Device Using Frame Therefor", Publication No. 11297921, Publication Date: Oct. 29, 1999. |
Patent Abstracts of Japan, Inventor: Yamada Yasuhiro, "Method and Apparatus for Manufacturing Resin Encapsulated Semiconductor Device", Publication No. 11274195, Publication Date: Oct. 8, 1999. |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090224382A1 (en) * | 2008-03-04 | 2009-09-10 | Infineon Technologies Ag | Semiconductor package with mold lock vent |
US7732937B2 (en) | 2008-03-04 | 2010-06-08 | Infineon Technologies Ag | Semiconductor package with mold lock vent |
US20100227436A1 (en) * | 2008-03-04 | 2010-09-09 | Infineon Technologies Ag | Method of fabricating a semiconductor package with mold lock opening |
US8466009B2 (en) | 2008-03-04 | 2013-06-18 | Infineon Technologies Ag | Method of fabricating a semiconductor package with mold lock opening |
US9129978B1 (en) | 2014-06-24 | 2015-09-08 | Stats Chippac Ltd. | Integrated circuit packaging system with void prevention mechanism and method of manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
FR2820240B1 (fr) | 2004-07-16 |
US20040075191A1 (en) | 2004-04-22 |
FR2820240A1 (fr) | 2002-08-02 |
WO2002059959A1 (fr) | 2002-08-01 |
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