KR910019218A - 보로실리케이트 유리스페이서를 갖는 반도체 디바이스 및 그 제조 방법 - Google Patents

보로실리케이트 유리스페이서를 갖는 반도체 디바이스 및 그 제조 방법 Download PDF

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KR910019218A
KR910019218A KR1019910005082A KR910005082A KR910019218A KR 910019218 A KR910019218 A KR 910019218A KR 1019910005082 A KR1019910005082 A KR 1019910005082A KR 910005082 A KR910005082 A KR 910005082A KR 910019218 A KR910019218 A KR 910019218A
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지. 솔혜임 알란
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존 지. 웨브
내쇼날 세미컨덕터 코포레이션
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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Abstract

내용 없음

Description

보로실리케이트 유리스페이서를 갖는 반도체 디바이스 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 발명의 한 구체 예에 따른 BICMOS구조의 단면도이다.

Claims (11)

  1. 반도체 구조내에 P+확산 영역 및 측벽 스페이서 영역을 형성하는 방법에 있어서, 최소한 하나의 제 1 측벽부분을 각기 지니는 복수의 폴리실리콘 영역등을 기판 표면상에 제공하는 단계, 상기 복수의 폴리실리콘 영역중 최소한한 부분위에 보로 실리케이트 유리층을 데포지트 하는 단계, 상기 보로실리케이트 유리층의 선택 부분을 에칭하여 상기 최소한 하나의 측벽 부분에 인접한 보로실리케이트 유리 스페이서를 제공하는 단계, 상기 기판, 폴리실리콘 및 스페이서를 어닐링하여 상기 보로실리게이트 유리로부터 상기 기판의 인접 부분까지 P형 도판트의 확산을 야기하여 확산 영역을 형성하는 단계로 이루어지는 방법.
  2. 제 1 항에 있어서, 상기 기판 부분들을 선택적으로 도핑하여 바이폴과 디바이스의 에미터, 컬렉터 및 베이스 영역을 형성하는 단계를 또한 포함하며, 상기 확산 영역이 상기 베이스 영역의 최소한 일부분을 형성하는 방법.
  3. 제 1 항에 있어서, 상기 기판 부분들을 선택적으로 도핑하여 상기 기판에 소오스, 드레인 및 채널 영역을 형성하는 단계를 또한 포함하며, 상기 확산 영역은 하나의 최소한 일부분을 형성하는 방법.
  4. 최소한 일부분이 기판의 표면에 인접한 최소한 제 1 의 능동 영역을 가지는 기판을 제공하는 단계, 최소한 하나의 제1측벽 부분을 가지고 있는 상기 활성 영역의 노출 지역에 인접한 최소한 하나의 제1폴리실리콘 영역을 상기 능동 영역의 상기 부분에 인접하여 상기 기판의 표면상에 제공하는 단계, 최소한 일부가 상기 노출 지역의 최소한 일부를 덮어서 최소한 상기 기판, 상기 제 1 폴리실리콘 영역 및 보로실리케이트 유리의 상기 층의 상기 부분을 포함하는 구조를 형성하는 보로실리케이트 유리의 층을 데포지트 하는 단계 및, 상기 구조의 최소한 일부를 가열하여 P형 도판트를 상기 보로실리케이트 유리로부터 상기 보로실리케이트 유리층에 인접한 상기 능동영역의 최소한 일부분내로 확산시키고 P형 도판트의 확산을 수용하는 상기 능동 영역의 상기 부분이 도판트가 풍부해지는 단계를 포함하는 트랜지스터 형성방법.
  5. 제 4 항에 있어서, 상기 능동 영역이 바이폴라 디바이스의 베이스 영역인 방법.
  6. 제 4 항에 있어서, 상기 능동 영역이 전계 효과 디바이스의 소오스 영역과 드레인 영역중 한 영역인 방법.
  7. 제 4 항에 있어서, 상기 보로 실리케이트 유리층의 부분들을 에칭하여 상기 측벽 부분들중 최소한 한 부분상에 보로실리케이트 유리 스페이서를 제공하는 단계를 또한 포함하는 방법.
  8. 제 4 항에 있어서, 최소한 상기기판의 선택된 일부분 및 상기 제 1 폴리실리콘 영역과 제 2 폴리 실리콘 영역중 최소한 한 영역에 고융점 금속 실리사이드 층을 형성하는 단계를 또한 포함하는 방법.
  9. 표면에 인접하여 최소한 하나의 제 1 의 P도핑 영역을 가지는 기판, 상기 기판의 표면상에 형성되고 최소한 하나의 제 1 측벽을 가지는 도핑된 폴리실리콘 영역 및, 상기 폴리실리콘 측벽에 인접한 최소한 하나의 제1측벽 스페이서로서 보로 실리케이트 유리를 포함하고, 상기 P도핑 영역내의 도판트의 최소한 일부가 상기 측벽 스페이서로부터 확산된 도판트인 반도체 구조체.
  10. 제 9 항에 있어서, 상기 P도핑 영역이 바이폴라 트랜지스터의 베이스 영역인 구조체.
  11. 제 9 항에 있어서, 상기 P도핑 영역이 전계효과 트랜지스터의 소오스영역과 드레인 영역중 한 영역인 구조체.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
KR1019910005082A 1990-04-02 1991-03-30 보로실리케이트 유리 스페이서를 갖는 반도체 디바이스 및 그 제조방법 KR100227874B1 (ko)

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EP0450503A3 (en) 1992-05-20
JPH0645343A (ja) 1994-02-18
US5443994A (en) 1995-08-22
KR100227874B1 (ko) 1999-11-01
EP0450503A2 (en) 1991-10-09

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